2 * $Id: synclinkmp.c,v 4.29 2004/08/27 20:06:41 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/config.h>
38 #include <linux/module.h>
39 #include <linux/errno.h>
40 #include <linux/signal.h>
41 #include <linux/sched.h>
42 #include <linux/timer.h>
43 #include <linux/interrupt.h>
44 #include <linux/pci.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial.h>
48 #include <linux/major.h>
49 #include <linux/string.h>
50 #include <linux/fcntl.h>
51 #include <linux/ptrace.h>
52 #include <linux/ioport.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <asm/serial.h>
59 #include <linux/delay.h>
60 #include <linux/ioctl.h>
62 #include <asm/system.h>
66 #include <asm/bitops.h>
67 #include <asm/types.h>
68 #include <linux/termios.h>
69 #include <linux/workqueue.h>
70 #include <linux/hdlc.h>
72 #ifdef CONFIG_HDLC_MODULE
76 #define GET_USER(error,value,addr) error = get_user(value,addr)
77 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
78 #define PUT_USER(error,value,addr) error = put_user(value,addr)
79 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81 #include <asm/uaccess.h>
83 #include "linux/synclink.h"
85 static MGSL_PARAMS default_params = {
86 MGSL_MODE_HDLC, /* unsigned long mode */
87 0, /* unsigned char loopback; */
88 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
89 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
90 0, /* unsigned long clock_speed; */
91 0xff, /* unsigned char addr_filter; */
92 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
93 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
94 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
95 9600, /* unsigned long data_rate; */
96 8, /* unsigned char data_bits; */
97 1, /* unsigned char stop_bits; */
98 ASYNC_PARITY_NONE /* unsigned char parity; */
101 /* size in bytes of DMA data buffers */
102 #define SCABUFSIZE 1024
103 #define SCA_MEM_SIZE 0x40000
104 #define SCA_BASE_SIZE 512
105 #define SCA_REG_SIZE 16
106 #define SCA_MAX_PORTS 4
107 #define SCAMAXDESC 128
109 #define BUFFERLISTSIZE 4096
111 /* SCA-I style DMA buffer descriptor */
112 typedef struct _SCADESC
114 u16 next; /* lower l6 bits of next descriptor addr */
115 u16 buf_ptr; /* lower 16 bits of buffer addr */
116 u8 buf_base; /* upper 8 bits of buffer addr */
118 u16 length; /* length of buffer */
119 u8 status; /* status of buffer */
121 } SCADESC, *PSCADESC;
123 typedef struct _SCADESC_EX
125 /* device driver bookkeeping section */
126 char *virt_addr; /* virtual address of data buffer */
127 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
128 } SCADESC_EX, *PSCADESC_EX;
130 /* The queue of BH actions to be performed */
133 #define BH_TRANSMIT 2
136 #define IO_PIN_SHUTDOWN_LIMIT 100
138 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
140 struct _input_signal_events {
152 * Device instance data structure
154 typedef struct _synclinkmp_info {
155 void *if_ptr; /* General purpose pointer (used by SPPP) */
158 int count; /* count of opens */
160 unsigned short close_delay;
161 unsigned short closing_wait; /* time to wait before closing */
163 struct mgsl_icount icount;
165 struct tty_struct *tty;
167 int x_char; /* xon/xoff character */
168 int blocked_open; /* # of blocked opens */
169 u16 read_status_mask1; /* break detection (SR1 indications) */
170 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
171 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
172 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
173 unsigned char *tx_buf;
178 wait_queue_head_t open_wait;
179 wait_queue_head_t close_wait;
181 wait_queue_head_t status_event_wait_q;
182 wait_queue_head_t event_wait_q;
183 struct timer_list tx_timer; /* HDLC transmit timeout timer */
184 struct _synclinkmp_info *next_device; /* device list link */
185 struct timer_list status_timer; /* input signal status check timer */
187 spinlock_t lock; /* spinlock for synchronizing with ISR */
188 struct work_struct task; /* task structure for scheduling bh */
190 u32 max_frame_size; /* as set by device config */
194 int bh_running; /* Protection from multiple */
198 int dcd_chkcount; /* check counts to prevent */
199 int cts_chkcount; /* too many IRQs if a signal */
200 int dsr_chkcount; /* is floating */
203 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
204 unsigned long buffer_list_phys;
206 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
207 SCADESC *rx_buf_list; /* list of receive buffer entries */
208 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
209 unsigned int current_rx_buf;
211 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
212 SCADESC *tx_buf_list; /* list of transmit buffer entries */
213 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
214 unsigned int last_tx_buf;
216 unsigned char *tmp_rx_buf;
217 unsigned int tmp_rx_buf_count;
226 unsigned char ie0_value;
227 unsigned char ie1_value;
228 unsigned char ie2_value;
229 unsigned char ctrlreg_value;
230 unsigned char old_signals;
232 char device_name[25]; /* device instance name */
238 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
240 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
242 unsigned int irq_level; /* interrupt level */
243 unsigned long irq_flags;
244 int irq_requested; /* nonzero if IRQ requested */
246 MGSL_PARAMS params; /* communications parameters */
248 unsigned char serial_signals; /* current serial signal states */
250 int irq_occurred; /* for diagnostics use */
251 unsigned int init_error; /* Initialization startup error */
254 unsigned char* memory_base; /* shared memory address (PCI only) */
255 u32 phys_memory_base;
256 int shared_mem_requested;
258 unsigned char* sca_base; /* HD64570 SCA Memory address */
261 int sca_base_requested;
263 unsigned char* lcr_base; /* local config registers (PCI only) */
266 int lcr_mem_requested;
268 unsigned char* statctrl_base; /* status/control register memory */
269 u32 phys_statctrl_base;
271 int sca_statctrl_requested;
274 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
275 char char_buf[MAX_ASYNC_BUFFER_SIZE];
276 BOOLEAN drop_rts_on_tx_done;
278 struct _input_signal_events input_signal_events;
280 /* SPPP/Cisco HDLC device parts */
286 struct net_device *netdev;
291 #define MGSL_MAGIC 0x5401
294 * define serial signal status change macros
296 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
297 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
298 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
299 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
301 /* Common Register macros */
320 /* MSCI Register macros */
350 /* Timer Register Macros */
360 /* DMA Controller Register macros */
391 /* combine with timer or DMA register address */
399 /* SCA Command Codes */
402 #define TXENABLE 0x02
403 #define TXDISABLE 0x03
404 #define TXCRCINIT 0x04
405 #define TXCRCEXCL 0x05
409 #define TXBUFCLR 0x09
411 #define RXENABLE 0x12
412 #define RXDISABLE 0x13
413 #define RXCRCINIT 0x14
414 #define RXREJECT 0x15
415 #define SEARCHMP 0x16
416 #define RXCRCEXCL 0x17
417 #define RXCRCCALC 0x18
421 /* DMA command codes */
423 #define FEICLEAR 0x02
457 * Global linked list of SyncLink devices
459 static SLMP_INFO *synclinkmp_device_list = NULL;
460 static int synclinkmp_adapter_count = -1;
461 static int synclinkmp_device_count = 0;
464 * Set this param to non-zero to load eax with the
465 * .text section address and breakpoint on module load.
466 * This is useful for use with gdb and add-symbol-file command.
468 static int break_on_load=0;
471 * Driver major number, defaults to zero to get auto
472 * assigned major number. May be forced as module parameter.
474 static int ttymajor=0;
477 * Array of user specified options for ISA adapters.
479 static int debug_level = 0;
480 static int maxframe[MAX_DEVICES] = {0,};
481 static int dosyncppp[MAX_DEVICES] = {0,};
483 MODULE_PARM(break_on_load,"i");
484 MODULE_PARM(ttymajor,"i");
485 MODULE_PARM(debug_level,"i");
486 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_DEVICES) "i");
487 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_DEVICES) "i");
489 static char *driver_name = "SyncLink MultiPort driver";
490 static char *driver_version = "$Revision: 4.29 $";
492 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
493 static void synclinkmp_remove_one(struct pci_dev *dev);
495 static struct pci_device_id synclinkmp_pci_tbl[] = {
496 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
497 { 0, }, /* terminate list */
499 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
501 MODULE_LICENSE("GPL");
503 static struct pci_driver synclinkmp_pci_driver = {
504 .name = "synclinkmp",
505 .id_table = synclinkmp_pci_tbl,
506 .probe = synclinkmp_init_one,
507 .remove = __devexit_p(synclinkmp_remove_one),
511 static struct tty_driver *serial_driver;
513 /* number of characters left in xmit buffer before we ask for more */
514 #define WAKEUP_CHARS 256
519 static int open(struct tty_struct *tty, struct file * filp);
520 static void close(struct tty_struct *tty, struct file * filp);
521 static void hangup(struct tty_struct *tty);
522 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
524 static int write(struct tty_struct *tty, int from_user, const unsigned char *buf, int count);
525 static void put_char(struct tty_struct *tty, unsigned char ch);
526 static void send_xchar(struct tty_struct *tty, char ch);
527 static void wait_until_sent(struct tty_struct *tty, int timeout);
528 static int write_room(struct tty_struct *tty);
529 static void flush_chars(struct tty_struct *tty);
530 static void flush_buffer(struct tty_struct *tty);
531 static void tx_hold(struct tty_struct *tty);
532 static void tx_release(struct tty_struct *tty);
534 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
535 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
536 static int chars_in_buffer(struct tty_struct *tty);
537 static void throttle(struct tty_struct * tty);
538 static void unthrottle(struct tty_struct * tty);
539 static void set_break(struct tty_struct *tty, int break_state);
542 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
543 static void hdlcdev_tx_done(SLMP_INFO *info);
544 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
545 static int hdlcdev_init(SLMP_INFO *info);
546 static void hdlcdev_exit(SLMP_INFO *info);
551 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
552 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
553 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
554 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
555 static int set_txidle(SLMP_INFO *info, int idle_mode);
556 static int tx_enable(SLMP_INFO *info, int enable);
557 static int tx_abort(SLMP_INFO *info);
558 static int rx_enable(SLMP_INFO *info, int enable);
559 static int map_status(int signals);
560 static int modem_input_wait(SLMP_INFO *info,int arg);
561 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
562 static int tiocmget(struct tty_struct *tty, struct file *file);
563 static int tiocmset(struct tty_struct *tty, struct file *file,
564 unsigned int set, unsigned int clear);
565 static void set_break(struct tty_struct *tty, int break_state);
567 static void add_device(SLMP_INFO *info);
568 static void device_init(int adapter_num, struct pci_dev *pdev);
569 static int claim_resources(SLMP_INFO *info);
570 static void release_resources(SLMP_INFO *info);
572 static int startup(SLMP_INFO *info);
573 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
574 static void shutdown(SLMP_INFO *info);
575 static void program_hw(SLMP_INFO *info);
576 static void change_params(SLMP_INFO *info);
578 static int init_adapter(SLMP_INFO *info);
579 static int register_test(SLMP_INFO *info);
580 static int irq_test(SLMP_INFO *info);
581 static int loopback_test(SLMP_INFO *info);
582 static int adapter_test(SLMP_INFO *info);
583 static int memory_test(SLMP_INFO *info);
585 static void reset_adapter(SLMP_INFO *info);
586 static void reset_port(SLMP_INFO *info);
587 static void async_mode(SLMP_INFO *info);
588 static void hdlc_mode(SLMP_INFO *info);
590 static void rx_stop(SLMP_INFO *info);
591 static void rx_start(SLMP_INFO *info);
592 static void rx_reset_buffers(SLMP_INFO *info);
593 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
594 static int rx_get_frame(SLMP_INFO *info);
596 static void tx_start(SLMP_INFO *info);
597 static void tx_stop(SLMP_INFO *info);
598 static void tx_load_fifo(SLMP_INFO *info);
599 static void tx_set_idle(SLMP_INFO *info);
600 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
602 static void get_signals(SLMP_INFO *info);
603 static void set_signals(SLMP_INFO *info);
604 static void enable_loopback(SLMP_INFO *info, int enable);
605 static void set_rate(SLMP_INFO *info, u32 data_rate);
607 static int bh_action(SLMP_INFO *info);
608 static void bh_handler(void* Context);
609 static void bh_receive(SLMP_INFO *info);
610 static void bh_transmit(SLMP_INFO *info);
611 static void bh_status(SLMP_INFO *info);
612 static void isr_timer(SLMP_INFO *info);
613 static void isr_rxint(SLMP_INFO *info);
614 static void isr_rxrdy(SLMP_INFO *info);
615 static void isr_txint(SLMP_INFO *info);
616 static void isr_txrdy(SLMP_INFO *info);
617 static void isr_rxdmaok(SLMP_INFO *info);
618 static void isr_rxdmaerror(SLMP_INFO *info);
619 static void isr_txdmaok(SLMP_INFO *info);
620 static void isr_txdmaerror(SLMP_INFO *info);
621 static void isr_io_pin(SLMP_INFO *info, u16 status);
623 static int alloc_dma_bufs(SLMP_INFO *info);
624 static void free_dma_bufs(SLMP_INFO *info);
625 static int alloc_buf_list(SLMP_INFO *info);
626 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
627 static int alloc_tmp_rx_buf(SLMP_INFO *info);
628 static void free_tmp_rx_buf(SLMP_INFO *info);
630 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
631 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
632 static void tx_timeout(unsigned long context);
633 static void status_timeout(unsigned long context);
635 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
636 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
637 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
638 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
639 static unsigned char read_status_reg(SLMP_INFO * info);
640 static void write_control_reg(SLMP_INFO * info);
643 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
644 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
645 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
647 static u32 misc_ctrl_value = 0x007e4040;
648 static u32 lcr1_brdr_value = 0x00800029;
650 static u32 read_ahead_count = 8;
652 /* DPCR, DMA Priority Control
654 * 07..05 Not used, must be 0
655 * 04 BRC, bus release condition: 0=all transfers complete
656 * 1=release after 1 xfer on all channels
657 * 03 CCC, channel change condition: 0=every cycle
658 * 1=after each channel completes all xfers
659 * 02..00 PR<2..0>, priority 100=round robin
663 static unsigned char dma_priority = 0x04;
665 // Number of bytes that can be written to shared RAM
666 // in a single write operation
667 static u32 sca_pci_load_interval = 64;
670 * 1st function defined in .text section. Calling this function in
671 * init_module() followed by a breakpoint allows a remote debugger
672 * (gdb) to get the .text address for the add-symbol-file command.
673 * This allows remote debugging of dynamically loadable modules.
675 static void* synclinkmp_get_text_ptr(void);
676 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
678 static inline int sanity_check(SLMP_INFO *info,
679 char *name, const char *routine)
682 static const char *badmagic =
683 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
684 static const char *badinfo =
685 "Warning: null synclinkmp_struct for (%s) in %s\n";
688 printk(badinfo, name, routine);
691 if (info->magic != MGSL_MAGIC) {
692 printk(badmagic, name, routine);
703 * line discipline callback wrappers
705 * The wrappers maintain line discipline references
706 * while calling into the line discipline.
708 * ldisc_receive_buf - pass receive data to line discipline
711 static void ldisc_receive_buf(struct tty_struct *tty,
712 const __u8 *data, char *flags, int count)
714 struct tty_ldisc *ld;
717 ld = tty_ldisc_ref(tty);
720 ld->receive_buf(tty, data, flags, count);
727 /* Called when a port is opened. Init and enable port.
729 static int open(struct tty_struct *tty, struct file *filp)
736 if ((line < 0) || (line >= synclinkmp_device_count)) {
737 printk("%s(%d): open with invalid line #%d.\n",
738 __FILE__,__LINE__,line);
742 info = synclinkmp_device_list;
743 while(info && info->line != line)
744 info = info->next_device;
745 if (sanity_check(info, tty->name, "open"))
747 if ( info->init_error ) {
748 printk("%s(%d):%s device is not allocated, init error=%d\n",
749 __FILE__,__LINE__,info->device_name,info->init_error);
753 tty->driver_data = info;
756 if (debug_level >= DEBUG_LEVEL_INFO)
757 printk("%s(%d):%s open(), old ref count = %d\n",
758 __FILE__,__LINE__,tty->driver->name, info->count);
760 /* If port is closing, signal caller to try again */
761 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
762 if (info->flags & ASYNC_CLOSING)
763 interruptible_sleep_on(&info->close_wait);
764 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
765 -EAGAIN : -ERESTARTSYS);
769 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
771 spin_lock_irqsave(&info->netlock, flags);
772 if (info->netcount) {
774 spin_unlock_irqrestore(&info->netlock, flags);
778 spin_unlock_irqrestore(&info->netlock, flags);
780 if (info->count == 1) {
781 /* 1st open on this device, init hardware */
782 retval = startup(info);
787 retval = block_til_ready(tty, filp, info);
789 if (debug_level >= DEBUG_LEVEL_INFO)
790 printk("%s(%d):%s block_til_ready() returned %d\n",
791 __FILE__,__LINE__, info->device_name, retval);
795 if (debug_level >= DEBUG_LEVEL_INFO)
796 printk("%s(%d):%s open() success\n",
797 __FILE__,__LINE__, info->device_name);
803 info->tty = NULL; /* tty layer will release tty struct */
811 /* Called when port is closed. Wait for remaining data to be
812 * sent. Disable port and free resources.
814 static void close(struct tty_struct *tty, struct file *filp)
816 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
818 if (sanity_check(info, tty->name, "close"))
821 if (debug_level >= DEBUG_LEVEL_INFO)
822 printk("%s(%d):%s close() entry, count=%d\n",
823 __FILE__,__LINE__, info->device_name, info->count);
828 if (tty_hung_up_p(filp))
831 if ((tty->count == 1) && (info->count != 1)) {
833 * tty->count is 1 and the tty structure will be freed.
834 * info->count should be one in this case.
835 * if it's not, correct it so that the port is shutdown.
837 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
838 "info->count is %d\n",
839 __FILE__,__LINE__, info->device_name, info->count);
845 /* if at least one open remaining, leave hardware active */
849 info->flags |= ASYNC_CLOSING;
851 /* set tty->closing to notify line discipline to
852 * only process XON/XOFF characters. Only the N_TTY
853 * discipline appears to use this (ppp does not).
857 /* wait for transmit data to clear all layers */
859 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
860 if (debug_level >= DEBUG_LEVEL_INFO)
861 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
862 __FILE__,__LINE__, info->device_name );
863 tty_wait_until_sent(tty, info->closing_wait);
866 if (info->flags & ASYNC_INITIALIZED)
867 wait_until_sent(tty, info->timeout);
869 if (tty->driver->flush_buffer)
870 tty->driver->flush_buffer(tty);
872 tty_ldisc_flush(tty);
879 if (info->blocked_open) {
880 if (info->close_delay) {
881 set_current_state(TASK_INTERRUPTIBLE);
882 schedule_timeout(info->close_delay);
884 wake_up_interruptible(&info->open_wait);
887 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
889 wake_up_interruptible(&info->close_wait);
892 if (debug_level >= DEBUG_LEVEL_INFO)
893 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
894 tty->driver->name, info->count);
897 /* Called by tty_hangup() when a hangup is signaled.
898 * This is the same as closing all open descriptors for the port.
900 static void hangup(struct tty_struct *tty)
902 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
904 if (debug_level >= DEBUG_LEVEL_INFO)
905 printk("%s(%d):%s hangup()\n",
906 __FILE__,__LINE__, info->device_name );
908 if (sanity_check(info, tty->name, "hangup"))
915 info->flags &= ~ASYNC_NORMAL_ACTIVE;
918 wake_up_interruptible(&info->open_wait);
921 /* Set new termios settings
923 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
925 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
928 if (debug_level >= DEBUG_LEVEL_INFO)
929 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
932 /* just return if nothing has changed */
933 if ((tty->termios->c_cflag == old_termios->c_cflag)
934 && (RELEVANT_IFLAG(tty->termios->c_iflag)
935 == RELEVANT_IFLAG(old_termios->c_iflag)))
940 /* Handle transition to B0 status */
941 if (old_termios->c_cflag & CBAUD &&
942 !(tty->termios->c_cflag & CBAUD)) {
943 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
944 spin_lock_irqsave(&info->lock,flags);
946 spin_unlock_irqrestore(&info->lock,flags);
949 /* Handle transition away from B0 status */
950 if (!(old_termios->c_cflag & CBAUD) &&
951 tty->termios->c_cflag & CBAUD) {
952 info->serial_signals |= SerialSignal_DTR;
953 if (!(tty->termios->c_cflag & CRTSCTS) ||
954 !test_bit(TTY_THROTTLED, &tty->flags)) {
955 info->serial_signals |= SerialSignal_RTS;
957 spin_lock_irqsave(&info->lock,flags);
959 spin_unlock_irqrestore(&info->lock,flags);
962 /* Handle turning off CRTSCTS */
963 if (old_termios->c_cflag & CRTSCTS &&
964 !(tty->termios->c_cflag & CRTSCTS)) {
970 /* Send a block of data
974 * tty pointer to tty information structure
975 * from_user flag: 1 = from user process
976 * buf pointer to buffer containing send data
977 * count size of send data in bytes
979 * Return Value: number of characters written
981 static int write(struct tty_struct *tty, int from_user,
982 const unsigned char *buf, int count)
985 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
988 if (debug_level >= DEBUG_LEVEL_INFO)
989 printk("%s(%d):%s write() count=%d\n",
990 __FILE__,__LINE__,info->device_name,count);
992 if (sanity_check(info, tty->name, "write"))
995 if (!tty || !info->tx_buf)
998 if (info->params.mode == MGSL_MODE_HDLC) {
999 if (count > info->max_frame_size) {
1003 if (info->tx_active)
1005 if (info->tx_count) {
1006 /* send accumulated data from send_char() calls */
1007 /* as frame and wait before accepting more data. */
1008 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1012 ret = info->tx_count = count;
1013 tx_load_dma_buffer(info, buf, count);
1019 c = min_t(int, count,
1020 min(info->max_frame_size - info->tx_count - 1,
1021 info->max_frame_size - info->tx_put));
1026 COPY_FROM_USER(err, info->tx_buf + info->tx_put, buf, c);
1033 memcpy(info->tx_buf + info->tx_put, buf, c);
1035 spin_lock_irqsave(&info->lock,flags);
1037 if (info->tx_put >= info->max_frame_size)
1038 info->tx_put -= info->max_frame_size;
1039 info->tx_count += c;
1040 spin_unlock_irqrestore(&info->lock,flags);
1047 if (info->params.mode == MGSL_MODE_HDLC) {
1049 ret = info->tx_count = 0;
1052 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1055 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1056 spin_lock_irqsave(&info->lock,flags);
1057 if (!info->tx_active)
1059 spin_unlock_irqrestore(&info->lock,flags);
1063 if (debug_level >= DEBUG_LEVEL_INFO)
1064 printk( "%s(%d):%s write() returning=%d\n",
1065 __FILE__,__LINE__,info->device_name,ret);
1069 /* Add a character to the transmit buffer.
1071 static void put_char(struct tty_struct *tty, unsigned char ch)
1073 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1074 unsigned long flags;
1076 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1077 printk( "%s(%d):%s put_char(%d)\n",
1078 __FILE__,__LINE__,info->device_name,ch);
1081 if (sanity_check(info, tty->name, "put_char"))
1084 if (!tty || !info->tx_buf)
1087 spin_lock_irqsave(&info->lock,flags);
1089 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1090 !info->tx_active ) {
1092 if (info->tx_count < info->max_frame_size - 1) {
1093 info->tx_buf[info->tx_put++] = ch;
1094 if (info->tx_put >= info->max_frame_size)
1095 info->tx_put -= info->max_frame_size;
1100 spin_unlock_irqrestore(&info->lock,flags);
1103 /* Send a high-priority XON/XOFF character
1105 static void send_xchar(struct tty_struct *tty, char ch)
1107 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1108 unsigned long flags;
1110 if (debug_level >= DEBUG_LEVEL_INFO)
1111 printk("%s(%d):%s send_xchar(%d)\n",
1112 __FILE__,__LINE__, info->device_name, ch );
1114 if (sanity_check(info, tty->name, "send_xchar"))
1119 /* Make sure transmit interrupts are on */
1120 spin_lock_irqsave(&info->lock,flags);
1121 if (!info->tx_enabled)
1123 spin_unlock_irqrestore(&info->lock,flags);
1127 /* Wait until the transmitter is empty.
1129 static void wait_until_sent(struct tty_struct *tty, int timeout)
1131 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1132 unsigned long orig_jiffies, char_time;
1137 if (debug_level >= DEBUG_LEVEL_INFO)
1138 printk("%s(%d):%s wait_until_sent() entry\n",
1139 __FILE__,__LINE__, info->device_name );
1141 if (sanity_check(info, tty->name, "wait_until_sent"))
1144 if (!(info->flags & ASYNC_INITIALIZED))
1147 orig_jiffies = jiffies;
1149 /* Set check interval to 1/5 of estimated time to
1150 * send a character, and make it at least 1. The check
1151 * interval should also be less than the timeout.
1152 * Note: use tight timings here to satisfy the NIST-PCTS.
1155 if ( info->params.data_rate ) {
1156 char_time = info->timeout/(32 * 5);
1163 char_time = min_t(unsigned long, char_time, timeout);
1165 if ( info->params.mode == MGSL_MODE_HDLC ) {
1166 while (info->tx_active) {
1167 set_current_state(TASK_INTERRUPTIBLE);
1168 schedule_timeout(char_time);
1169 if (signal_pending(current))
1171 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1175 //TODO: determine if there is something similar to USC16C32
1176 // TXSTATUS_ALL_SENT status
1177 while ( info->tx_active && info->tx_enabled) {
1178 set_current_state(TASK_INTERRUPTIBLE);
1179 schedule_timeout(char_time);
1180 if (signal_pending(current))
1182 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1188 if (debug_level >= DEBUG_LEVEL_INFO)
1189 printk("%s(%d):%s wait_until_sent() exit\n",
1190 __FILE__,__LINE__, info->device_name );
1193 /* Return the count of free bytes in transmit buffer
1195 static int write_room(struct tty_struct *tty)
1197 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1200 if (sanity_check(info, tty->name, "write_room"))
1203 if (info->params.mode == MGSL_MODE_HDLC) {
1204 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1206 ret = info->max_frame_size - info->tx_count - 1;
1211 if (debug_level >= DEBUG_LEVEL_INFO)
1212 printk("%s(%d):%s write_room()=%d\n",
1213 __FILE__, __LINE__, info->device_name, ret);
1218 /* enable transmitter and send remaining buffered characters
1220 static void flush_chars(struct tty_struct *tty)
1222 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1223 unsigned long flags;
1225 if ( debug_level >= DEBUG_LEVEL_INFO )
1226 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1227 __FILE__,__LINE__,info->device_name,info->tx_count);
1229 if (sanity_check(info, tty->name, "flush_chars"))
1232 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1236 if ( debug_level >= DEBUG_LEVEL_INFO )
1237 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1238 __FILE__,__LINE__,info->device_name );
1240 spin_lock_irqsave(&info->lock,flags);
1242 if (!info->tx_active) {
1243 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1245 /* operating in synchronous (frame oriented) mode */
1246 /* copy data from circular tx_buf to */
1247 /* transmit DMA buffer. */
1248 tx_load_dma_buffer(info,
1249 info->tx_buf,info->tx_count);
1254 spin_unlock_irqrestore(&info->lock,flags);
1257 /* Discard all data in the send buffer
1259 static void flush_buffer(struct tty_struct *tty)
1261 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1262 unsigned long flags;
1264 if (debug_level >= DEBUG_LEVEL_INFO)
1265 printk("%s(%d):%s flush_buffer() entry\n",
1266 __FILE__,__LINE__, info->device_name );
1268 if (sanity_check(info, tty->name, "flush_buffer"))
1271 spin_lock_irqsave(&info->lock,flags);
1272 info->tx_count = info->tx_put = info->tx_get = 0;
1273 del_timer(&info->tx_timer);
1274 spin_unlock_irqrestore(&info->lock,flags);
1276 wake_up_interruptible(&tty->write_wait);
1280 /* throttle (stop) transmitter
1282 static void tx_hold(struct tty_struct *tty)
1284 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1285 unsigned long flags;
1287 if (sanity_check(info, tty->name, "tx_hold"))
1290 if ( debug_level >= DEBUG_LEVEL_INFO )
1291 printk("%s(%d):%s tx_hold()\n",
1292 __FILE__,__LINE__,info->device_name);
1294 spin_lock_irqsave(&info->lock,flags);
1295 if (info->tx_enabled)
1297 spin_unlock_irqrestore(&info->lock,flags);
1300 /* release (start) transmitter
1302 static void tx_release(struct tty_struct *tty)
1304 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1305 unsigned long flags;
1307 if (sanity_check(info, tty->name, "tx_release"))
1310 if ( debug_level >= DEBUG_LEVEL_INFO )
1311 printk("%s(%d):%s tx_release()\n",
1312 __FILE__,__LINE__,info->device_name);
1314 spin_lock_irqsave(&info->lock,flags);
1315 if (!info->tx_enabled)
1317 spin_unlock_irqrestore(&info->lock,flags);
1320 /* Service an IOCTL request
1324 * tty pointer to tty instance data
1325 * file pointer to associated file object for device
1326 * cmd IOCTL command code
1327 * arg command argument/context
1329 * Return Value: 0 if success, otherwise error code
1331 static int ioctl(struct tty_struct *tty, struct file *file,
1332 unsigned int cmd, unsigned long arg)
1334 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1336 struct mgsl_icount cnow; /* kernel counter temps */
1337 struct serial_icounter_struct __user *p_cuser; /* user space */
1338 unsigned long flags;
1339 void __user *argp = (void __user *)arg;
1341 if (debug_level >= DEBUG_LEVEL_INFO)
1342 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1343 info->device_name, cmd );
1345 if (sanity_check(info, tty->name, "ioctl"))
1348 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1349 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1350 if (tty->flags & (1 << TTY_IO_ERROR))
1355 case MGSL_IOCGPARAMS:
1356 return get_params(info, argp);
1357 case MGSL_IOCSPARAMS:
1358 return set_params(info, argp);
1359 case MGSL_IOCGTXIDLE:
1360 return get_txidle(info, argp);
1361 case MGSL_IOCSTXIDLE:
1362 return set_txidle(info, (int)arg);
1363 case MGSL_IOCTXENABLE:
1364 return tx_enable(info, (int)arg);
1365 case MGSL_IOCRXENABLE:
1366 return rx_enable(info, (int)arg);
1367 case MGSL_IOCTXABORT:
1368 return tx_abort(info);
1369 case MGSL_IOCGSTATS:
1370 return get_stats(info, argp);
1371 case MGSL_IOCWAITEVENT:
1372 return wait_mgsl_event(info, argp);
1373 case MGSL_IOCLOOPTXDONE:
1374 return 0; // TODO: Not supported, need to document
1375 /* Wait for modem input (DCD,RI,DSR,CTS) change
1376 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1379 return modem_input_wait(info,(int)arg);
1382 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1383 * Return: write counters to the user passed counter struct
1384 * NB: both 1->0 and 0->1 transitions are counted except for
1385 * RI where only 0->1 is counted.
1388 spin_lock_irqsave(&info->lock,flags);
1389 cnow = info->icount;
1390 spin_unlock_irqrestore(&info->lock,flags);
1392 PUT_USER(error,cnow.cts, &p_cuser->cts);
1393 if (error) return error;
1394 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1395 if (error) return error;
1396 PUT_USER(error,cnow.rng, &p_cuser->rng);
1397 if (error) return error;
1398 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1399 if (error) return error;
1400 PUT_USER(error,cnow.rx, &p_cuser->rx);
1401 if (error) return error;
1402 PUT_USER(error,cnow.tx, &p_cuser->tx);
1403 if (error) return error;
1404 PUT_USER(error,cnow.frame, &p_cuser->frame);
1405 if (error) return error;
1406 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1407 if (error) return error;
1408 PUT_USER(error,cnow.parity, &p_cuser->parity);
1409 if (error) return error;
1410 PUT_USER(error,cnow.brk, &p_cuser->brk);
1411 if (error) return error;
1412 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1413 if (error) return error;
1416 return -ENOIOCTLCMD;
1422 * /proc fs routines....
1425 static inline int line_info(char *buf, SLMP_INFO *info)
1429 unsigned long flags;
1431 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1432 "\tIRQ=%d MaxFrameSize=%u\n",
1434 info->phys_sca_base,
1435 info->phys_memory_base,
1436 info->phys_statctrl_base,
1437 info->phys_lcr_base,
1439 info->max_frame_size );
1441 /* output current serial signal states */
1442 spin_lock_irqsave(&info->lock,flags);
1444 spin_unlock_irqrestore(&info->lock,flags);
1448 if (info->serial_signals & SerialSignal_RTS)
1449 strcat(stat_buf, "|RTS");
1450 if (info->serial_signals & SerialSignal_CTS)
1451 strcat(stat_buf, "|CTS");
1452 if (info->serial_signals & SerialSignal_DTR)
1453 strcat(stat_buf, "|DTR");
1454 if (info->serial_signals & SerialSignal_DSR)
1455 strcat(stat_buf, "|DSR");
1456 if (info->serial_signals & SerialSignal_DCD)
1457 strcat(stat_buf, "|CD");
1458 if (info->serial_signals & SerialSignal_RI)
1459 strcat(stat_buf, "|RI");
1461 if (info->params.mode == MGSL_MODE_HDLC) {
1462 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1463 info->icount.txok, info->icount.rxok);
1464 if (info->icount.txunder)
1465 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1466 if (info->icount.txabort)
1467 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1468 if (info->icount.rxshort)
1469 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1470 if (info->icount.rxlong)
1471 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1472 if (info->icount.rxover)
1473 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1474 if (info->icount.rxcrc)
1475 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1477 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1478 info->icount.tx, info->icount.rx);
1479 if (info->icount.frame)
1480 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1481 if (info->icount.parity)
1482 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1483 if (info->icount.brk)
1484 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1485 if (info->icount.overrun)
1486 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1489 /* Append serial signal status to end */
1490 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1492 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1493 info->tx_active,info->bh_requested,info->bh_running,
1499 /* Called to print information about devices
1501 int read_proc(char *page, char **start, off_t off, int count,
1502 int *eof, void *data)
1508 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1510 info = synclinkmp_device_list;
1512 l = line_info(page + len, info);
1514 if (len+begin > off+count)
1516 if (len+begin < off) {
1520 info = info->next_device;
1525 if (off >= len+begin)
1527 *start = page + (off-begin);
1528 return ((count < begin+len-off) ? count : begin+len-off);
1531 /* Return the count of bytes in transmit buffer
1533 static int chars_in_buffer(struct tty_struct *tty)
1535 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1537 if (sanity_check(info, tty->name, "chars_in_buffer"))
1540 if (debug_level >= DEBUG_LEVEL_INFO)
1541 printk("%s(%d):%s chars_in_buffer()=%d\n",
1542 __FILE__, __LINE__, info->device_name, info->tx_count);
1544 return info->tx_count;
1547 /* Signal remote device to throttle send data (our receive data)
1549 static void throttle(struct tty_struct * tty)
1551 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1552 unsigned long flags;
1554 if (debug_level >= DEBUG_LEVEL_INFO)
1555 printk("%s(%d):%s throttle() entry\n",
1556 __FILE__,__LINE__, info->device_name );
1558 if (sanity_check(info, tty->name, "throttle"))
1562 send_xchar(tty, STOP_CHAR(tty));
1564 if (tty->termios->c_cflag & CRTSCTS) {
1565 spin_lock_irqsave(&info->lock,flags);
1566 info->serial_signals &= ~SerialSignal_RTS;
1568 spin_unlock_irqrestore(&info->lock,flags);
1572 /* Signal remote device to stop throttling send data (our receive data)
1574 static void unthrottle(struct tty_struct * tty)
1576 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1577 unsigned long flags;
1579 if (debug_level >= DEBUG_LEVEL_INFO)
1580 printk("%s(%d):%s unthrottle() entry\n",
1581 __FILE__,__LINE__, info->device_name );
1583 if (sanity_check(info, tty->name, "unthrottle"))
1590 send_xchar(tty, START_CHAR(tty));
1593 if (tty->termios->c_cflag & CRTSCTS) {
1594 spin_lock_irqsave(&info->lock,flags);
1595 info->serial_signals |= SerialSignal_RTS;
1597 spin_unlock_irqrestore(&info->lock,flags);
1601 /* set or clear transmit break condition
1602 * break_state -1=set break condition, 0=clear
1604 static void set_break(struct tty_struct *tty, int break_state)
1606 unsigned char RegValue;
1607 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1608 unsigned long flags;
1610 if (debug_level >= DEBUG_LEVEL_INFO)
1611 printk("%s(%d):%s set_break(%d)\n",
1612 __FILE__,__LINE__, info->device_name, break_state);
1614 if (sanity_check(info, tty->name, "set_break"))
1617 spin_lock_irqsave(&info->lock,flags);
1618 RegValue = read_reg(info, CTL);
1619 if (break_state == -1)
1623 write_reg(info, CTL, RegValue);
1624 spin_unlock_irqrestore(&info->lock,flags);
1630 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1631 * set encoding and frame check sequence (FCS) options
1633 * dev pointer to network device structure
1634 * encoding serial encoding setting
1635 * parity FCS setting
1637 * returns 0 if success, otherwise error code
1639 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1640 unsigned short parity)
1642 SLMP_INFO *info = dev_to_port(dev);
1643 unsigned char new_encoding;
1644 unsigned short new_crctype;
1646 /* return error if TTY interface open */
1652 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1653 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1654 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1655 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1656 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1657 default: return -EINVAL;
1662 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1663 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1664 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1665 default: return -EINVAL;
1668 info->params.encoding = new_encoding;
1669 info->params.crc_type = new_crctype;;
1671 /* if network interface up, reprogram hardware */
1679 * called by generic HDLC layer to send frame
1681 * skb socket buffer containing HDLC frame
1682 * dev pointer to network device structure
1684 * returns 0 if success, otherwise error code
1686 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1688 SLMP_INFO *info = dev_to_port(dev);
1689 struct net_device_stats *stats = hdlc_stats(dev);
1690 unsigned long flags;
1692 if (debug_level >= DEBUG_LEVEL_INFO)
1693 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1695 /* stop sending until this frame completes */
1696 netif_stop_queue(dev);
1698 /* copy data to device buffers */
1699 info->tx_count = skb->len;
1700 tx_load_dma_buffer(info, skb->data, skb->len);
1702 /* update network statistics */
1703 stats->tx_packets++;
1704 stats->tx_bytes += skb->len;
1706 /* done with socket buffer, so free it */
1709 /* save start time for transmit timeout detection */
1710 dev->trans_start = jiffies;
1712 /* start hardware transmitter if necessary */
1713 spin_lock_irqsave(&info->lock,flags);
1714 if (!info->tx_active)
1716 spin_unlock_irqrestore(&info->lock,flags);
1722 * called by network layer when interface enabled
1723 * claim resources and initialize hardware
1725 * dev pointer to network device structure
1727 * returns 0 if success, otherwise error code
1729 static int hdlcdev_open(struct net_device *dev)
1731 SLMP_INFO *info = dev_to_port(dev);
1733 unsigned long flags;
1735 if (debug_level >= DEBUG_LEVEL_INFO)
1736 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1738 /* generic HDLC layer open processing */
1739 if ((rc = hdlc_open(dev)))
1742 /* arbitrate between network and tty opens */
1743 spin_lock_irqsave(&info->netlock, flags);
1744 if (info->count != 0 || info->netcount != 0) {
1745 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1746 spin_unlock_irqrestore(&info->netlock, flags);
1750 spin_unlock_irqrestore(&info->netlock, flags);
1752 /* claim resources and init adapter */
1753 if ((rc = startup(info)) != 0) {
1754 spin_lock_irqsave(&info->netlock, flags);
1756 spin_unlock_irqrestore(&info->netlock, flags);
1760 /* assert DTR and RTS, apply hardware settings */
1761 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1764 /* enable network layer transmit */
1765 dev->trans_start = jiffies;
1766 netif_start_queue(dev);
1768 /* inform generic HDLC layer of current DCD status */
1769 spin_lock_irqsave(&info->lock, flags);
1771 spin_unlock_irqrestore(&info->lock, flags);
1772 hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
1778 * called by network layer when interface is disabled
1779 * shutdown hardware and release resources
1781 * dev pointer to network device structure
1783 * returns 0 if success, otherwise error code
1785 static int hdlcdev_close(struct net_device *dev)
1787 SLMP_INFO *info = dev_to_port(dev);
1788 unsigned long flags;
1790 if (debug_level >= DEBUG_LEVEL_INFO)
1791 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1793 netif_stop_queue(dev);
1795 /* shutdown adapter and release resources */
1800 spin_lock_irqsave(&info->netlock, flags);
1802 spin_unlock_irqrestore(&info->netlock, flags);
1808 * called by network layer to process IOCTL call to network device
1810 * dev pointer to network device structure
1811 * ifr pointer to network interface request structure
1812 * cmd IOCTL command code
1814 * returns 0 if success, otherwise error code
1816 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1818 const size_t size = sizeof(sync_serial_settings);
1819 sync_serial_settings new_line;
1820 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1821 SLMP_INFO *info = dev_to_port(dev);
1824 if (debug_level >= DEBUG_LEVEL_INFO)
1825 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1827 /* return error if TTY interface open */
1831 if (cmd != SIOCWANDEV)
1832 return hdlc_ioctl(dev, ifr, cmd);
1834 switch(ifr->ifr_settings.type) {
1835 case IF_GET_IFACE: /* return current sync_serial_settings */
1837 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1838 if (ifr->ifr_settings.size < size) {
1839 ifr->ifr_settings.size = size; /* data size wanted */
1843 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1844 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1845 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1846 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1849 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1850 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1851 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1852 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1853 default: new_line.clock_type = CLOCK_DEFAULT;
1856 new_line.clock_rate = info->params.clock_speed;
1857 new_line.loopback = info->params.loopback ? 1:0;
1859 if (copy_to_user(line, &new_line, size))
1863 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1865 if(!capable(CAP_NET_ADMIN))
1867 if (copy_from_user(&new_line, line, size))
1870 switch (new_line.clock_type)
1872 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1873 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1874 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1875 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1876 case CLOCK_DEFAULT: flags = info->params.flags &
1877 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1878 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1879 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1880 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1881 default: return -EINVAL;
1884 if (new_line.loopback != 0 && new_line.loopback != 1)
1887 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1888 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1889 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1890 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1891 info->params.flags |= flags;
1893 info->params.loopback = new_line.loopback;
1895 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1896 info->params.clock_speed = new_line.clock_rate;
1898 info->params.clock_speed = 0;
1900 /* if network interface up, reprogram hardware */
1906 return hdlc_ioctl(dev, ifr, cmd);
1911 * called by network layer when transmit timeout is detected
1913 * dev pointer to network device structure
1915 static void hdlcdev_tx_timeout(struct net_device *dev)
1917 SLMP_INFO *info = dev_to_port(dev);
1918 struct net_device_stats *stats = hdlc_stats(dev);
1919 unsigned long flags;
1921 if (debug_level >= DEBUG_LEVEL_INFO)
1922 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1925 stats->tx_aborted_errors++;
1927 spin_lock_irqsave(&info->lock,flags);
1929 spin_unlock_irqrestore(&info->lock,flags);
1931 netif_wake_queue(dev);
1935 * called by device driver when transmit completes
1936 * reenable network layer transmit if stopped
1938 * info pointer to device instance information
1940 static void hdlcdev_tx_done(SLMP_INFO *info)
1942 if (netif_queue_stopped(info->netdev))
1943 netif_wake_queue(info->netdev);
1947 * called by device driver when frame received
1948 * pass frame to network layer
1950 * info pointer to device instance information
1951 * buf pointer to buffer contianing frame data
1952 * size count of data bytes in buf
1954 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1956 struct sk_buff *skb = dev_alloc_skb(size);
1957 struct net_device *dev = info->netdev;
1958 struct net_device_stats *stats = hdlc_stats(dev);
1960 if (debug_level >= DEBUG_LEVEL_INFO)
1961 printk("hdlcdev_rx(%s)\n",dev->name);
1964 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1965 stats->rx_dropped++;
1969 memcpy(skb_put(skb, size),buf,size);
1971 skb->dev = info->netdev;
1972 skb->mac.raw = skb->data;
1973 skb->protocol = hdlc_type_trans(skb, skb->dev);
1975 stats->rx_packets++;
1976 stats->rx_bytes += size;
1980 info->netdev->last_rx = jiffies;
1984 * called by device driver when adding device instance
1985 * do generic HDLC initialization
1987 * info pointer to device instance information
1989 * returns 0 if success, otherwise error code
1991 static int hdlcdev_init(SLMP_INFO *info)
1994 struct net_device *dev;
1997 /* allocate and initialize network and HDLC layer objects */
1999 if (!(dev = alloc_hdlcdev(info))) {
2000 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
2004 /* for network layer reporting purposes only */
2005 dev->mem_start = info->phys_sca_base;
2006 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
2007 dev->irq = info->irq_level;
2009 /* network layer callbacks and settings */
2010 dev->do_ioctl = hdlcdev_ioctl;
2011 dev->open = hdlcdev_open;
2012 dev->stop = hdlcdev_close;
2013 dev->tx_timeout = hdlcdev_tx_timeout;
2014 dev->watchdog_timeo = 10*HZ;
2015 dev->tx_queue_len = 50;
2017 /* generic HDLC layer callbacks and settings */
2018 hdlc = dev_to_hdlc(dev);
2019 hdlc->attach = hdlcdev_attach;
2020 hdlc->xmit = hdlcdev_xmit;
2022 /* register objects with HDLC layer */
2023 if ((rc = register_hdlc_device(dev))) {
2024 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2034 * called by device driver when removing device instance
2035 * do generic HDLC cleanup
2037 * info pointer to device instance information
2039 static void hdlcdev_exit(SLMP_INFO *info)
2041 unregister_hdlc_device(info->netdev);
2042 free_netdev(info->netdev);
2043 info->netdev = NULL;
2046 #endif /* CONFIG_HDLC */
2049 /* Return next bottom half action to perform.
2050 * Return Value: BH action code or 0 if nothing to do.
2052 int bh_action(SLMP_INFO *info)
2054 unsigned long flags;
2057 spin_lock_irqsave(&info->lock,flags);
2059 if (info->pending_bh & BH_RECEIVE) {
2060 info->pending_bh &= ~BH_RECEIVE;
2062 } else if (info->pending_bh & BH_TRANSMIT) {
2063 info->pending_bh &= ~BH_TRANSMIT;
2065 } else if (info->pending_bh & BH_STATUS) {
2066 info->pending_bh &= ~BH_STATUS;
2071 /* Mark BH routine as complete */
2072 info->bh_running = 0;
2073 info->bh_requested = 0;
2076 spin_unlock_irqrestore(&info->lock,flags);
2081 /* Perform bottom half processing of work items queued by ISR.
2083 void bh_handler(void* Context)
2085 SLMP_INFO *info = (SLMP_INFO*)Context;
2091 if ( debug_level >= DEBUG_LEVEL_BH )
2092 printk( "%s(%d):%s bh_handler() entry\n",
2093 __FILE__,__LINE__,info->device_name);
2095 info->bh_running = 1;
2097 while((action = bh_action(info)) != 0) {
2099 /* Process work item */
2100 if ( debug_level >= DEBUG_LEVEL_BH )
2101 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2102 __FILE__,__LINE__,info->device_name, action);
2116 /* unknown work item ID */
2117 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2118 __FILE__,__LINE__,info->device_name,action);
2123 if ( debug_level >= DEBUG_LEVEL_BH )
2124 printk( "%s(%d):%s bh_handler() exit\n",
2125 __FILE__,__LINE__,info->device_name);
2128 void bh_receive(SLMP_INFO *info)
2130 if ( debug_level >= DEBUG_LEVEL_BH )
2131 printk( "%s(%d):%s bh_receive()\n",
2132 __FILE__,__LINE__,info->device_name);
2134 while( rx_get_frame(info) );
2137 void bh_transmit(SLMP_INFO *info)
2139 struct tty_struct *tty = info->tty;
2141 if ( debug_level >= DEBUG_LEVEL_BH )
2142 printk( "%s(%d):%s bh_transmit() entry\n",
2143 __FILE__,__LINE__,info->device_name);
2147 wake_up_interruptible(&tty->write_wait);
2151 void bh_status(SLMP_INFO *info)
2153 if ( debug_level >= DEBUG_LEVEL_BH )
2154 printk( "%s(%d):%s bh_status() entry\n",
2155 __FILE__,__LINE__,info->device_name);
2157 info->ri_chkcount = 0;
2158 info->dsr_chkcount = 0;
2159 info->dcd_chkcount = 0;
2160 info->cts_chkcount = 0;
2163 void isr_timer(SLMP_INFO * info)
2165 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2167 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2168 write_reg(info, IER2, 0);
2170 /* TMCS, Timer Control/Status Register
2172 * 07 CMF, Compare match flag (read only) 1=match
2173 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2174 * 05 Reserved, must be 0
2175 * 04 TME, Timer Enable
2176 * 03..00 Reserved, must be 0
2180 write_reg(info, (unsigned char)(timer + TMCS), 0);
2182 info->irq_occurred = TRUE;
2184 if ( debug_level >= DEBUG_LEVEL_ISR )
2185 printk("%s(%d):%s isr_timer()\n",
2186 __FILE__,__LINE__,info->device_name);
2189 void isr_rxint(SLMP_INFO * info)
2191 struct tty_struct *tty = info->tty;
2192 struct mgsl_icount *icount = &info->icount;
2193 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2194 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2196 /* clear status bits */
2198 write_reg(info, SR1, status);
2201 write_reg(info, SR2, status2);
2203 if ( debug_level >= DEBUG_LEVEL_ISR )
2204 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2205 __FILE__,__LINE__,info->device_name,status,status2);
2207 if (info->params.mode == MGSL_MODE_ASYNC) {
2208 if (status & BRKD) {
2211 /* process break detection if tty control
2212 * is not set to ignore it
2215 if (!(status & info->ignore_status_mask1)) {
2216 if (info->read_status_mask1 & BRKD) {
2217 *tty->flip.flag_buf_ptr = TTY_BREAK;
2218 if (info->flags & ASYNC_SAK)
2226 if (status & (FLGD|IDLD)) {
2228 info->icount.exithunt++;
2229 else if (status & IDLD)
2230 info->icount.rxidle++;
2231 wake_up_interruptible(&info->event_wait_q);
2235 if (status & CDCD) {
2236 /* simulate a common modem status change interrupt
2239 get_signals( info );
2241 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2246 * handle async rx data interrupts
2248 void isr_rxrdy(SLMP_INFO * info)
2251 unsigned char DataByte;
2252 struct tty_struct *tty = info->tty;
2253 struct mgsl_icount *icount = &info->icount;
2255 if ( debug_level >= DEBUG_LEVEL_ISR )
2256 printk("%s(%d):%s isr_rxrdy\n",
2257 __FILE__,__LINE__,info->device_name);
2259 while((status = read_reg(info,CST0)) & BIT0)
2261 DataByte = read_reg(info,TRB);
2264 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2267 *tty->flip.char_buf_ptr = DataByte;
2268 *tty->flip.flag_buf_ptr = 0;
2273 if ( status & (PE + FRME + OVRN) ) {
2274 printk("%s(%d):%s rxerr=%04X\n",
2275 __FILE__,__LINE__,info->device_name,status);
2277 /* update error statistics */
2280 else if (status & FRME)
2282 else if (status & OVRN)
2285 /* discard char if tty control flags say so */
2286 if (status & info->ignore_status_mask2)
2289 status &= info->read_status_mask2;
2293 *tty->flip.flag_buf_ptr = TTY_PARITY;
2294 else if (status & FRME)
2295 *tty->flip.flag_buf_ptr = TTY_FRAME;
2296 if (status & OVRN) {
2297 /* Overrun is special, since it's
2298 * reported immediately, and doesn't
2299 * affect the current character
2301 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2303 tty->flip.flag_buf_ptr++;
2304 tty->flip.char_buf_ptr++;
2305 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2309 } /* end of if (error) */
2312 tty->flip.flag_buf_ptr++;
2313 tty->flip.char_buf_ptr++;
2318 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2319 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2320 __FILE__,__LINE__,info->device_name,
2321 tty ? tty->flip.count : 0);
2322 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2323 __FILE__,__LINE__,info->device_name,
2324 icount->rx,icount->brk,icount->parity,
2325 icount->frame,icount->overrun);
2328 if ( tty && tty->flip.count )
2329 tty_flip_buffer_push(tty);
2332 void isr_txeom(SLMP_INFO * info, unsigned char status)
2334 if ( debug_level >= DEBUG_LEVEL_ISR )
2335 printk("%s(%d):%s isr_txeom status=%02x\n",
2336 __FILE__,__LINE__,info->device_name,status);
2338 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2339 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2340 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2342 if (status & UDRN) {
2343 write_reg(info, CMD, TXRESET);
2344 write_reg(info, CMD, TXENABLE);
2346 write_reg(info, CMD, TXBUFCLR);
2348 /* disable and clear tx interrupts */
2349 info->ie0_value &= ~TXRDYE;
2350 info->ie1_value &= ~(IDLE + UDRN);
2351 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2352 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2354 if ( info->tx_active ) {
2355 if (info->params.mode != MGSL_MODE_ASYNC) {
2357 info->icount.txunder++;
2358 else if (status & IDLE)
2359 info->icount.txok++;
2362 info->tx_active = 0;
2363 info->tx_count = info->tx_put = info->tx_get = 0;
2365 del_timer(&info->tx_timer);
2367 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2368 info->serial_signals &= ~SerialSignal_RTS;
2369 info->drop_rts_on_tx_done = 0;
2375 hdlcdev_tx_done(info);
2379 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2383 info->pending_bh |= BH_TRANSMIT;
2390 * handle tx status interrupts
2392 void isr_txint(SLMP_INFO * info)
2394 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2396 /* clear status bits */
2397 write_reg(info, SR1, status);
2399 if ( debug_level >= DEBUG_LEVEL_ISR )
2400 printk("%s(%d):%s isr_txint status=%02x\n",
2401 __FILE__,__LINE__,info->device_name,status);
2403 if (status & (UDRN + IDLE))
2404 isr_txeom(info, status);
2406 if (status & CCTS) {
2407 /* simulate a common modem status change interrupt
2410 get_signals( info );
2412 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2418 * handle async tx data interrupts
2420 void isr_txrdy(SLMP_INFO * info)
2422 if ( debug_level >= DEBUG_LEVEL_ISR )
2423 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2424 __FILE__,__LINE__,info->device_name,info->tx_count);
2426 if (info->params.mode != MGSL_MODE_ASYNC) {
2427 /* disable TXRDY IRQ, enable IDLE IRQ */
2428 info->ie0_value &= ~TXRDYE;
2429 info->ie1_value |= IDLE;
2430 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2434 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2439 if ( info->tx_count )
2440 tx_load_fifo( info );
2442 info->tx_active = 0;
2443 info->ie0_value &= ~TXRDYE;
2444 write_reg(info, IE0, info->ie0_value);
2447 if (info->tx_count < WAKEUP_CHARS)
2448 info->pending_bh |= BH_TRANSMIT;
2451 void isr_rxdmaok(SLMP_INFO * info)
2453 /* BIT7 = EOT (end of transfer)
2454 * BIT6 = EOM (end of message/frame)
2456 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2458 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2459 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2461 if ( debug_level >= DEBUG_LEVEL_ISR )
2462 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2463 __FILE__,__LINE__,info->device_name,status);
2465 info->pending_bh |= BH_RECEIVE;
2468 void isr_rxdmaerror(SLMP_INFO * info)
2470 /* BIT5 = BOF (buffer overflow)
2471 * BIT4 = COF (counter overflow)
2473 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2475 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2476 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2478 if ( debug_level >= DEBUG_LEVEL_ISR )
2479 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2480 __FILE__,__LINE__,info->device_name,status);
2482 info->rx_overflow = TRUE;
2483 info->pending_bh |= BH_RECEIVE;
2486 void isr_txdmaok(SLMP_INFO * info)
2488 unsigned char status_reg1 = read_reg(info, SR1);
2490 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2491 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2492 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2494 if ( debug_level >= DEBUG_LEVEL_ISR )
2495 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2496 __FILE__,__LINE__,info->device_name,status_reg1);
2498 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2499 write_reg16(info, TRC0, 0);
2500 info->ie0_value |= TXRDYE;
2501 write_reg(info, IE0, info->ie0_value);
2504 void isr_txdmaerror(SLMP_INFO * info)
2506 /* BIT5 = BOF (buffer overflow)
2507 * BIT4 = COF (counter overflow)
2509 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2511 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2512 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2514 if ( debug_level >= DEBUG_LEVEL_ISR )
2515 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2516 __FILE__,__LINE__,info->device_name,status);
2519 /* handle input serial signal changes
2521 void isr_io_pin( SLMP_INFO *info, u16 status )
2523 struct mgsl_icount *icount;
2525 if ( debug_level >= DEBUG_LEVEL_ISR )
2526 printk("%s(%d):isr_io_pin status=%04X\n",
2527 __FILE__,__LINE__,status);
2529 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2530 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2531 icount = &info->icount;
2532 /* update input line counters */
2533 if (status & MISCSTATUS_RI_LATCHED) {
2535 if ( status & SerialSignal_RI )
2536 info->input_signal_events.ri_up++;
2538 info->input_signal_events.ri_down++;
2540 if (status & MISCSTATUS_DSR_LATCHED) {
2542 if ( status & SerialSignal_DSR )
2543 info->input_signal_events.dsr_up++;
2545 info->input_signal_events.dsr_down++;
2547 if (status & MISCSTATUS_DCD_LATCHED) {
2548 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2549 info->ie1_value &= ~CDCD;
2550 write_reg(info, IE1, info->ie1_value);
2553 if (status & SerialSignal_DCD) {
2554 info->input_signal_events.dcd_up++;
2556 info->input_signal_events.dcd_down++;
2559 hdlc_set_carrier(status & SerialSignal_DCD, info->netdev);
2562 if (status & MISCSTATUS_CTS_LATCHED)
2564 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2565 info->ie1_value &= ~CCTS;
2566 write_reg(info, IE1, info->ie1_value);
2569 if ( status & SerialSignal_CTS )
2570 info->input_signal_events.cts_up++;
2572 info->input_signal_events.cts_down++;
2574 wake_up_interruptible(&info->status_event_wait_q);
2575 wake_up_interruptible(&info->event_wait_q);
2577 if ( (info->flags & ASYNC_CHECK_CD) &&
2578 (status & MISCSTATUS_DCD_LATCHED) ) {
2579 if ( debug_level >= DEBUG_LEVEL_ISR )
2580 printk("%s CD now %s...", info->device_name,
2581 (status & SerialSignal_DCD) ? "on" : "off");
2582 if (status & SerialSignal_DCD)
2583 wake_up_interruptible(&info->open_wait);
2585 if ( debug_level >= DEBUG_LEVEL_ISR )
2586 printk("doing serial hangup...");
2588 tty_hangup(info->tty);
2592 if ( (info->flags & ASYNC_CTS_FLOW) &&
2593 (status & MISCSTATUS_CTS_LATCHED) ) {
2595 if (info->tty->hw_stopped) {
2596 if (status & SerialSignal_CTS) {
2597 if ( debug_level >= DEBUG_LEVEL_ISR )
2598 printk("CTS tx start...");
2599 info->tty->hw_stopped = 0;
2601 info->pending_bh |= BH_TRANSMIT;
2605 if (!(status & SerialSignal_CTS)) {
2606 if ( debug_level >= DEBUG_LEVEL_ISR )
2607 printk("CTS tx stop...");
2608 info->tty->hw_stopped = 1;
2616 info->pending_bh |= BH_STATUS;
2619 /* Interrupt service routine entry point.
2622 * irq interrupt number that caused interrupt
2623 * dev_id device ID supplied during interrupt registration
2624 * regs interrupted processor context
2626 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2627 struct pt_regs *regs)
2630 unsigned char status, status0, status1=0;
2631 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2632 unsigned char timerstatus0, timerstatus1=0;
2633 unsigned char shift;
2637 if ( debug_level >= DEBUG_LEVEL_ISR )
2638 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2639 __FILE__,__LINE__,irq);
2641 info = (SLMP_INFO *)dev_id;
2645 spin_lock(&info->lock);
2649 /* get status for SCA0 (ports 0-1) */
2650 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2651 status0 = (unsigned char)tmp;
2652 dmastatus0 = (unsigned char)(tmp>>8);
2653 timerstatus0 = read_reg(info, ISR2);
2655 if ( debug_level >= DEBUG_LEVEL_ISR )
2656 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2657 __FILE__,__LINE__,info->device_name,
2658 status0,dmastatus0,timerstatus0);
2660 if (info->port_count == 4) {
2661 /* get status for SCA1 (ports 2-3) */
2662 tmp = read_reg16(info->port_array[2], ISR0);
2663 status1 = (unsigned char)tmp;
2664 dmastatus1 = (unsigned char)(tmp>>8);
2665 timerstatus1 = read_reg(info->port_array[2], ISR2);
2667 if ( debug_level >= DEBUG_LEVEL_ISR )
2668 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2669 __FILE__,__LINE__,info->device_name,
2670 status1,dmastatus1,timerstatus1);
2673 if (!status0 && !dmastatus0 && !timerstatus0 &&
2674 !status1 && !dmastatus1 && !timerstatus1)
2677 for(i=0; i < info->port_count ; i++) {
2678 if (info->port_array[i] == NULL)
2682 dmastatus = dmastatus0;
2685 dmastatus = dmastatus1;
2688 shift = i & 1 ? 4 :0;
2690 if (status & BIT0 << shift)
2691 isr_rxrdy(info->port_array[i]);
2692 if (status & BIT1 << shift)
2693 isr_txrdy(info->port_array[i]);
2694 if (status & BIT2 << shift)
2695 isr_rxint(info->port_array[i]);
2696 if (status & BIT3 << shift)
2697 isr_txint(info->port_array[i]);
2699 if (dmastatus & BIT0 << shift)
2700 isr_rxdmaerror(info->port_array[i]);
2701 if (dmastatus & BIT1 << shift)
2702 isr_rxdmaok(info->port_array[i]);
2703 if (dmastatus & BIT2 << shift)
2704 isr_txdmaerror(info->port_array[i]);
2705 if (dmastatus & BIT3 << shift)
2706 isr_txdmaok(info->port_array[i]);
2709 if (timerstatus0 & (BIT5 | BIT4))
2710 isr_timer(info->port_array[0]);
2711 if (timerstatus0 & (BIT7 | BIT6))
2712 isr_timer(info->port_array[1]);
2713 if (timerstatus1 & (BIT5 | BIT4))
2714 isr_timer(info->port_array[2]);
2715 if (timerstatus1 & (BIT7 | BIT6))
2716 isr_timer(info->port_array[3]);
2719 for(i=0; i < info->port_count ; i++) {
2720 SLMP_INFO * port = info->port_array[i];
2722 /* Request bottom half processing if there's something
2723 * for it to do and the bh is not already running.
2725 * Note: startup adapter diags require interrupts.
2726 * do not request bottom half processing if the
2727 * device is not open in a normal mode.
2729 if ( port && (port->count || port->netcount) &&
2730 port->pending_bh && !port->bh_running &&
2731 !port->bh_requested ) {
2732 if ( debug_level >= DEBUG_LEVEL_ISR )
2733 printk("%s(%d):%s queueing bh task.\n",
2734 __FILE__,__LINE__,port->device_name);
2735 schedule_work(&port->task);
2736 port->bh_requested = 1;
2740 spin_unlock(&info->lock);
2742 if ( debug_level >= DEBUG_LEVEL_ISR )
2743 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2744 __FILE__,__LINE__,irq);
2748 /* Initialize and start device.
2750 static int startup(SLMP_INFO * info)
2752 if ( debug_level >= DEBUG_LEVEL_INFO )
2753 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2755 if (info->flags & ASYNC_INITIALIZED)
2758 if (!info->tx_buf) {
2759 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2760 if (!info->tx_buf) {
2761 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2762 __FILE__,__LINE__,info->device_name);
2767 info->pending_bh = 0;
2769 /* program hardware for current parameters */
2772 change_params(info);
2774 info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2775 add_timer(&info->status_timer);
2778 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2780 info->flags |= ASYNC_INITIALIZED;
2785 /* Called by close() and hangup() to shutdown hardware
2787 static void shutdown(SLMP_INFO * info)
2789 unsigned long flags;
2791 if (!(info->flags & ASYNC_INITIALIZED))
2794 if (debug_level >= DEBUG_LEVEL_INFO)
2795 printk("%s(%d):%s synclinkmp_shutdown()\n",
2796 __FILE__,__LINE__, info->device_name );
2798 /* clear status wait queue because status changes */
2799 /* can't happen after shutting down the hardware */
2800 wake_up_interruptible(&info->status_event_wait_q);
2801 wake_up_interruptible(&info->event_wait_q);
2803 del_timer(&info->tx_timer);
2804 del_timer(&info->status_timer);
2807 kfree(info->tx_buf);
2808 info->tx_buf = NULL;
2811 spin_lock_irqsave(&info->lock,flags);
2815 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2816 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2820 spin_unlock_irqrestore(&info->lock,flags);
2823 set_bit(TTY_IO_ERROR, &info->tty->flags);
2825 info->flags &= ~ASYNC_INITIALIZED;
2828 static void program_hw(SLMP_INFO *info)
2830 unsigned long flags;
2832 spin_lock_irqsave(&info->lock,flags);
2837 info->tx_count = info->tx_put = info->tx_get = 0;
2839 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2846 info->dcd_chkcount = 0;
2847 info->cts_chkcount = 0;
2848 info->ri_chkcount = 0;
2849 info->dsr_chkcount = 0;
2851 info->ie1_value |= (CDCD|CCTS);
2852 write_reg(info, IE1, info->ie1_value);
2856 if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2859 spin_unlock_irqrestore(&info->lock,flags);
2862 /* Reconfigure adapter based on new parameters
2864 static void change_params(SLMP_INFO *info)
2869 if (!info->tty || !info->tty->termios)
2872 if (debug_level >= DEBUG_LEVEL_INFO)
2873 printk("%s(%d):%s change_params()\n",
2874 __FILE__,__LINE__, info->device_name );
2876 cflag = info->tty->termios->c_cflag;
2878 /* if B0 rate (hangup) specified then negate DTR and RTS */
2879 /* otherwise assert DTR and RTS */
2881 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2883 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2885 /* byte size and parity */
2887 switch (cflag & CSIZE) {
2888 case CS5: info->params.data_bits = 5; break;
2889 case CS6: info->params.data_bits = 6; break;
2890 case CS7: info->params.data_bits = 7; break;
2891 case CS8: info->params.data_bits = 8; break;
2892 /* Never happens, but GCC is too dumb to figure it out */
2893 default: info->params.data_bits = 7; break;
2897 info->params.stop_bits = 2;
2899 info->params.stop_bits = 1;
2901 info->params.parity = ASYNC_PARITY_NONE;
2902 if (cflag & PARENB) {
2904 info->params.parity = ASYNC_PARITY_ODD;
2906 info->params.parity = ASYNC_PARITY_EVEN;
2909 info->params.parity = ASYNC_PARITY_SPACE;
2913 /* calculate number of jiffies to transmit a full
2914 * FIFO (32 bytes) at specified data rate
2916 bits_per_char = info->params.data_bits +
2917 info->params.stop_bits + 1;
2919 /* if port data rate is set to 460800 or less then
2920 * allow tty settings to override, otherwise keep the
2921 * current data rate.
2923 if (info->params.data_rate <= 460800) {
2924 info->params.data_rate = tty_get_baud_rate(info->tty);
2927 if ( info->params.data_rate ) {
2928 info->timeout = (32*HZ*bits_per_char) /
2929 info->params.data_rate;
2931 info->timeout += HZ/50; /* Add .02 seconds of slop */
2933 if (cflag & CRTSCTS)
2934 info->flags |= ASYNC_CTS_FLOW;
2936 info->flags &= ~ASYNC_CTS_FLOW;
2939 info->flags &= ~ASYNC_CHECK_CD;
2941 info->flags |= ASYNC_CHECK_CD;
2943 /* process tty input control flags */
2945 info->read_status_mask2 = OVRN;
2946 if (I_INPCK(info->tty))
2947 info->read_status_mask2 |= PE | FRME;
2948 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2949 info->read_status_mask1 |= BRKD;
2950 if (I_IGNPAR(info->tty))
2951 info->ignore_status_mask2 |= PE | FRME;
2952 if (I_IGNBRK(info->tty)) {
2953 info->ignore_status_mask1 |= BRKD;
2954 /* If ignoring parity and break indicators, ignore
2955 * overruns too. (For real raw support).
2957 if (I_IGNPAR(info->tty))
2958 info->ignore_status_mask2 |= OVRN;
2964 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2968 if (debug_level >= DEBUG_LEVEL_INFO)
2969 printk("%s(%d):%s get_params()\n",
2970 __FILE__,__LINE__, info->device_name);
2972 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2974 if ( debug_level >= DEBUG_LEVEL_INFO )
2975 printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2976 __FILE__,__LINE__,info->device_name);
2983 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2986 if (debug_level >= DEBUG_LEVEL_INFO)
2987 printk("%s(%d):%s get_params()\n",
2988 __FILE__,__LINE__, info->device_name);
2990 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2992 if ( debug_level >= DEBUG_LEVEL_INFO )
2993 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2994 __FILE__,__LINE__,info->device_name);
3001 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
3003 unsigned long flags;
3004 MGSL_PARAMS tmp_params;
3007 if (debug_level >= DEBUG_LEVEL_INFO)
3008 printk("%s(%d):%s set_params\n",
3009 __FILE__,__LINE__,info->device_name );
3010 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
3012 if ( debug_level >= DEBUG_LEVEL_INFO )
3013 printk( "%s(%d):%s set_params() user buffer copy failed\n",
3014 __FILE__,__LINE__,info->device_name);
3018 spin_lock_irqsave(&info->lock,flags);
3019 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3020 spin_unlock_irqrestore(&info->lock,flags);
3022 change_params(info);
3027 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3031 if (debug_level >= DEBUG_LEVEL_INFO)
3032 printk("%s(%d):%s get_txidle()=%d\n",
3033 __FILE__,__LINE__, info->device_name, info->idle_mode);
3035 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3037 if ( debug_level >= DEBUG_LEVEL_INFO )
3038 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3039 __FILE__,__LINE__,info->device_name);
3046 static int set_txidle(SLMP_INFO * info, int idle_mode)
3048 unsigned long flags;
3050 if (debug_level >= DEBUG_LEVEL_INFO)
3051 printk("%s(%d):%s set_txidle(%d)\n",
3052 __FILE__,__LINE__,info->device_name, idle_mode );
3054 spin_lock_irqsave(&info->lock,flags);
3055 info->idle_mode = idle_mode;
3056 tx_set_idle( info );
3057 spin_unlock_irqrestore(&info->lock,flags);
3061 static int tx_enable(SLMP_INFO * info, int enable)
3063 unsigned long flags;
3065 if (debug_level >= DEBUG_LEVEL_INFO)
3066 printk("%s(%d):%s tx_enable(%d)\n",
3067 __FILE__,__LINE__,info->device_name, enable);
3069 spin_lock_irqsave(&info->lock,flags);
3071 if ( !info->tx_enabled ) {
3075 if ( info->tx_enabled )
3078 spin_unlock_irqrestore(&info->lock,flags);
3082 /* abort send HDLC frame
3084 static int tx_abort(SLMP_INFO * info)
3086 unsigned long flags;
3088 if (debug_level >= DEBUG_LEVEL_INFO)
3089 printk("%s(%d):%s tx_abort()\n",
3090 __FILE__,__LINE__,info->device_name);
3092 spin_lock_irqsave(&info->lock,flags);
3093 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3094 info->ie1_value &= ~UDRN;
3095 info->ie1_value |= IDLE;
3096 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3097 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3099 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3100 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3102 write_reg(info, CMD, TXABORT);
3104 spin_unlock_irqrestore(&info->lock,flags);
3108 static int rx_enable(SLMP_INFO * info, int enable)
3110 unsigned long flags;
3112 if (debug_level >= DEBUG_LEVEL_INFO)
3113 printk("%s(%d):%s rx_enable(%d)\n",
3114 __FILE__,__LINE__,info->device_name,enable);
3116 spin_lock_irqsave(&info->lock,flags);
3118 if ( !info->rx_enabled )
3121 if ( info->rx_enabled )
3124 spin_unlock_irqrestore(&info->lock,flags);
3128 static int map_status(int signals)
3130 /* Map status bits to API event bits */
3132 return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
3133 ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
3134 ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
3135 ((signals & SerialSignal_RI) ? MgslEvent_RiActive : MgslEvent_RiInactive);
3138 /* wait for specified event to occur
3140 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3142 unsigned long flags;
3145 struct mgsl_icount cprev, cnow;
3148 struct _input_signal_events oldsigs, newsigs;
3149 DECLARE_WAITQUEUE(wait, current);
3151 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3156 if (debug_level >= DEBUG_LEVEL_INFO)
3157 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3158 __FILE__,__LINE__,info->device_name,mask);
3160 spin_lock_irqsave(&info->lock,flags);
3162 /* return immediately if state matches requested events */
3164 s = map_status(info->serial_signals);
3167 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3168 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3169 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3170 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3172 spin_unlock_irqrestore(&info->lock,flags);
3176 /* save current irq counts */
3177 cprev = info->icount;
3178 oldsigs = info->input_signal_events;
3180 /* enable hunt and idle irqs if needed */
3181 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3182 unsigned char oldval = info->ie1_value;
3183 unsigned char newval = oldval +
3184 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3185 (mask & MgslEvent_IdleReceived ? IDLD:0);
3186 if ( oldval != newval ) {
3187 info->ie1_value = newval;
3188 write_reg(info, IE1, info->ie1_value);
3192 set_current_state(TASK_INTERRUPTIBLE);
3193 add_wait_queue(&info->event_wait_q, &wait);
3195 spin_unlock_irqrestore(&info->lock,flags);
3199 if (signal_pending(current)) {
3204 /* get current irq counts */
3205 spin_lock_irqsave(&info->lock,flags);
3206 cnow = info->icount;
3207 newsigs = info->input_signal_events;
3208 set_current_state(TASK_INTERRUPTIBLE);
3209 spin_unlock_irqrestore(&info->lock,flags);
3211 /* if no change, wait aborted for some reason */
3212 if (newsigs.dsr_up == oldsigs.dsr_up &&
3213 newsigs.dsr_down == oldsigs.dsr_down &&
3214 newsigs.dcd_up == oldsigs.dcd_up &&
3215 newsigs.dcd_down == oldsigs.dcd_down &&
3216 newsigs.cts_up == oldsigs.cts_up &&
3217 newsigs.cts_down == oldsigs.cts_down &&
3218 newsigs.ri_up == oldsigs.ri_up &&
3219 newsigs.ri_down == oldsigs.ri_down &&
3220 cnow.exithunt == cprev.exithunt &&
3221 cnow.rxidle == cprev.rxidle) {
3227 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3228 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3229 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3230 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3231 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3232 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3233 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3234 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3235 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3236 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3244 remove_wait_queue(&info->event_wait_q, &wait);
3245 set_current_state(TASK_RUNNING);
3248 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3249 spin_lock_irqsave(&info->lock,flags);
3250 if (!waitqueue_active(&info->event_wait_q)) {
3251 /* disable enable exit hunt mode/idle rcvd IRQs */
3252 info->ie1_value &= ~(FLGD|IDLD);
3253 write_reg(info, IE1, info->ie1_value);
3255 spin_unlock_irqrestore(&info->lock,flags);
3259 PUT_USER(rc, events, mask_ptr);
3264 static int modem_input_wait(SLMP_INFO *info,int arg)
3266 unsigned long flags;
3268 struct mgsl_icount cprev, cnow;
3269 DECLARE_WAITQUEUE(wait, current);
3271 /* save current irq counts */
3272 spin_lock_irqsave(&info->lock,flags);
3273 cprev = info->icount;
3274 add_wait_queue(&info->status_event_wait_q, &wait);
3275 set_current_state(TASK_INTERRUPTIBLE);
3276 spin_unlock_irqrestore(&info->lock,flags);
3280 if (signal_pending(current)) {
3285 /* get new irq counts */
3286 spin_lock_irqsave(&info->lock,flags);
3287 cnow = info->icount;
3288 set_current_state(TASK_INTERRUPTIBLE);
3289 spin_unlock_irqrestore(&info->lock,flags);
3291 /* if no change, wait aborted for some reason */
3292 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3293 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3298 /* check for change in caller specified modem input */
3299 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3300 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3301 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3302 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3309 remove_wait_queue(&info->status_event_wait_q, &wait);
3310 set_current_state(TASK_RUNNING);
3314 /* return the state of the serial control and status signals
3316 static int tiocmget(struct tty_struct *tty, struct file *file)
3318 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3319 unsigned int result;
3320 unsigned long flags;
3322 spin_lock_irqsave(&info->lock,flags);
3324 spin_unlock_irqrestore(&info->lock,flags);
3326 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3327 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3328 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3329 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3330 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3331 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3333 if (debug_level >= DEBUG_LEVEL_INFO)
3334 printk("%s(%d):%s tiocmget() value=%08X\n",
3335 __FILE__,__LINE__, info->device_name, result );
3339 /* set modem control signals (DTR/RTS)
3341 static int tiocmset(struct tty_struct *tty, struct file *file,
3342 unsigned int set, unsigned int clear)
3344 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3345 unsigned long flags;
3347 if (debug_level >= DEBUG_LEVEL_INFO)
3348 printk("%s(%d):%s tiocmset(%x,%x)\n",
3349 __FILE__,__LINE__,info->device_name, set, clear);
3351 if (set & TIOCM_RTS)
3352 info->serial_signals |= SerialSignal_RTS;
3353 if (set & TIOCM_DTR)
3354 info->serial_signals |= SerialSignal_DTR;
3355 if (clear & TIOCM_RTS)
3356 info->serial_signals &= ~SerialSignal_RTS;
3357 if (clear & TIOCM_DTR)
3358 info->serial_signals &= ~SerialSignal_DTR;
3360 spin_lock_irqsave(&info->lock,flags);
3362 spin_unlock_irqrestore(&info->lock,flags);
3369 /* Block the current process until the specified port is ready to open.
3371 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3374 DECLARE_WAITQUEUE(wait, current);
3376 int do_clocal = 0, extra_count = 0;
3377 unsigned long flags;
3379 if (debug_level >= DEBUG_LEVEL_INFO)
3380 printk("%s(%d):%s block_til_ready()\n",
3381 __FILE__,__LINE__, tty->driver->name );
3383 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3384 /* nonblock mode is set or port is not enabled */
3385 /* just verify that callout device is not active */
3386 info->flags |= ASYNC_NORMAL_ACTIVE;
3390 if (tty->termios->c_cflag & CLOCAL)
3393 /* Wait for carrier detect and the line to become
3394 * free (i.e., not in use by the callout). While we are in
3395 * this loop, info->count is dropped by one, so that
3396 * close() knows when to free things. We restore it upon
3397 * exit, either normal or abnormal.
3401 add_wait_queue(&info->open_wait, &wait);
3403 if (debug_level >= DEBUG_LEVEL_INFO)
3404 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3405 __FILE__,__LINE__, tty->driver->name, info->count );
3407 spin_lock_irqsave(&info->lock, flags);
3408 if (!tty_hung_up_p(filp)) {
3412 spin_unlock_irqrestore(&info->lock, flags);
3413 info->blocked_open++;
3416 if ((tty->termios->c_cflag & CBAUD)) {
3417 spin_lock_irqsave(&info->lock,flags);
3418 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3420 spin_unlock_irqrestore(&info->lock,flags);
3423 set_current_state(TASK_INTERRUPTIBLE);
3425 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3426 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3427 -EAGAIN : -ERESTARTSYS;
3431 spin_lock_irqsave(&info->lock,flags);
3433 spin_unlock_irqrestore(&info->lock,flags);
3435 if (!(info->flags & ASYNC_CLOSING) &&
3436 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3440 if (signal_pending(current)) {
3441 retval = -ERESTARTSYS;
3445 if (debug_level >= DEBUG_LEVEL_INFO)
3446 printk("%s(%d):%s block_til_ready() count=%d\n",
3447 __FILE__,__LINE__, tty->driver->name, info->count );
3452 set_current_state(TASK_RUNNING);
3453 remove_wait_queue(&info->open_wait, &wait);
3457 info->blocked_open--;
3459 if (debug_level >= DEBUG_LEVEL_INFO)
3460 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3461 __FILE__,__LINE__, tty->driver->name, info->count );
3464 info->flags |= ASYNC_NORMAL_ACTIVE;
3469 int alloc_dma_bufs(SLMP_INFO *info)
3471 unsigned short BuffersPerFrame;
3472 unsigned short BufferCount;
3474 // Force allocation to start at 64K boundary for each port.
3475 // This is necessary because *all* buffer descriptors for a port
3476 // *must* be in the same 64K block. All descriptors on a port
3477 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3478 // into the CBP register.
3479 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3481 /* Calculate the number of DMA buffers necessary to hold the */
3482 /* largest allowable frame size. Note: If the max frame size is */
3483 /* not an even multiple of the DMA buffer size then we need to */
3484 /* round the buffer count per frame up one. */
3486 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3487 if ( info->max_frame_size % SCABUFSIZE )
3490 /* calculate total number of data buffers (SCABUFSIZE) possible
3491 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3492 * for the descriptor list (BUFFERLISTSIZE).
3494 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3496 /* limit number of buffers to maximum amount of descriptors */
3497 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3498 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3500 /* use enough buffers to transmit one max size frame */
3501 info->tx_buf_count = BuffersPerFrame + 1;
3503 /* never use more than half the available buffers for transmit */
3504 if (info->tx_buf_count > (BufferCount/2))
3505 info->tx_buf_count = BufferCount/2;
3507 if (info->tx_buf_count > SCAMAXDESC)
3508 info->tx_buf_count = SCAMAXDESC;
3510 /* use remaining buffers for receive */
3511 info->rx_buf_count = BufferCount - info->tx_buf_count;
3513 if (info->rx_buf_count > SCAMAXDESC)
3514 info->rx_buf_count = SCAMAXDESC;
3516 if ( debug_level >= DEBUG_LEVEL_INFO )
3517 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3518 __FILE__,__LINE__, info->device_name,
3519 info->tx_buf_count,info->rx_buf_count);
3521 if ( alloc_buf_list( info ) < 0 ||
3522 alloc_frame_bufs(info,
3524 info->rx_buf_list_ex,
3525 info->rx_buf_count) < 0 ||
3526 alloc_frame_bufs(info,
3528 info->tx_buf_list_ex,
3529 info->tx_buf_count) < 0 ||
3530 alloc_tmp_rx_buf(info) < 0 ) {
3531 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3532 __FILE__,__LINE__, info->device_name);
3536 rx_reset_buffers( info );
3541 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3543 int alloc_buf_list(SLMP_INFO *info)
3547 /* build list in adapter shared memory */
3548 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3549 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3550 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3552 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3554 /* Save virtual address pointers to the receive and */
3555 /* transmit buffer lists. (Receive 1st). These pointers will */
3556 /* be used by the processor to access the lists. */
3557 info->rx_buf_list = (SCADESC *)info->buffer_list;
3559 info->tx_buf_list = (SCADESC *)info->buffer_list;
3560 info->tx_buf_list += info->rx_buf_count;
3562 /* Build links for circular buffer entry lists (tx and rx)
3564 * Note: links are physical addresses read by the SCA device
3565 * to determine the next buffer entry to use.
3568 for ( i = 0; i < info->rx_buf_count; i++ ) {
3569 /* calculate and store physical address of this buffer entry */
3570 info->rx_buf_list_ex[i].phys_entry =
3571 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3573 /* calculate and store physical address of */
3574 /* next entry in cirular list of entries */
3575 info->rx_buf_list[i].next = info->buffer_list_phys;
3576 if ( i < info->rx_buf_count - 1 )
3577 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3579 info->rx_buf_list[i].length = SCABUFSIZE;
3582 for ( i = 0; i < info->tx_buf_count; i++ ) {
3583 /* calculate and store physical address of this buffer entry */
3584 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3585 ((info->rx_buf_count + i) * sizeof(SCADESC));
3587 /* calculate and store physical address of */
3588 /* next entry in cirular list of entries */
3590 info->tx_buf_list[i].next = info->buffer_list_phys +
3591 info->rx_buf_count * sizeof(SCADESC);
3593 if ( i < info->tx_buf_count - 1 )
3594 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3600 /* Allocate the frame DMA buffers used by the specified buffer list.
3602 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3605 unsigned long phys_addr;
3607 for ( i = 0; i < count; i++ ) {
3608 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3609 phys_addr = info->port_array[0]->last_mem_alloc;
3610 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3612 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3613 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3619 void free_dma_bufs(SLMP_INFO *info)
3621 info->buffer_list = NULL;
3622 info->rx_buf_list = NULL;
3623 info->tx_buf_list = NULL;
3626 /* allocate buffer large enough to hold max_frame_size.
3627 * This buffer is used to pass an assembled frame to the line discipline.
3629 int alloc_tmp_rx_buf(SLMP_INFO *info)
3631 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3632 if (info->tmp_rx_buf == NULL)
3637 void free_tmp_rx_buf(SLMP_INFO *info)
3639 if (info->tmp_rx_buf)
3640 kfree(info->tmp_rx_buf);
3641 info->tmp_rx_buf = NULL;
3644 int claim_resources(SLMP_INFO *info)
3646 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3647 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3648 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3649 info->init_error = DiagStatus_AddressConflict;
3653 info->shared_mem_requested = 1;
3655 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3656 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3657 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3658 info->init_error = DiagStatus_AddressConflict;
3662 info->lcr_mem_requested = 1;
3664 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3665 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3666 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3667 info->init_error = DiagStatus_AddressConflict;
3671 info->sca_base_requested = 1;
3673 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3674 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3675 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3676 info->init_error = DiagStatus_AddressConflict;
3680 info->sca_statctrl_requested = 1;
3682 info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3683 if (!info->memory_base) {
3684 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3685 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3686 info->init_error = DiagStatus_CantAssignPciResources;
3690 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3691 if (!info->lcr_base) {
3692 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3693 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3694 info->init_error = DiagStatus_CantAssignPciResources;
3697 info->lcr_base += info->lcr_offset;
3699 info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3700 if (!info->sca_base) {
3701 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3702 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3703 info->init_error = DiagStatus_CantAssignPciResources;
3706 info->sca_base += info->sca_offset;
3708 info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3709 if (!info->statctrl_base) {
3710 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3711 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3712 info->init_error = DiagStatus_CantAssignPciResources;
3715 info->statctrl_base += info->statctrl_offset;
3717 if ( !memory_test(info) ) {
3718 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3719 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3720 info->init_error = DiagStatus_MemoryError;
3727 release_resources( info );
3731 void release_resources(SLMP_INFO *info)
3733 if ( debug_level >= DEBUG_LEVEL_INFO )
3734 printk( "%s(%d):%s release_resources() entry\n",
3735 __FILE__,__LINE__,info->device_name );
3737 if ( info->irq_requested ) {
3738 free_irq(info->irq_level, info);
3739 info->irq_requested = 0;
3742 if ( info->shared_mem_requested ) {
3743 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3744 info->shared_mem_requested = 0;
3746 if ( info->lcr_mem_requested ) {
3747 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3748 info->lcr_mem_requested = 0;
3750 if ( info->sca_base_requested ) {
3751 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3752 info->sca_base_requested = 0;
3754 if ( info->sca_statctrl_requested ) {
3755 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3756 info->sca_statctrl_requested = 0;
3759 if (info->memory_base){
3760 iounmap(info->memory_base);
3761 info->memory_base = NULL;
3764 if (info->sca_base) {
3765 iounmap(info->sca_base - info->sca_offset);
3766 info->sca_base=NULL;
3769 if (info->statctrl_base) {
3770 iounmap(info->statctrl_base - info->statctrl_offset);
3771 info->statctrl_base=NULL;
3774 if (info->lcr_base){
3775 iounmap(info->lcr_base - info->lcr_offset);
3776 info->lcr_base = NULL;
3779 if ( debug_level >= DEBUG_LEVEL_INFO )
3780 printk( "%s(%d):%s release_resources() exit\n",
3781 __FILE__,__LINE__,info->device_name );
3784 /* Add the specified device instance data structure to the
3785 * global linked list of devices and increment the device count.
3787 void add_device(SLMP_INFO *info)
3789 info->next_device = NULL;
3790 info->line = synclinkmp_device_count;
3791 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3793 if (info->line < MAX_DEVICES) {
3794 if (maxframe[info->line])
3795 info->max_frame_size = maxframe[info->line];
3796 info->dosyncppp = dosyncppp[info->line];
3799 synclinkmp_device_count++;
3801 if ( !synclinkmp_device_list )
3802 synclinkmp_device_list = info;
3804 SLMP_INFO *current_dev = synclinkmp_device_list;
3805 while( current_dev->next_device )
3806 current_dev = current_dev->next_device;
3807 current_dev->next_device = info;
3810 if ( info->max_frame_size < 4096 )
3811 info->max_frame_size = 4096;
3812 else if ( info->max_frame_size > 65535 )
3813 info->max_frame_size = 65535;
3815 printk( "SyncLink MultiPort %s: "
3816 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3818 info->phys_sca_base,
3819 info->phys_memory_base,
3820 info->phys_statctrl_base,
3821 info->phys_lcr_base,
3823 info->max_frame_size );
3830 /* Allocate and initialize a device instance structure
3832 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3834 SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3838 info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3842 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3843 __FILE__,__LINE__, adapter_num, port_num);
3845 memset(info, 0, sizeof(SLMP_INFO));
3846 info->magic = MGSL_MAGIC;
3847 INIT_WORK(&info->task, bh_handler, info);
3848 info->max_frame_size = 4096;
3849 info->close_delay = 5*HZ/10;
3850 info->closing_wait = 30*HZ;
3851 init_waitqueue_head(&info->open_wait);
3852 init_waitqueue_head(&info->close_wait);
3853 init_waitqueue_head(&info->status_event_wait_q);
3854 init_waitqueue_head(&info->event_wait_q);
3855 spin_lock_init(&info->netlock);
3856 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3857 info->idle_mode = HDLC_TXIDLE_FLAGS;
3858 info->adapter_num = adapter_num;
3859 info->port_num = port_num;
3861 /* Copy configuration info to device instance data */
3862 info->irq_level = pdev->irq;
3863 info->phys_lcr_base = pci_resource_start(pdev,0);
3864 info->phys_sca_base = pci_resource_start(pdev,2);
3865 info->phys_memory_base = pci_resource_start(pdev,3);
3866 info->phys_statctrl_base = pci_resource_start(pdev,4);
3868 /* Because veremap only works on page boundaries we must map
3869 * a larger area than is actually implemented for the LCR
3870 * memory range. We map a full page starting at the page boundary.
3872 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3873 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3875 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3876 info->phys_sca_base &= ~(PAGE_SIZE-1);
3878 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3879 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3881 info->bus_type = MGSL_BUS_TYPE_PCI;
3882 info->irq_flags = SA_SHIRQ;
3884 init_timer(&info->tx_timer);
3885 info->tx_timer.data = (unsigned long)info;
3886 info->tx_timer.function = tx_timeout;
3888 init_timer(&info->status_timer);
3889 info->status_timer.data = (unsigned long)info;
3890 info->status_timer.function = status_timeout;
3892 /* Store the PCI9050 misc control register value because a flaw
3893 * in the PCI9050 prevents LCR registers from being read if
3894 * BIOS assigns an LCR base address with bit 7 set.
3896 * Only the misc control register is accessed for which only
3897 * write access is needed, so set an initial value and change
3898 * bits to the device instance data as we write the value
3899 * to the actual misc control register.
3901 info->misc_ctrl_value = 0x087e4546;
3903 /* initial port state is unknown - if startup errors
3904 * occur, init_error will be set to indicate the
3905 * problem. Once the port is fully initialized,
3906 * this value will be set to 0 to indicate the
3907 * port is available.
3909 info->init_error = -1;
3915 void device_init(int adapter_num, struct pci_dev *pdev)
3917 SLMP_INFO *port_array[SCA_MAX_PORTS];
3920 /* allocate device instances for up to SCA_MAX_PORTS devices */
3921 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3922 port_array[port] = alloc_dev(adapter_num,port,pdev);
3923 if( port_array[port] == NULL ) {
3924 for ( --port; port >= 0; --port )
3925 kfree(port_array[port]);
3930 /* give copy of port_array to all ports and add to device list */
3931 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3932 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3933 add_device( port_array[port] );
3934 spin_lock_init(&port_array[port]->lock);
3937 /* Allocate and claim adapter resources */
3938 if ( !claim_resources(port_array[0]) ) {
3940 alloc_dma_bufs(port_array[0]);
3942 /* copy resource information from first port to others */
3943 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3944 port_array[port]->lock = port_array[0]->lock;
3945 port_array[port]->irq_level = port_array[0]->irq_level;
3946 port_array[port]->memory_base = port_array[0]->memory_base;
3947 port_array[port]->sca_base = port_array[0]->sca_base;
3948 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3949 port_array[port]->lcr_base = port_array[0]->lcr_base;
3950 alloc_dma_bufs(port_array[port]);
3953 if ( request_irq(port_array[0]->irq_level,
3954 synclinkmp_interrupt,
3955 port_array[0]->irq_flags,
3956 port_array[0]->device_name,
3957 port_array[0]) < 0 ) {
3958 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3960 port_array[0]->device_name,
3961 port_array[0]->irq_level );
3964 port_array[0]->irq_requested = 1;
3965 adapter_test(port_array[0]);
3970 static struct tty_operations ops = {
3974 .put_char = put_char,
3975 .flush_chars = flush_chars,
3976 .write_room = write_room,
3977 .chars_in_buffer = chars_in_buffer,
3978 .flush_buffer = flush_buffer,
3980 .throttle = throttle,
3981 .unthrottle = unthrottle,
3982 .send_xchar = send_xchar,
3983 .break_ctl = set_break,
3984 .wait_until_sent = wait_until_sent,
3985 .read_proc = read_proc,
3986 .set_termios = set_termios,
3988 .start = tx_release,
3990 .tiocmget = tiocmget,
3991 .tiocmset = tiocmset,
3994 static void synclinkmp_cleanup(void)
4000 printk("Unloading %s %s\n", driver_name, driver_version);
4002 if (serial_driver) {
4003 if ((rc = tty_unregister_driver(serial_driver)))
4004 printk("%s(%d) failed to unregister tty driver err=%d\n",
4005 __FILE__,__LINE__,rc);
4006 put_tty_driver(serial_driver);
4010 info = synclinkmp_device_list;
4013 info = info->next_device;
4016 /* release devices */
4017 info = synclinkmp_device_list;
4022 free_dma_bufs(info);
4023 free_tmp_rx_buf(info);
4024 if ( info->port_num == 0 ) {
4026 write_reg(info, LPR, 1); /* set low power mode */
4027 release_resources(info);
4030 info = info->next_device;
4034 pci_unregister_driver(&synclinkmp_pci_driver);
4037 /* Driver initialization entry point.
4040 static int __init synclinkmp_init(void)
4044 if (break_on_load) {
4045 synclinkmp_get_text_ptr();
4049 printk("%s %s\n", driver_name, driver_version);
4051 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4052 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4056 serial_driver = alloc_tty_driver(128);
4057 if (!serial_driver) {
4062 /* Initialize the tty_driver structure */
4064 serial_driver->owner = THIS_MODULE;
4065 serial_driver->driver_name = "synclinkmp";
4066 serial_driver->name = "ttySLM";
4067 serial_driver->major = ttymajor;
4068 serial_driver->minor_start = 64;
4069 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4070 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4071 serial_driver->init_termios = tty_std_termios;
4072 serial_driver->init_termios.c_cflag =
4073 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4074 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4075 tty_set_operations(serial_driver, &ops);
4076 if ((rc = tty_register_driver(serial_driver)) < 0) {
4077 printk("%s(%d):Couldn't register serial driver\n",
4079 put_tty_driver(serial_driver);
4080 serial_driver = NULL;
4084 printk("%s %s, tty major#%d\n",
4085 driver_name, driver_version,
4086 serial_driver->major);
4091 synclinkmp_cleanup();
4095 static void __exit synclinkmp_exit(void)
4097 synclinkmp_cleanup();
4100 module_init(synclinkmp_init);
4101 module_exit(synclinkmp_exit);
4103 /* Set the port for internal loopback mode.
4104 * The TxCLK and RxCLK signals are generated from the BRG and
4105 * the TxD is looped back to the RxD internally.
4107 void enable_loopback(SLMP_INFO *info, int enable)
4110 /* MD2 (Mode Register 2)
4111 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4113 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4115 /* degate external TxC clock source */
4116 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4117 write_control_reg(info);
4119 /* RXS/TXS (Rx/Tx clock source)
4120 * 07 Reserved, must be 0
4121 * 06..04 Clock Source, 100=BRG
4122 * 03..00 Clock Divisor, 0000=1
4124 write_reg(info, RXS, 0x40);
4125 write_reg(info, TXS, 0x40);
4128 /* MD2 (Mode Register 2)
4129 * 01..00 CNCT<1..0> Channel connection, 0=normal
4131 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4133 /* RXS/TXS (Rx/Tx clock source)
4134 * 07 Reserved, must be 0
4135 * 06..04 Clock Source, 000=RxC/TxC Pin
4136 * 03..00 Clock Divisor, 0000=1
4138 write_reg(info, RXS, 0x00);
4139 write_reg(info, TXS, 0x00);
4142 /* set LinkSpeed if available, otherwise default to 2Mbps */
4143 if (info->params.clock_speed)
4144 set_rate(info, info->params.clock_speed);
4146 set_rate(info, 3686400);
4149 /* Set the baud rate register to the desired speed
4151 * data_rate data rate of clock in bits per second
4152 * A data rate of 0 disables the AUX clock.
4154 void set_rate( SLMP_INFO *info, u32 data_rate )
4157 unsigned char BRValue;
4160 /* fBRG = fCLK/(TMC * 2^BR)
4162 if (data_rate != 0) {
4163 Divisor = 14745600/data_rate;
4170 if (TMCValue != 1 && TMCValue != 2) {
4171 /* BRValue of 0 provides 50/50 duty cycle *only* when
4172 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4179 /* while TMCValue is too big for TMC register, divide
4180 * by 2 and increment BR exponent.
4182 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4185 write_reg(info, TXS,
4186 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4187 write_reg(info, RXS,
4188 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4189 write_reg(info, TMC, (unsigned char)TMCValue);
4192 write_reg(info, TXS,0);
4193 write_reg(info, RXS,0);
4194 write_reg(info, TMC, 0);
4200 void rx_stop(SLMP_INFO *info)
4202 if (debug_level >= DEBUG_LEVEL_ISR)
4203 printk("%s(%d):%s rx_stop()\n",
4204 __FILE__,__LINE__, info->device_name );
4206 write_reg(info, CMD, RXRESET);
4208 info->ie0_value &= ~RXRDYE;
4209 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4211 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4212 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4213 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4215 info->rx_enabled = 0;
4216 info->rx_overflow = 0;
4219 /* enable the receiver
4221 void rx_start(SLMP_INFO *info)
4225 if (debug_level >= DEBUG_LEVEL_ISR)
4226 printk("%s(%d):%s rx_start()\n",
4227 __FILE__,__LINE__, info->device_name );
4229 write_reg(info, CMD, RXRESET);
4231 if ( info->params.mode == MGSL_MODE_HDLC ) {
4232 /* HDLC, disabe IRQ on rxdata */
4233 info->ie0_value &= ~RXRDYE;
4234 write_reg(info, IE0, info->ie0_value);
4236 /* Reset all Rx DMA buffers and program rx dma */
4237 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4238 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4240 for (i = 0; i < info->rx_buf_count; i++) {
4241 info->rx_buf_list[i].status = 0xff;
4243 // throttle to 4 shared memory writes at a time to prevent
4244 // hogging local bus (keep latency time for DMA requests low).
4246 read_status_reg(info);
4248 info->current_rx_buf = 0;
4250 /* set current/1st descriptor address */
4251 write_reg16(info, RXDMA + CDA,
4252 info->rx_buf_list_ex[0].phys_entry);
4254 /* set new last rx descriptor address */
4255 write_reg16(info, RXDMA + EDA,
4256 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4258 /* set buffer length (shared by all rx dma data buffers) */
4259 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4261 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4262 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4264 /* async, enable IRQ on rxdata */
4265 info->ie0_value |= RXRDYE;
4266 write_reg(info, IE0, info->ie0_value);
4269 write_reg(info, CMD, RXENABLE);
4271 info->rx_overflow = FALSE;
4272 info->rx_enabled = 1;
4275 /* Enable the transmitter and send a transmit frame if
4276 * one is loaded in the DMA buffers.
4278 void tx_start(SLMP_INFO *info)
4280 if (debug_level >= DEBUG_LEVEL_ISR)
4281 printk("%s(%d):%s tx_start() tx_count=%d\n",
4282 __FILE__,__LINE__, info->device_name,info->tx_count );
4284 if (!info->tx_enabled ) {
4285 write_reg(info, CMD, TXRESET);
4286 write_reg(info, CMD, TXENABLE);
4287 info->tx_enabled = TRUE;
4290 if ( info->tx_count ) {
4292 /* If auto RTS enabled and RTS is inactive, then assert */
4293 /* RTS and set a flag indicating that the driver should */
4294 /* negate RTS when the transmission completes. */
4296 info->drop_rts_on_tx_done = 0;
4298 if (info->params.mode != MGSL_MODE_ASYNC) {
4300 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4301 get_signals( info );
4302 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4303 info->serial_signals |= SerialSignal_RTS;
4304 set_signals( info );
4305 info->drop_rts_on_tx_done = 1;
4309 write_reg16(info, TRC0,
4310 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4312 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4313 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4315 /* set TX CDA (current descriptor address) */
4316 write_reg16(info, TXDMA + CDA,
4317 info->tx_buf_list_ex[0].phys_entry);
4319 /* set TX EDA (last descriptor address) */
4320 write_reg16(info, TXDMA + EDA,
4321 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4323 /* enable underrun IRQ */
4324 info->ie1_value &= ~IDLE;
4325 info->ie1_value |= UDRN;
4326 write_reg(info, IE1, info->ie1_value);
4327 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4329 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4330 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4332 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4333 add_timer(&info->tx_timer);
4337 /* async, enable IRQ on txdata */
4338 info->ie0_value |= TXRDYE;
4339 write_reg(info, IE0, info->ie0_value);
4342 info->tx_active = 1;
4346 /* stop the transmitter and DMA
4348 void tx_stop( SLMP_INFO *info )
4350 if (debug_level >= DEBUG_LEVEL_ISR)
4351 printk("%s(%d):%s tx_stop()\n",
4352 __FILE__,__LINE__, info->device_name );
4354 del_timer(&info->tx_timer);
4356 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4357 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4359 write_reg(info, CMD, TXRESET);
4361 info->ie1_value &= ~(UDRN + IDLE);
4362 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4363 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4365 info->ie0_value &= ~TXRDYE;
4366 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4368 info->tx_enabled = 0;
4369 info->tx_active = 0;
4372 /* Fill the transmit FIFO until the FIFO is full or
4373 * there is no more data to load.
4375 void tx_load_fifo(SLMP_INFO *info)
4379 /* do nothing is now tx data available and no XON/XOFF pending */
4381 if ( !info->tx_count && !info->x_char )
4384 /* load the Transmit FIFO until FIFOs full or all data sent */
4386 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4388 /* there is more space in the transmit FIFO and */
4389 /* there is more data in transmit buffer */
4391 if ( (info->tx_count > 1) && !info->x_char ) {
4393 TwoBytes[0] = info->tx_buf[info->tx_get++];
4394 if (info->tx_get >= info->max_frame_size)
4395 info->tx_get -= info->max_frame_size;
4396 TwoBytes[1] = info->tx_buf[info->tx_get++];
4397 if (info->tx_get >= info->max_frame_size)
4398 info->tx_get -= info->max_frame_size;
4400 write_reg16(info, TRB, *((u16 *)TwoBytes));
4402 info->tx_count -= 2;
4403 info->icount.tx += 2;
4405 /* only 1 byte left to transmit or 1 FIFO slot left */
4408 /* transmit pending high priority char */
4409 write_reg(info, TRB, info->x_char);
4412 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4413 if (info->tx_get >= info->max_frame_size)
4414 info->tx_get -= info->max_frame_size;
4422 /* Reset a port to a known state
4424 void reset_port(SLMP_INFO *info)
4426 if (info->sca_base) {
4431 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4434 /* disable all port interrupts */
4435 info->ie0_value = 0;
4436 info->ie1_value = 0;
4437 info->ie2_value = 0;
4438 write_reg(info, IE0, info->ie0_value);
4439 write_reg(info, IE1, info->ie1_value);
4440 write_reg(info, IE2, info->ie2_value);
4442 write_reg(info, CMD, CHRESET);
4446 /* Reset all the ports to a known state.
4448 void reset_adapter(SLMP_INFO *info)
4452 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4453 if (info->port_array[i])
4454 reset_port(info->port_array[i]);
4458 /* Program port for asynchronous communications.
4460 void async_mode(SLMP_INFO *info)
4463 unsigned char RegValue;
4468 /* MD0, Mode Register 0
4470 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4471 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4472 * 03 Reserved, must be 0
4473 * 02 CRCCC, CRC Calculation, 0=disabled
4474 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4479 if (info->params.stop_bits != 1)
4481 write_reg(info, MD0, RegValue);
4483 /* MD1, Mode Register 1
4485 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4486 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4487 * 03..02 RXCHR<1..0>, rx char size
4488 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4493 switch (info->params.data_bits) {
4494 case 7: RegValue |= BIT4 + BIT2; break;
4495 case 6: RegValue |= BIT5 + BIT3; break;
4496 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4498 if (info->params.parity != ASYNC_PARITY_NONE) {
4500 if (info->params.parity == ASYNC_PARITY_ODD)
4503 write_reg(info, MD1, RegValue);
4505 /* MD2, Mode Register 2
4507 * 07..02 Reserved, must be 0
4508 * 01..00 CNCT<1..0> Channel connection, 0=normal
4513 write_reg(info, MD2, RegValue);
4515 /* RXS, Receive clock source
4517 * 07 Reserved, must be 0
4518 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4519 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4522 write_reg(info, RXS, RegValue);
4524 /* TXS, Transmit clock source
4526 * 07 Reserved, must be 0
4527 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4528 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4531 write_reg(info, TXS, RegValue);
4535 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4537 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4538 write_control_reg(info);
4542 /* RRC Receive Ready Control 0
4544 * 07..05 Reserved, must be 0
4545 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4547 write_reg(info, TRC0, 0x00);
4549 /* TRC0 Transmit Ready Control 0
4551 * 07..05 Reserved, must be 0
4552 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4554 write_reg(info, TRC0, 0x10);
4556 /* TRC1 Transmit Ready Control 1
4558 * 07..05 Reserved, must be 0
4559 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4561 write_reg(info, TRC1, 0x1e);
4563 /* CTL, MSCI control register
4565 * 07..06 Reserved, set to 0
4566 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4567 * 04 IDLC, idle control, 0=mark 1=idle register
4568 * 03 BRK, break, 0=off 1 =on (async)
4569 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4570 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4571 * 00 RTS, RTS output control, 0=active 1=inactive
4576 if (!(info->serial_signals & SerialSignal_RTS))
4578 write_reg(info, CTL, RegValue);
4580 /* enable status interrupts */
4581 info->ie0_value |= TXINTE + RXINTE;
4582 write_reg(info, IE0, info->ie0_value);
4584 /* enable break detect interrupt */
4585 info->ie1_value = BRKD;
4586 write_reg(info, IE1, info->ie1_value);
4588 /* enable rx overrun interrupt */
4589 info->ie2_value = OVRN;
4590 write_reg(info, IE2, info->ie2_value);
4592 set_rate( info, info->params.data_rate * 16 );
4594 if (info->params.loopback)
4595 enable_loopback(info,1);
4598 /* Program the SCA for HDLC communications.
4600 void hdlc_mode(SLMP_INFO *info)
4602 unsigned char RegValue;
4605 // Can't use DPLL because SCA outputs recovered clock on RxC when
4606 // DPLL mode selected. This causes output contention with RxC receiver.
4607 // Use of DPLL would require external hardware to disable RxC receiver
4608 // when DPLL mode selected.
4609 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4611 /* disable DMA interrupts */
4612 write_reg(info, TXDMA + DIR, 0);
4613 write_reg(info, RXDMA + DIR, 0);
4615 /* MD0, Mode Register 0
4617 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4618 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4619 * 03 Reserved, must be 0
4620 * 02 CRCCC, CRC Calculation, 1=enabled
4621 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4622 * 00 CRC0, CRC initial value, 1 = all 1s
4627 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4629 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4631 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4632 RegValue |= BIT2 + BIT1;
4633 write_reg(info, MD0, RegValue);
4635 /* MD1, Mode Register 1
4637 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4638 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4639 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4640 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4645 write_reg(info, MD1, RegValue);
4647 /* MD2, Mode Register 2
4649 * 07 NRZFM, 0=NRZ, 1=FM
4650 * 06..05 CODE<1..0> Encoding, 00=NRZ
4651 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4652 * 02 Reserved, must be 0
4653 * 01..00 CNCT<1..0> Channel connection, 0=normal
4658 switch(info->params.encoding) {
4659 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4660 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4661 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4662 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4664 case HDLC_ENCODING_NRZB: /* not supported */
4665 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4666 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4669 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4672 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4678 write_reg(info, MD2, RegValue);
4681 /* RXS, Receive clock source
4683 * 07 Reserved, must be 0
4684 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4685 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4688 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4690 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4691 RegValue |= BIT6 + BIT5;
4692 write_reg(info, RXS, RegValue);
4694 /* TXS, Transmit clock source
4696 * 07 Reserved, must be 0
4697 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4698 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4701 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4703 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4704 RegValue |= BIT6 + BIT5;
4705 write_reg(info, TXS, RegValue);
4707 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4708 set_rate(info, info->params.clock_speed * DpllDivisor);
4710 set_rate(info, info->params.clock_speed);
4712 /* GPDATA (General Purpose I/O Data Register)
4714 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4716 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4717 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4719 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4720 write_control_reg(info);
4722 /* RRC Receive Ready Control 0
4724 * 07..05 Reserved, must be 0
4725 * 04..00 RRC<4..0> Rx FIFO trigger active
4727 write_reg(info, RRC, rx_active_fifo_level);
4729 /* TRC0 Transmit Ready Control 0
4731 * 07..05 Reserved, must be 0
4732 * 04..00 TRC<4..0> Tx FIFO trigger active
4734 write_reg(info, TRC0, tx_active_fifo_level);
4736 /* TRC1 Transmit Ready Control 1
4738 * 07..05 Reserved, must be 0
4739 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4741 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4743 /* DMR, DMA Mode Register
4745 * 07..05 Reserved, must be 0
4746 * 04 TMOD, Transfer Mode: 1=chained-block
4747 * 03 Reserved, must be 0
4748 * 02 NF, Number of Frames: 1=multi-frame
4749 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4750 * 00 Reserved, must be 0
4754 write_reg(info, TXDMA + DMR, 0x14);
4755 write_reg(info, RXDMA + DMR, 0x14);
4757 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4758 write_reg(info, RXDMA + CPB,
4759 (unsigned char)(info->buffer_list_phys >> 16));
4761 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4762 write_reg(info, TXDMA + CPB,
4763 (unsigned char)(info->buffer_list_phys >> 16));
4765 /* enable status interrupts. other code enables/disables
4766 * the individual sources for these two interrupt classes.
4768 info->ie0_value |= TXINTE + RXINTE;
4769 write_reg(info, IE0, info->ie0_value);
4771 /* CTL, MSCI control register
4773 * 07..06 Reserved, set to 0
4774 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4775 * 04 IDLC, idle control, 0=mark 1=idle register
4776 * 03 BRK, break, 0=off 1 =on (async)
4777 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4778 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4779 * 00 RTS, RTS output control, 0=active 1=inactive
4784 if (!(info->serial_signals & SerialSignal_RTS))
4786 write_reg(info, CTL, RegValue);
4788 /* preamble not supported ! */
4794 set_rate(info, info->params.clock_speed);
4796 if (info->params.loopback)
4797 enable_loopback(info,1);
4800 /* Set the transmit HDLC idle mode
4802 void tx_set_idle(SLMP_INFO *info)
4804 unsigned char RegValue = 0xff;
4806 /* Map API idle mode to SCA register bits */
4807 switch(info->idle_mode) {
4808 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4809 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4810 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4811 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4812 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4813 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4814 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4817 write_reg(info, IDL, RegValue);
4820 /* Query the adapter for the state of the V24 status (input) signals.
4822 void get_signals(SLMP_INFO *info)
4824 u16 status = read_reg(info, SR3);
4825 u16 gpstatus = read_status_reg(info);
4828 /* clear all serial signals except DTR and RTS */
4829 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4831 /* set serial signal bits to reflect MISR */
4833 if (!(status & BIT3))
4834 info->serial_signals |= SerialSignal_CTS;
4836 if ( !(status & BIT2))
4837 info->serial_signals |= SerialSignal_DCD;
4839 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4840 if (!(gpstatus & testbit))
4841 info->serial_signals |= SerialSignal_RI;
4843 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4844 if (!(gpstatus & testbit))
4845 info->serial_signals |= SerialSignal_DSR;
4848 /* Set the state of DTR and RTS based on contents of
4849 * serial_signals member of device context.
4851 void set_signals(SLMP_INFO *info)
4853 unsigned char RegValue;
4856 RegValue = read_reg(info, CTL);
4857 if (info->serial_signals & SerialSignal_RTS)
4861 write_reg(info, CTL, RegValue);
4863 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4864 EnableBit = BIT1 << (info->port_num*2);
4865 if (info->serial_signals & SerialSignal_DTR)
4866 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4868 info->port_array[0]->ctrlreg_value |= EnableBit;
4869 write_control_reg(info);
4872 /*******************/
4873 /* DMA Buffer Code */
4874 /*******************/
4876 /* Set the count for all receive buffers to SCABUFSIZE
4877 * and set the current buffer to the first buffer. This effectively
4878 * makes all buffers free and discards any data in buffers.
4880 void rx_reset_buffers(SLMP_INFO *info)
4882 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4885 /* Free the buffers used by a received frame
4887 * info pointer to device instance data
4888 * first index of 1st receive buffer of frame
4889 * last index of last receive buffer of frame
4891 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4896 /* reset current buffer for reuse */
4897 info->rx_buf_list[first].status = 0xff;
4899 if (first == last) {
4901 /* set new last rx descriptor address */
4902 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4906 if (first == info->rx_buf_count)
4910 /* set current buffer to next buffer after last buffer of frame */
4911 info->current_rx_buf = first;
4914 /* Return a received frame from the receive DMA buffers.
4915 * Only frames received without errors are returned.
4917 * Return Value: 1 if frame returned, otherwise 0
4919 int rx_get_frame(SLMP_INFO *info)
4921 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4922 unsigned short status;
4923 unsigned int framesize = 0;
4925 unsigned long flags;
4926 struct tty_struct *tty = info->tty;
4927 unsigned char addr_field = 0xff;
4929 SCADESC_EX *desc_ex;
4932 /* assume no frame returned, set zero length */
4937 * current_rx_buf points to the 1st buffer of the next available
4938 * receive frame. To find the last buffer of the frame look for
4939 * a non-zero status field in the buffer entries. (The status
4940 * field is set by the 16C32 after completing a receive frame.
4942 StartIndex = EndIndex = info->current_rx_buf;
4945 desc = &info->rx_buf_list[EndIndex];
4946 desc_ex = &info->rx_buf_list_ex[EndIndex];
4948 if (desc->status == 0xff)
4949 goto Cleanup; /* current desc still in use, no frames available */
4951 if (framesize == 0 && info->params.addr_filter != 0xff)
4952 addr_field = desc_ex->virt_addr[0];
4954 framesize += desc->length;
4956 /* Status != 0 means last buffer of frame */
4961 if (EndIndex == info->rx_buf_count)
4964 if (EndIndex == info->current_rx_buf) {
4965 /* all buffers have been 'used' but none mark */
4966 /* the end of a frame. Reset buffers and receiver. */
4967 if ( info->rx_enabled ){
4968 spin_lock_irqsave(&info->lock,flags);
4970 spin_unlock_irqrestore(&info->lock,flags);
4977 /* check status of receive frame */
4979 /* frame status is byte stored after frame data
4981 * 7 EOM (end of msg), 1 = last buffer of frame
4982 * 6 Short Frame, 1 = short frame
4983 * 5 Abort, 1 = frame aborted
4984 * 4 Residue, 1 = last byte is partial
4985 * 3 Overrun, 1 = overrun occurred during frame reception
4986 * 2 CRC, 1 = CRC error detected
4989 status = desc->status;
4991 /* ignore CRC bit if not using CRC (bit is undefined) */
4992 /* Note:CRC is not save to data buffer */
4993 if (info->params.crc_type == HDLC_CRC_NONE)
4996 if (framesize == 0 ||
4997 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4998 /* discard 0 byte frames, this seems to occur sometime
4999 * when remote is idling flags.
5001 rx_free_frame_buffers(info, StartIndex, EndIndex);
5008 if (status & (BIT6+BIT5+BIT3+BIT2)) {
5009 /* received frame has errors,
5010 * update counts and mark frame size as 0
5013 info->icount.rxshort++;
5014 else if (status & BIT5)
5015 info->icount.rxabort++;
5016 else if (status & BIT3)
5017 info->icount.rxover++;
5019 info->icount.rxcrc++;
5024 struct net_device_stats *stats = hdlc_stats(info->netdev);
5026 stats->rx_frame_errors++;
5031 if ( debug_level >= DEBUG_LEVEL_BH )
5032 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5033 __FILE__,__LINE__,info->device_name,status,framesize);
5035 if ( debug_level >= DEBUG_LEVEL_DATA )
5036 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5037 min_t(int, framesize,SCABUFSIZE),0);
5040 if (framesize > info->max_frame_size)
5041 info->icount.rxlong++;
5043 /* copy dma buffer(s) to contiguous intermediate buffer */
5044 int copy_count = framesize;
5045 int index = StartIndex;
5046 unsigned char *ptmp = info->tmp_rx_buf;
5047 info->tmp_rx_buf_count = framesize;
5049 info->icount.rxok++;
5052 int partial_count = min(copy_count,SCABUFSIZE);
5054 info->rx_buf_list_ex[index].virt_addr,
5056 ptmp += partial_count;
5057 copy_count -= partial_count;
5059 if ( ++index == info->rx_buf_count )
5065 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5068 ldisc_receive_buf(tty,info->tmp_rx_buf,
5069 info->flag_buf, framesize);
5072 /* Free the buffers used by this frame. */
5073 rx_free_frame_buffers( info, StartIndex, EndIndex );
5078 if ( info->rx_enabled && info->rx_overflow ) {
5079 /* Receiver is enabled, but needs to restarted due to
5080 * rx buffer overflow. If buffers are empty, restart receiver.
5082 if (info->rx_buf_list[EndIndex].status == 0xff) {
5083 spin_lock_irqsave(&info->lock,flags);
5085 spin_unlock_irqrestore(&info->lock,flags);
5092 /* load the transmit DMA buffer with data
5094 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5096 unsigned short copy_count;
5099 SCADESC_EX *desc_ex;
5101 if ( debug_level >= DEBUG_LEVEL_DATA )
5102 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5104 /* Copy source buffer to one or more DMA buffers, starting with
5105 * the first transmit dma buffer.
5109 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5111 desc = &info->tx_buf_list[i];
5112 desc_ex = &info->tx_buf_list_ex[i];
5114 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5116 desc->length = copy_count;
5120 count -= copy_count;
5126 if (i >= info->tx_buf_count)
5130 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5131 info->last_tx_buf = ++i;
5134 int register_test(SLMP_INFO *info)
5136 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5137 static unsigned int count = sizeof(testval)/sizeof(unsigned char);
5140 unsigned long flags;
5142 spin_lock_irqsave(&info->lock,flags);
5145 /* assume failure */
5146 info->init_error = DiagStatus_AddressFailure;
5148 /* Write bit patterns to various registers but do it out of */
5149 /* sync, then read back and verify values. */
5151 for (i = 0 ; i < count ; i++) {
5152 write_reg(info, TMC, testval[i]);
5153 write_reg(info, IDL, testval[(i+1)%count]);
5154 write_reg(info, SA0, testval[(i+2)%count]);
5155 write_reg(info, SA1, testval[(i+3)%count]);
5157 if ( (read_reg(info, TMC) != testval[i]) ||
5158 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5159 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5160 (read_reg(info, SA1) != testval[(i+3)%count]) )
5168 spin_unlock_irqrestore(&info->lock,flags);
5173 int irq_test(SLMP_INFO *info)
5175 unsigned long timeout;
5176 unsigned long flags;
5178 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5180 spin_lock_irqsave(&info->lock,flags);
5183 /* assume failure */
5184 info->init_error = DiagStatus_IrqFailure;
5185 info->irq_occurred = FALSE;
5187 /* setup timer0 on SCA0 to interrupt */
5189 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5190 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5192 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5193 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5196 /* TMCS, Timer Control/Status Register
5198 * 07 CMF, Compare match flag (read only) 1=match
5199 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5200 * 05 Reserved, must be 0
5201 * 04 TME, Timer Enable
5202 * 03..00 Reserved, must be 0
5206 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5208 spin_unlock_irqrestore(&info->lock,flags);
5211 while( timeout-- && !info->irq_occurred ) {
5212 set_current_state(TASK_INTERRUPTIBLE);
5213 schedule_timeout(msecs_to_jiffies(10));
5216 spin_lock_irqsave(&info->lock,flags);
5218 spin_unlock_irqrestore(&info->lock,flags);
5220 return info->irq_occurred;
5223 /* initialize individual SCA device (2 ports)
5225 int sca_init(SLMP_INFO *info)
5227 /* set wait controller to single mem partition (low), no wait states */
5228 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5229 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5230 write_reg(info, WCRL, 0); /* wait controller low range */
5231 write_reg(info, WCRM, 0); /* wait controller mid range */
5232 write_reg(info, WCRH, 0); /* wait controller high range */
5234 /* DPCR, DMA Priority Control
5236 * 07..05 Not used, must be 0
5237 * 04 BRC, bus release condition: 0=all transfers complete
5238 * 03 CCC, channel change condition: 0=every cycle
5239 * 02..00 PR<2..0>, priority 100=round robin
5243 write_reg(info, DPCR, dma_priority);
5245 /* DMA Master Enable, BIT7: 1=enable all channels */
5246 write_reg(info, DMER, 0x80);
5248 /* enable all interrupt classes */
5249 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5250 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5251 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5253 /* ITCR, interrupt control register
5254 * 07 IPC, interrupt priority, 0=MSCI->DMA
5255 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5256 * 04 VOS, Vector Output, 0=unmodified vector
5257 * 03..00 Reserved, must be 0
5259 write_reg(info, ITCR, 0);
5264 /* initialize adapter hardware
5266 int init_adapter(SLMP_INFO *info)
5270 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5271 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5274 info->misc_ctrl_value |= BIT30;
5275 *MiscCtrl = info->misc_ctrl_value;
5278 * Force at least 170ns delay before clearing
5279 * reset bit. Each read from LCR takes at least
5280 * 30ns so 10 times for 300ns to be safe.
5283 readval = *MiscCtrl;
5285 info->misc_ctrl_value &= ~BIT30;
5286 *MiscCtrl = info->misc_ctrl_value;
5288 /* init control reg (all DTRs off, all clksel=input) */
5289 info->ctrlreg_value = 0xaa;
5290 write_control_reg(info);
5293 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5294 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5296 switch(read_ahead_count)
5299 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5302 lcr1_brdr_value |= BIT5 + BIT4;
5305 lcr1_brdr_value |= BIT5 + BIT3;
5308 lcr1_brdr_value |= BIT5;
5312 *LCR1BRDR = lcr1_brdr_value;
5313 *MiscCtrl = misc_ctrl_value;
5316 sca_init(info->port_array[0]);
5317 sca_init(info->port_array[2]);
5322 /* Loopback an HDLC frame to test the hardware
5323 * interrupt and DMA functions.
5325 int loopback_test(SLMP_INFO *info)
5327 #define TESTFRAMESIZE 20
5329 unsigned long timeout;
5330 u16 count = TESTFRAMESIZE;
5331 unsigned char buf[TESTFRAMESIZE];
5333 unsigned long flags;
5335 struct tty_struct *oldtty = info->tty;
5336 u32 speed = info->params.clock_speed;
5338 info->params.clock_speed = 3686400;
5341 /* assume failure */
5342 info->init_error = DiagStatus_DmaFailure;
5344 /* build and send transmit frame */
5345 for (count = 0; count < TESTFRAMESIZE;++count)
5346 buf[count] = (unsigned char)count;
5348 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5350 /* program hardware for HDLC and enabled receiver */
5351 spin_lock_irqsave(&info->lock,flags);
5353 enable_loopback(info,1);
5355 info->tx_count = count;
5356 tx_load_dma_buffer(info,buf,count);
5358 spin_unlock_irqrestore(&info->lock,flags);
5360 /* wait for receive complete */
5361 /* Set a timeout for waiting for interrupt. */
5362 for ( timeout = 100; timeout; --timeout ) {
5363 set_current_state(TASK_INTERRUPTIBLE);
5364 schedule_timeout(msecs_to_jiffies(10));
5366 if (rx_get_frame(info)) {
5372 /* verify received frame length and contents */
5374 ( info->tmp_rx_buf_count != count ||
5375 memcmp(buf, info->tmp_rx_buf,count))) {
5379 spin_lock_irqsave(&info->lock,flags);
5380 reset_adapter(info);
5381 spin_unlock_irqrestore(&info->lock,flags);
5383 info->params.clock_speed = speed;
5389 /* Perform diagnostics on hardware
5391 int adapter_test( SLMP_INFO *info )
5393 unsigned long flags;
5394 if ( debug_level >= DEBUG_LEVEL_INFO )
5395 printk( "%s(%d):Testing device %s\n",
5396 __FILE__,__LINE__,info->device_name );
5398 spin_lock_irqsave(&info->lock,flags);
5400 spin_unlock_irqrestore(&info->lock,flags);
5402 info->port_array[0]->port_count = 0;
5404 if ( register_test(info->port_array[0]) &&
5405 register_test(info->port_array[1])) {
5407 info->port_array[0]->port_count = 2;
5409 if ( register_test(info->port_array[2]) &&
5410 register_test(info->port_array[3]) )
5411 info->port_array[0]->port_count += 2;
5414 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5415 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5419 if ( !irq_test(info->port_array[0]) ||
5420 !irq_test(info->port_array[1]) ||
5421 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5422 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5423 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5424 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5428 if (!loopback_test(info->port_array[0]) ||
5429 !loopback_test(info->port_array[1]) ||
5430 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5431 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5432 printk( "%s(%d):DMA test failure for device %s\n",
5433 __FILE__,__LINE__,info->device_name);
5437 if ( debug_level >= DEBUG_LEVEL_INFO )
5438 printk( "%s(%d):device %s passed diagnostics\n",
5439 __FILE__,__LINE__,info->device_name );
5441 info->port_array[0]->init_error = 0;
5442 info->port_array[1]->init_error = 0;
5443 if ( info->port_count > 2 ) {
5444 info->port_array[2]->init_error = 0;
5445 info->port_array[3]->init_error = 0;
5451 /* Test the shared memory on a PCI adapter.
5453 int memory_test(SLMP_INFO *info)
5455 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5456 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5457 unsigned long count = sizeof(testval)/sizeof(unsigned long);
5459 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5460 unsigned long * addr = (unsigned long *)info->memory_base;
5462 /* Test data lines with test pattern at one location. */
5464 for ( i = 0 ; i < count ; i++ ) {
5466 if ( *addr != testval[i] )
5470 /* Test address lines with incrementing pattern over */
5471 /* entire address range. */
5473 for ( i = 0 ; i < limit ; i++ ) {
5478 addr = (unsigned long *)info->memory_base;
5480 for ( i = 0 ; i < limit ; i++ ) {
5481 if ( *addr != i * 4 )
5486 memset( info->memory_base, 0, SCA_MEM_SIZE );
5490 /* Load data into PCI adapter shared memory.
5492 * The PCI9050 releases control of the local bus
5493 * after completing the current read or write operation.
5495 * While the PCI9050 write FIFO not empty, the
5496 * PCI9050 treats all of the writes as a single transaction
5497 * and does not release the bus. This causes DMA latency problems
5498 * at high speeds when copying large data blocks to the shared memory.
5500 * This function breaks a write into multiple transations by
5501 * interleaving a read which flushes the write FIFO and 'completes'
5502 * the write transation. This allows any pending DMA request to gain control
5503 * of the local bus in a timely fasion.
5505 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5507 /* A load interval of 16 allows for 4 32-bit writes at */
5508 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5510 unsigned short interval = count / sca_pci_load_interval;
5513 for ( i = 0 ; i < interval ; i++ )
5515 memcpy(dest, src, sca_pci_load_interval);
5516 read_status_reg(info);
5517 dest += sca_pci_load_interval;
5518 src += sca_pci_load_interval;
5521 memcpy(dest, src, count % sca_pci_load_interval);
5524 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5529 printk("%s tx data:\n",info->device_name);
5531 printk("%s rx data:\n",info->device_name);
5539 for(i=0;i<linecount;i++)
5540 printk("%02X ",(unsigned char)data[i]);
5543 for(i=0;i<linecount;i++) {
5544 if (data[i]>=040 && data[i]<=0176)
5545 printk("%c",data[i]);
5554 } /* end of trace_block() */
5556 /* called when HDLC frame times out
5557 * update stats and do tx completion processing
5559 void tx_timeout(unsigned long context)
5561 SLMP_INFO *info = (SLMP_INFO*)context;
5562 unsigned long flags;
5564 if ( debug_level >= DEBUG_LEVEL_INFO )
5565 printk( "%s(%d):%s tx_timeout()\n",
5566 __FILE__,__LINE__,info->device_name);
5567 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5568 info->icount.txtimeout++;
5570 spin_lock_irqsave(&info->lock,flags);
5571 info->tx_active = 0;
5572 info->tx_count = info->tx_put = info->tx_get = 0;
5574 spin_unlock_irqrestore(&info->lock,flags);
5578 hdlcdev_tx_done(info);
5584 /* called to periodically check the DSR/RI modem signal input status
5586 void status_timeout(unsigned long context)
5589 SLMP_INFO *info = (SLMP_INFO*)context;
5590 unsigned long flags;
5591 unsigned char delta;
5594 spin_lock_irqsave(&info->lock,flags);
5596 spin_unlock_irqrestore(&info->lock,flags);
5598 /* check for DSR/RI state change */
5600 delta = info->old_signals ^ info->serial_signals;
5601 info->old_signals = info->serial_signals;
5603 if (delta & SerialSignal_DSR)
5604 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5606 if (delta & SerialSignal_RI)
5607 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5609 if (delta & SerialSignal_DCD)
5610 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5612 if (delta & SerialSignal_CTS)
5613 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5616 isr_io_pin(info,status);
5618 info->status_timer.data = (unsigned long)info;
5619 info->status_timer.function = status_timeout;
5620 info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5621 add_timer(&info->status_timer);
5625 /* Register Access Routines -
5626 * All registers are memory mapped
5628 #define CALC_REGADDR() \
5629 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5630 if (info->port_num > 1) \
5631 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5632 if ( info->port_num & 1) { \
5634 RegAddr += 0x40; /* DMA access */ \
5635 else if (Addr > 0x1f && Addr < 0x60) \
5636 RegAddr += 0x20; /* MSCI access */ \
5640 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5645 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5651 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5654 return *((u16 *)RegAddr);
5657 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5660 *((u16 *)RegAddr) = Value;
5663 unsigned char read_status_reg(SLMP_INFO * info)
5665 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5669 void write_control_reg(SLMP_INFO * info)
5671 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5672 *RegAddr = info->port_array[0]->ctrlreg_value;
5676 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5677 const struct pci_device_id *ent)
5679 if (pci_enable_device(dev)) {
5680 printk("error enabling pci device %p\n", dev);
5683 device_init( ++synclinkmp_adapter_count, dev );
5687 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)