3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
11 * NMI handling support added by
12 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
14 * $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/smp.h>
26 #include <linux/pci.h>
27 #include <linux/time.h>
28 #include <linux/nmi.h>
29 #include <linux/rcupdate.h>
30 #include <linux/completion.h>
31 #include <linux/kobject.h>
32 #include <linux/platform_device.h>
34 #define EDAC_MC_LABEL_LEN 31
35 #define MC_PROC_NAME_MAX_LEN 7
38 #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
39 #else /* PAGE_SHIFT > 20 */
40 #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
43 #define edac_printk(level, prefix, fmt, arg...) \
44 printk(level "EDAC " prefix ": " fmt, ##arg)
46 #define edac_mc_printk(mci, level, fmt, arg...) \
47 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
49 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
50 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
52 /* prefixes for edac_printk() and edac_mc_printk() */
54 #define EDAC_PCI "PCI"
55 #define EDAC_DEBUG "DEBUG"
57 #ifdef CONFIG_EDAC_DEBUG
58 extern int edac_debug_level;
60 #define edac_debug_printk(level, fmt, arg...) \
62 if (level <= edac_debug_level) \
63 edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
66 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
67 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
68 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
69 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
70 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
72 #else /* !CONFIG_EDAC_DEBUG */
74 #define debugf0( ... )
75 #define debugf1( ... )
76 #define debugf2( ... )
77 #define debugf3( ... )
78 #define debugf4( ... )
80 #endif /* !CONFIG_EDAC_DEBUG */
82 #define BIT(x) (1 << (x))
84 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
85 PCI_DEVICE_ID_ ## vend ## _ ## dev
87 #if defined(CONFIG_X86) && defined(CONFIG_PCI)
88 #define dev_name(dev) pci_name(to_pci_dev(dev))
90 #define dev_name(dev) to_platform_device(dev)->name
101 DEV_X32, /* Do these parts exist? */
102 DEV_X64 /* Do these parts exist? */
105 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
106 #define DEV_FLAG_X1 BIT(DEV_X1)
107 #define DEV_FLAG_X2 BIT(DEV_X2)
108 #define DEV_FLAG_X4 BIT(DEV_X4)
109 #define DEV_FLAG_X8 BIT(DEV_X8)
110 #define DEV_FLAG_X16 BIT(DEV_X16)
111 #define DEV_FLAG_X32 BIT(DEV_X32)
112 #define DEV_FLAG_X64 BIT(DEV_X64)
116 MEM_EMPTY = 0, /* Empty csrow */
117 MEM_RESERVED, /* Reserved csrow type */
118 MEM_UNKNOWN, /* Unknown csrow type */
119 MEM_FPM, /* Fast page mode */
120 MEM_EDO, /* Extended data out */
121 MEM_BEDO, /* Burst Extended data out */
122 MEM_SDR, /* Single data rate SDRAM */
123 MEM_RDR, /* Registered single data rate SDRAM */
124 MEM_DDR, /* Double data rate SDRAM */
125 MEM_RDDR, /* Registered Double data rate SDRAM */
126 MEM_RMBS, /* Rambus DRAM */
127 MEM_DDR2, /* DDR2 RAM */
128 MEM_FB_DDR2, /* fully buffered DDR2 */
129 MEM_RDDR2, /* Registered DDR2 RAM */
132 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
133 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
134 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
135 #define MEM_FLAG_FPM BIT(MEM_FPM)
136 #define MEM_FLAG_EDO BIT(MEM_EDO)
137 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
138 #define MEM_FLAG_SDR BIT(MEM_SDR)
139 #define MEM_FLAG_RDR BIT(MEM_RDR)
140 #define MEM_FLAG_DDR BIT(MEM_DDR)
141 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
142 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
143 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
144 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
145 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
147 /* chipset Error Detection and Correction capabilities and mode */
149 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
150 EDAC_NONE, /* Doesnt support ECC */
151 EDAC_RESERVED, /* Reserved ECC type */
152 EDAC_PARITY, /* Detects parity errors */
153 EDAC_EC, /* Error Checking - no correction */
154 EDAC_SECDED, /* Single bit error correction, Double detection */
155 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
156 EDAC_S4ECD4ED, /* Chipkill x4 devices */
157 EDAC_S8ECD8ED, /* Chipkill x8 devices */
158 EDAC_S16ECD16ED, /* Chipkill x16 devices */
161 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
162 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
163 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
164 #define EDAC_FLAG_EC BIT(EDAC_EC)
165 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
166 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
167 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
168 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
169 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
171 /* scrubbing capabilities */
173 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
174 SCRUB_NONE, /* No scrubber */
175 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
176 SCRUB_SW_SRC, /* Software scrub only errors */
177 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
178 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
179 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
180 SCRUB_HW_SRC, /* Hardware scrub only errors */
181 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
182 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
185 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
186 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC_CORR)
187 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC_CORR)
188 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
189 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
190 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC_CORR)
191 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC_CORR)
192 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
194 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
197 * There are several things to be aware of that aren't at all obvious:
200 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
202 * These are some of the many terms that are thrown about that don't always
203 * mean what people think they mean (Inconceivable!). In the interest of
204 * creating a common ground for discussion, terms and their definitions
205 * will be established.
207 * Memory devices: The individual chip on a memory stick. These devices
208 * commonly output 4 and 8 bits each. Grouping several
209 * of these in parallel provides 64 bits which is common
210 * for a memory stick.
212 * Memory Stick: A printed circuit board that agregates multiple
213 * memory devices in parallel. This is the atomic
214 * memory component that is purchaseable by Joe consumer
215 * and loaded into a memory socket.
217 * Socket: A physical connector on the motherboard that accepts
218 * a single memory stick.
220 * Channel: Set of memory devices on a memory stick that must be
221 * grouped in parallel with one or more additional
222 * channels from other memory sticks. This parallel
223 * grouping of the output from multiple channels are
224 * necessary for the smallest granularity of memory access.
225 * Some memory controllers are capable of single channel -
226 * which means that memory sticks can be loaded
227 * individually. Other memory controllers are only
228 * capable of dual channel - which means that memory
229 * sticks must be loaded as pairs (see "socket set").
231 * Chip-select row: All of the memory devices that are selected together.
232 * for a single, minimum grain of memory access.
233 * This selects all of the parallel memory devices across
234 * all of the parallel channels. Common chip-select rows
235 * for single channel are 64 bits, for dual channel 128
238 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
239 * Motherboards commonly drive two chip-select pins to
240 * a memory stick. A single-ranked stick, will occupy
241 * only one of those rows. The other will be unused.
243 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
244 * access different sets of memory devices. The two
245 * rows cannot be accessed concurrently.
247 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
248 * A double-sided stick has two chip-select rows which
249 * access different sets of memory devices. The two
250 * rows cannot be accessed concurrently. "Double-sided"
251 * is irrespective of the memory devices being mounted
252 * on both sides of the memory stick.
254 * Socket set: All of the memory sticks that are required for for
255 * a single memory access or all of the memory sticks
256 * spanned by a chip-select row. A single socket set
257 * has two chip-select rows and if double-sided sticks
258 * are used these will occupy those chip-select rows.
260 * Bank: This term is avoided because it is unclear when
261 * needing to distinguish between chip-select rows and
271 * STRUCTURE ORGANIZATION AND CHOICES
275 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
278 struct channel_info {
279 int chan_idx; /* channel index */
280 u32 ce_count; /* Correctable Errors for this CHANNEL */
281 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
282 struct csrow_info *csrow; /* the parent */
286 unsigned long first_page; /* first page number in dimm */
287 unsigned long last_page; /* last page number in dimm */
288 unsigned long page_mask; /* used for interleaving -
291 u32 nr_pages; /* number of pages in csrow */
292 u32 grain; /* granularity of reported error in bytes */
293 int csrow_idx; /* the chip-select row */
294 enum dev_type dtype; /* memory device type */
295 u32 ue_count; /* Uncorrectable Errors for this csrow */
296 u32 ce_count; /* Correctable Errors for this csrow */
297 enum mem_type mtype; /* memory csrow type */
298 enum edac_type edac_mode; /* EDAC mode for this csrow */
299 struct mem_ctl_info *mci; /* the parent */
301 struct kobject kobj; /* sysfs kobject for this csrow */
302 struct completion kobj_complete;
304 /* FIXME the number of CHANNELs might need to become dynamic */
306 struct channel_info *channels;
309 struct mem_ctl_info {
310 struct list_head link; /* for global list of mem_ctl_info structs */
311 unsigned long mtype_cap; /* memory types supported by mc */
312 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
313 unsigned long edac_cap; /* configuration capabilities - this is
314 * closely related to edac_ctl_cap. The
315 * difference is that the controller may be
316 * capable of s4ecd4ed which would be listed
317 * in edac_ctl_cap, but if channels aren't
318 * capable of s4ecd4ed then the edac_cap would
319 * not have that capability.
321 unsigned long scrub_cap; /* chipset scrub capabilities */
322 enum scrub_type scrub_mode; /* current scrub mode */
324 /* pointer to edac checking routine */
325 void (*edac_check) (struct mem_ctl_info * mci);
327 * Remaps memory pages: controller pages to physical pages.
328 * For most MC's, this will be NULL.
330 /* FIXME - why not send the phys page to begin with? */
331 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
335 struct csrow_info *csrows;
337 * FIXME - what about controllers on other busses? - IDs must be
338 * unique. dev pointer should be sufficiently unique, but
339 * BUS:SLOT.FUNC numbers may not be unique.
342 const char *mod_name;
344 const char *ctl_name;
345 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
347 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
348 u32 ce_noinfo_count; /* Correctable Errors w/o info */
349 u32 ue_count; /* Total Uncorrectable Errors for this MC */
350 u32 ce_count; /* Total Correctable Errors for this MC */
351 unsigned long start_time; /* mci load start time (in jiffies) */
353 /* this stuff is for safe removal of mc devices from global list while
354 * NMI handlers may be traversing list
357 struct completion complete;
359 /* edac sysfs device control */
360 struct kobject edac_mci_kobj;
361 struct completion kobj_complete;
366 /* write all or some bits in a byte-register*/
367 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
373 pci_read_config_byte(pdev, offset, &buf);
379 pci_write_config_byte(pdev, offset, value);
382 /* write all or some bits in a word-register*/
383 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
386 if (mask != 0xffff) {
389 pci_read_config_word(pdev, offset, &buf);
395 pci_write_config_word(pdev, offset, value);
398 /* write all or some bits in a dword-register*/
399 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
402 if (mask != 0xffff) {
405 pci_read_config_dword(pdev, offset, &buf);
411 pci_write_config_dword(pdev, offset, value);
414 #endif /* CONFIG_PCI */
416 #ifdef CONFIG_EDAC_DEBUG
417 void edac_mc_dump_channel(struct channel_info *chan);
418 void edac_mc_dump_mci(struct mem_ctl_info *mci);
419 void edac_mc_dump_csrow(struct csrow_info *csrow);
420 #endif /* CONFIG_EDAC_DEBUG */
422 extern struct mem_ctl_info * edac_mc_find(int idx);
423 extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx);
424 extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
425 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
427 extern void edac_mc_scrub_block(unsigned long page, unsigned long offset,
431 * The no info errors are used when error overflows are reported.
432 * There are a limited number of error logging registers that can
433 * be exausted. When all registers are exhausted and an additional
434 * error occurs then an error overflow register records that an
435 * error occured and the type of error, but doesn't have any
436 * further information. The ce/ue versions make for cleaner
437 * reporting logic and function interface - reduces conditional
438 * statement clutter and extra function arguments.
440 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
441 unsigned long page_frame_number, unsigned long offset_in_page,
442 unsigned long syndrome, int row, int channel,
444 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
446 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
447 unsigned long page_frame_number, unsigned long offset_in_page,
448 int row, const char *msg);
449 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
453 * This kmalloc's and initializes all the structures.
454 * Can't be used if all structures don't have the same lifetime.
456 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
459 /* Free an mc previously allocated by edac_mc_alloc() */
460 extern void edac_mc_free(struct mem_ctl_info *mci);
462 #endif /* _EDAC_MC_H_ */