2 -------------------------------------------------------------------------
3 i2c-algo-ite.c i2c driver algorithms for ITE adapters
5 Hai-Pao Fan, MontaVista Software, Inc.
6 hpfan@mvista.com or source@mvista.com
8 Copyright 2000 MontaVista Software Inc.
10 ---------------------------------------------------------------------------
11 This file was highly leveraged from i2c-algo-pcf.c, which was created
12 by Simon G. Vogl and Hans Berglund:
15 Copyright (C) 1995-1997 Simon G. Vogl
16 1998-2000 Hans Berglund
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; if not, write to the Free Software
30 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
31 /* ------------------------------------------------------------------------- */
33 /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
34 Frodo Looijaard <frodol@dds.nl> ,and also from Martin Bailey
35 <mbailey@littlefeet-inc.com> */
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/init.h>
42 #include <asm/uaccess.h>
43 #include <linux/ioport.h>
44 #include <linux/errno.h>
45 #include <linux/sched.h>
47 #include <linux/i2c.h>
48 #include <linux/i2c-algo-ite.h>
49 #include "i2c-algo-ite.h"
51 #define PM_DSR IT8172_PCI_IO_BASE + IT_PM_DSR
52 #define PM_IBSR IT8172_PCI_IO_BASE + IT_PM_DSR + 0x04
53 #define GPIO_CCR IT8172_PCI_IO_BASE + IT_GPCCR
55 /* ----- global defines ----------------------------------------------- */
56 #define DEB(x) if (i2c_debug>=1) x
57 #define DEB2(x) if (i2c_debug>=2) x
58 #define DEB3(x) if (i2c_debug>=3) x /* print several statistical values*/
59 #define DEBPROTO(x) if (i2c_debug>=9) x;
60 /* debug the protocol by showing transferred bits */
61 #define DEF_TIMEOUT 16
64 /* ----- global variables --------------------------------------------- */
68 static int i2c_debug=1;
69 static int iic_test=0; /* see if the line-setting functions work */
71 /* --- setting states on the bus with the right timing: --------------- */
73 #define get_clock(adap) adap->getclock(adap->data)
74 #define iic_outw(adap, reg, val) adap->setiic(adap->data, reg, val)
75 #define iic_inw(adap, reg) adap->getiic(adap->data, reg)
78 /* --- other auxiliary functions -------------------------------------- */
80 static void iic_start(struct i2c_algo_iic_data *adap)
82 iic_outw(adap,ITE_I2CHCR,ITE_CMD);
85 static void iic_stop(struct i2c_algo_iic_data *adap)
87 iic_outw(adap,ITE_I2CHCR,0);
88 iic_outw(adap,ITE_I2CHSR,ITE_I2CHSR_TDI);
91 static void iic_reset(struct i2c_algo_iic_data *adap)
93 iic_outw(adap, PM_IBSR, iic_inw(adap, PM_IBSR) | 0x80);
97 static int wait_for_bb(struct i2c_algo_iic_data *adap)
99 int timeout = DEF_TIMEOUT;
102 status = iic_inw(adap, ITE_I2CHSR);
104 while (timeout-- && (status & ITE_I2CHSR_HB)) {
105 udelay(1000); /* How much is this? */
106 status = iic_inw(adap, ITE_I2CHSR);
110 printk(KERN_ERR "Timeout, host is busy\n");
117 * Puts this process to sleep for a period equal to timeout
119 static inline void iic_sleep(unsigned long timeout)
121 schedule_timeout( timeout * HZ);
124 /* After we issue a transaction on the IIC bus, this function
125 * is called. It puts this process to sleep until we get an interrupt from
126 * from the controller telling us that the transaction we requested in complete.
128 static int wait_for_pin(struct i2c_algo_iic_data *adap, short *status) {
130 int timeout = DEF_TIMEOUT;
132 timeout = wait_for_bb(adap);
134 DEB2(printk("Timeout waiting for host not busy\n");)
137 timeout = DEF_TIMEOUT;
139 *status = iic_inw(adap, ITE_I2CHSR);
141 while (timeout-- && !(*status & ITE_I2CHSR_TDI)) {
143 *status = iic_inw(adap, ITE_I2CHSR);
152 static int wait_for_fe(struct i2c_algo_iic_data *adap, short *status)
154 int timeout = DEF_TIMEOUT;
156 *status = iic_inw(adap, ITE_I2CFSR);
158 while (timeout-- && (*status & ITE_I2CFSR_FE)) {
160 iic_inw(adap, ITE_I2CFSR);
169 static int iic_init (struct i2c_algo_iic_data *adap)
173 /* Clear bit 7 to set I2C to normal operation mode */
174 i=iic_inw(adap, PM_DSR)& 0xff7f;
175 iic_outw(adap, PM_DSR, i);
177 /* set IT_GPCCR port C bit 2&3 as function 2 */
178 i = iic_inw(adap, GPIO_CCR) & 0xfc0f;
179 iic_outw(adap,GPIO_CCR,i);
181 /* Clear slave address/sub-address */
182 iic_outw(adap,ITE_I2CSAR, 0);
183 iic_outw(adap,ITE_I2CSSAR, 0);
185 /* Set clock counter register */
186 iic_outw(adap,ITE_I2CCKCNT, get_clock(adap));
188 /* Set START/reSTART/STOP time registers */
189 iic_outw(adap,ITE_I2CSHDR, 0x0a);
190 iic_outw(adap,ITE_I2CRSUR, 0x0a);
191 iic_outw(adap,ITE_I2CPSUR, 0x0a);
193 /* Enable interrupts on completing the current transaction */
194 iic_outw(adap,ITE_I2CHCR, ITE_I2CHCR_IE | ITE_I2CHCR_HCE);
196 /* Clear transfer count */
197 iic_outw(adap,ITE_I2CFBCR, 0x0);
199 DEB2(printk("iic_init: Initialized IIC on ITE 0x%x\n",
200 iic_inw(adap, ITE_I2CHSR)));
206 * Sanity check for the adapter hardware - check the reaction of
207 * the bus lines only if it seems to be idle.
209 static int test_bus(struct i2c_algo_iic_data *adap, char *name) {
213 if (adap->getscl==NULL) {
214 printk("test_bus: Warning: Adapter can't read from clock line - skipping test.\n");
218 printk("test_bus: Adapter: %s scl: %d sda: %d -- testing...\n",
219 name,getscl(adap),getsda(adap));
221 printk("test_bus: %s seems to be busy.\n",adap->name);
225 printk("test_bus:1 scl: %d sda: %d \n",getscl(adap),
227 if ( 0 != getsda(adap) ) {
228 printk("test_bus: %s SDA stuck high!\n",name);
232 if ( 0 == getscl(adap) ) {
233 printk("test_bus: %s SCL unexpected low while pulling SDA low!\n",
238 printk("test_bus:2 scl: %d sda: %d \n",getscl(adap),
240 if ( 0 == getsda(adap) ) {
241 printk("test_bus: %s SDA stuck low!\n",name);
245 if ( 0 == getscl(adap) ) {
246 printk("test_bus: %s SCL unexpected low while SDA high!\n",
251 printk("test_bus:3 scl: %d sda: %d \n",getscl(adap),
253 if ( 0 != getscl(adap) ) {
258 if ( 0 == getsda(adap) ) {
259 printk("test_bus: %s SDA unexpected low while pulling SCL low!\n",
264 printk("test_bus:4 scl: %d sda: %d \n",getscl(adap),
266 if ( 0 == getscl(adap) ) {
267 printk("test_bus: %s SCL stuck low!\n",name);
271 if ( 0 == getsda(adap) ) {
272 printk("test_bus: %s SDA unexpected low while SCL high!\n",
276 printk("test_bus: %s passed test.\n",name);
286 /* ----- Utility functions
290 /* Verify the device we want to talk to on the IIC bus really exists. */
291 static inline int try_address(struct i2c_algo_iic_data *adap,
292 unsigned int addr, int retries)
297 for (i=0;i<retries;i++) {
298 iic_outw(adap, ITE_I2CSAR, addr);
300 if (wait_for_pin(adap, &status) == 0) {
301 if ((status & ITE_I2CHSR_DNE) == 0) {
303 iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
305 break; /* success! */
309 udelay(adap->udelay);
311 DEB2(if (i) printk("try_address: needed %d retries for 0x%x\n",i,
317 static int iic_sendbytes(struct i2c_adapter *i2c_adap,const char *buf,
320 struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
321 int wrcount=0, timeout;
323 int loops, remainder, i, j;
329 iic_outw(adap, ITE_I2CSSAR, (unsigned short)buf[wrcount++]);
334 loops = count / 32; /* 32-byte FIFO */
335 remainder = count % 32;
338 for(i=0; i<loops; i++) {
340 iic_outw(adap, ITE_I2CFBCR, 32);
341 for(j=0; j<32/2; j++) {
342 tmp.byte[1] = buf[wrcount++];
343 tmp.byte[0] = buf[wrcount++];
344 iic_outw(adap, ITE_I2CFDR, tmp.word);
347 /* status FIFO overrun */
348 iic_inw(adap, ITE_I2CFSR);
349 iic_inw(adap, ITE_I2CFBCR);
351 iic_outw(adap, ITE_I2CHCR, ITE_WRITE); /* Issue WRITE command */
353 /* Wait for transmission to complete */
354 timeout = wait_for_pin(adap, &status);
357 printk("iic_sendbytes: %s write timeout.\n", i2c_adap->name);
358 return -EREMOTEIO; /* got a better one ?? */
360 if (status & ITE_I2CHSR_DB) {
362 printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name);
363 return -EREMOTEIO; /* got a better one ?? */
368 iic_outw(adap, ITE_I2CFBCR, remainder);
369 for(i=0; i<remainder/2; i++) {
370 tmp.byte[1] = buf[wrcount++];
371 tmp.byte[0] = buf[wrcount++];
372 iic_outw(adap, ITE_I2CFDR, tmp.word);
375 /* status FIFO overrun */
376 iic_inw(adap, ITE_I2CFSR);
377 iic_inw(adap, ITE_I2CFBCR);
379 iic_outw(adap, ITE_I2CHCR, ITE_WRITE); /* Issue WRITE command */
381 timeout = wait_for_pin(adap, &status);
384 printk("iic_sendbytes: %s write timeout.\n", i2c_adap->name);
385 return -EREMOTEIO; /* got a better one ?? */
388 if (status & ITE_I2CHSR_DB) {
390 printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name);
391 return -EREMOTEIO; /* got a better one ?? */
400 static int iic_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count,
403 int rdcount=0, i, timeout;
405 struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
406 int loops, remainder, j;
412 loops = count / 32; /* 32-byte FIFO */
413 remainder = count % 32;
416 for(i=0; i<loops; i++) {
417 iic_outw(adap, ITE_I2CFBCR, 32);
419 iic_outw(adap, ITE_I2CHCR, ITE_SREAD);
421 iic_outw(adap, ITE_I2CHCR, ITE_READ); /* Issue READ command */
423 timeout = wait_for_pin(adap, &status);
426 printk("iic_readbytes: %s read timeout.\n", i2c_adap->name);
430 if (status & ITE_I2CHSR_DB) {
432 printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name);
437 timeout = wait_for_fe(adap, &status);
440 printk("iic_readbytes: %s FIFO is empty\n", i2c_adap->name);
444 for(j=0; j<32/2; j++) {
445 tmp.word = iic_inw(adap, ITE_I2CFDR);
446 buf[rdcount++] = tmp.byte[1];
447 buf[rdcount++] = tmp.byte[0];
450 /* status FIFO underrun */
451 iic_inw(adap, ITE_I2CFSR);
458 remainder=(remainder+1)/2 * 2;
459 iic_outw(adap, ITE_I2CFBCR, remainder);
461 iic_outw(adap, ITE_I2CHCR, ITE_SREAD);
463 iic_outw(adap, ITE_I2CHCR, ITE_READ); /* Issue READ command */
465 timeout = wait_for_pin(adap, &status);
468 printk("iic_readbytes: %s read timeout.\n", i2c_adap->name);
472 if (status & ITE_I2CHSR_DB) {
474 printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name);
478 timeout = wait_for_fe(adap, &status);
481 printk("iic_readbytes: %s FIFO is empty\n", i2c_adap->name);
485 for(i=0; i<(remainder+1)/2; i++) {
486 tmp.word = iic_inw(adap, ITE_I2CFDR);
487 buf[rdcount++] = tmp.byte[1];
488 buf[rdcount++] = tmp.byte[0];
491 /* status FIFO underrun */
492 iic_inw(adap, ITE_I2CFSR);
501 /* This function implements combined transactions. Combined
502 * transactions consist of combinations of reading and writing blocks of data.
503 * Each transfer (i.e. a read or a write) is separated by a repeated start
507 static int iic_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num)
510 struct i2c_msg *pmsg;
513 DEB2(printk("Beginning combined transaction\n"));
515 for(i=0; i<(num-1); i++) {
517 if(pmsg->flags & I2C_M_RD) {
518 DEB2(printk(" This one is a read\n"));
519 ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER);
521 else if(!(pmsg->flags & I2C_M_RD)) {
522 DEB2(printk("This one is a write\n"));
523 ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER);
526 /* Last read or write segment needs to be terminated with a stop */
529 if(pmsg->flags & I2C_M_RD) {
530 DEB2(printk("Doing the last read\n"));
531 ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
533 else if(!(pmsg->flags & I2C_M_RD)) {
534 DEB2(printk("Doing the last write\n"));
535 ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
543 /* Whenever we initiate a transaction, the first byte clocked
544 * onto the bus after the start condition is the address (7 bit) of the
545 * device we want to talk to. This function manipulates the address specified
546 * so that it makes sense to the hardware when written to the IIC peripheral.
548 * Note: 10 bit addresses are not supported in this driver, although they are
549 * supported by the hardware. This functionality needs to be implemented.
551 static inline int iic_doAddress(struct i2c_algo_iic_data *adap,
552 struct i2c_msg *msg, int retries)
554 unsigned short flags = msg->flags;
558 /* Ten bit addresses not supported right now */
559 if ( (flags & I2C_M_TEN) ) {
561 addr = 0xf0 | (( msg->addr >> 7) & 0x03);
562 DEB2(printk("addr0: %d\n",addr));
563 ret = try_address(adap, addr, retries);
565 printk("iic_doAddress: died at extended address code.\n");
568 iic_outw(adap,msg->addr & 0x7f);
570 printk("iic_doAddress: died at 2nd address code.\n");
573 if ( flags & I2C_M_RD ) {
576 ret = try_address(adap, addr, retries);
578 printk("iic_doAddress: died at extended address code.\n");
585 addr = ( msg->addr << 1 );
588 if (flags & I2C_M_RD )
590 if (flags & I2C_M_REV_DIR_ADDR )
594 if (iic_inw(adap, ITE_I2CSAR) != addr) {
595 iic_outw(adap, ITE_I2CSAR, addr);
596 ret = try_address(adap, addr, retries);
598 printk("iic_doAddress: died at address code.\n");
609 /* Description: Prepares the controller for a transaction (clearing status
610 * registers, data buffers, etc), and then calls either iic_readbytes or
611 * iic_sendbytes to do the actual transaction.
613 * still to be done: Before we issue a transaction, we should
614 * verify that the bus is not busy or in some unknown state.
616 static int iic_xfer(struct i2c_adapter *i2c_adap,
617 struct i2c_msg msgs[],
620 struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
621 struct i2c_msg *pmsg;
628 DEB2(printk("iic_xfer: read/write length is 0\n");)
631 if(!(pmsg->flags & I2C_M_RD) && (!(pmsg->len)%2) ) {
632 DEB2(printk("iic_xfer: write buffer length is not odd\n");)
636 /* Wait for any pending transfers to complete */
637 timeout = wait_for_bb(adap);
639 DEB2(printk("iic_xfer: Timeout waiting for host not busy\n");)
644 iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
647 ret = iic_doAddress(adap, pmsg, i2c_adap->retries);
652 /* Combined transaction (read and write) */
654 DEB2(printk("iic_xfer: Call combined transaction\n"));
655 ret = iic_combined_transaction(i2c_adap, msgs, num);
659 DEB3(printk("iic_xfer: Msg %d, addr=0x%x, flags=0x%x, len=%d\n",
660 i, msgs[i].addr, msgs[i].flags, msgs[i].len);)
662 if(pmsg->flags & I2C_M_RD) /* Read */
663 ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, 0);
666 ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len);
669 if (ret != pmsg->len)
670 DEB3(printk("iic_xfer: error or fail on read/write %d bytes.\n",ret));
672 DEB3(printk("iic_xfer: read/write %d bytes.\n",ret));
678 /* Implements device specific ioctls. Higher level ioctls can
679 * be found in i2c-core.c and are typical of any i2c controller (specifying
680 * slave address, timeouts, etc). These ioctls take advantage of any hardware
681 * features built into the controller for which this algorithm-adapter set
682 * was written. These ioctls allow you to take control of the data and clock
683 * lines and set the either high or low,
684 * similar to a GPIO pin.
686 static int algo_control(struct i2c_adapter *adapter,
687 unsigned int cmd, unsigned long arg)
690 struct i2c_algo_iic_data *adap = adapter->algo_data;
691 struct i2c_iic_msg s_msg;
695 if (cmd == I2C_SREAD) {
696 if(copy_from_user(&s_msg, (struct i2c_iic_msg *)arg,
697 sizeof(struct i2c_iic_msg)))
699 buf = kmalloc(s_msg.len, GFP_KERNEL);
704 iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
707 iic_outw(adap, ITE_I2CSAR,s_msg.addr<<1);
708 iic_outw(adap, ITE_I2CSSAR,s_msg.waddr & 0xff);
710 ret = iic_readbytes(adapter, buf, s_msg.len, 1);
712 if(copy_to_user( s_msg.buf, buf, s_msg.len) )
721 static u32 iic_func(struct i2c_adapter *adap)
723 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
724 I2C_FUNC_PROTOCOL_MANGLING;
727 /* -----exported algorithm data: ------------------------------------- */
729 static struct i2c_algorithm iic_algo = {
732 iic_xfer, /* master_xfer */
733 NULL, /* smbus_xfer */
734 NULL, /* slave_xmit */
735 NULL, /* slave_recv */
736 algo_control, /* ioctl */
737 iic_func, /* functionality */
742 * registering functions to load algorithms at runtime
744 int i2c_iic_add_bus(struct i2c_adapter *adap)
746 struct i2c_algo_iic_data *iic_adap = adap->algo_data;
749 int ret = test_bus(iic_adap, adap->name);
754 DEB2(printk("i2c-algo-ite: hw routines for %s registered.\n",
757 /* register new adapter to i2c module... */
759 adap->id |= iic_algo.id;
760 adap->algo = &iic_algo;
762 adap->timeout = 100; /* default values, should */
763 adap->retries = 3; /* be replaced by defines */
766 i2c_add_adapter(adap);
773 int i2c_iic_del_bus(struct i2c_adapter *adap)
776 if ((res = i2c_del_adapter(adap)) < 0)
778 DEB2(printk("i2c-algo-ite: adapter unregistered: %s\n",adap->name));
784 int __init i2c_algo_iic_init (void)
786 printk(KERN_INFO "ITE iic (i2c) algorithm module\n");
791 void i2c_algo_iic_exit(void)
797 EXPORT_SYMBOL(i2c_iic_add_bus);
798 EXPORT_SYMBOL(i2c_iic_del_bus);
800 /* The MODULE_* macros resolve to nothing if MODULES is not defined
801 * when this file is compiled.
803 MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
804 MODULE_DESCRIPTION("ITE iic algorithm");
805 MODULE_LICENSE("GPL");
807 MODULE_PARM(iic_test, "i");
808 MODULE_PARM(i2c_debug,"i");
810 MODULE_PARM_DESC(iic_test, "Test if the I2C bus is available");
811 MODULE_PARM_DESC(i2c_debug,
812 "debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");
815 /* This function resolves to init_module (the function invoked when a module
816 * is loaded via insmod) when this file is compiled with MODULES defined.
817 * Otherwise (i.e. if you want this driver statically linked to the kernel),
818 * a pointer to this function is stored in a table and called
819 * during the initialization of the kernel (in do_basic_setup in /init/main.c)
821 * All this functionality is complements of the macros defined in linux/init.h
823 module_init(i2c_algo_iic_init);
826 /* If MODULES is defined when this file is compiled, then this function will
827 * resolved to cleanup_module.
829 module_exit(i2c_algo_iic_exit);