2 i801.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 SUPPORTED DEVICES PCI ID
29 82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30 82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
32 This driver supports several versions of Intel's I/O Controller Hubs (ICH).
33 For SMBus support, they are similar to the PIIX4 and are part
34 of Intel's '810' and other chipsets.
35 See the doc/busses/i2c-i801 file for details.
36 I2C Block Read and Process Call are not supported.
39 /* Note: we assume there can only be one I801, with one SMBus interface */
41 #include <linux/config.h>
42 #include <linux/module.h>
43 #include <linux/pci.h>
44 #include <linux/kernel.h>
45 #include <linux/stddef.h>
46 #include <linux/sched.h>
47 #include <linux/ioport.h>
48 #include <linux/init.h>
49 #include <linux/i2c.h>
52 #ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
56 /* I801 SMBus address offsets */
57 #define SMBHSTSTS (0 + i801_smba)
58 #define SMBHSTCNT (2 + i801_smba)
59 #define SMBHSTCMD (3 + i801_smba)
60 #define SMBHSTADD (4 + i801_smba)
61 #define SMBHSTDAT0 (5 + i801_smba)
62 #define SMBHSTDAT1 (6 + i801_smba)
63 #define SMBBLKDAT (7 + i801_smba)
64 #define SMBPEC (8 + i801_smba) /* ICH4 only */
65 #define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
66 #define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
68 /* PCI Address Constants */
70 #define SMBHSTCFG 0x040
73 /* Host configuration bits for SMBHSTCFG */
74 #define SMBHSTCFG_HST_EN 1
75 #define SMBHSTCFG_SMB_SMI_EN 2
76 #define SMBHSTCFG_I2C_EN 4
79 #define MAX_TIMEOUT 100
80 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
82 /* I801 command constants */
83 #define I801_QUICK 0x00
84 #define I801_BYTE 0x04
85 #define I801_BYTE_DATA 0x08
86 #define I801_WORD_DATA 0x0C
87 #define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
88 #define I801_BLOCK_DATA 0x14
89 #define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
90 #define I801_BLOCK_LAST 0x34
91 #define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
92 #define I801_START 0x40
93 #define I801_PEC_EN 0x80 /* ICH4 only */
95 /* insmod parameters */
97 /* If force_addr is set to anything different from 0, we forcibly enable
98 the I801 at the given address. VERY DANGEROUS! */
99 static int force_addr = 0;
100 MODULE_PARM(force_addr, "i");
101 MODULE_PARM_DESC(force_addr,
102 "Forcibly enable the I801 at the given address. "
103 "EXTREMELY DANGEROUS!");
105 static int i801_transaction(void);
106 static int i801_block_transaction(union i2c_smbus_data *data,
107 char read_write, int command);
109 static unsigned short i801_smba;
110 static struct pci_dev *I801_dev;
113 static int i801_setup(struct pci_dev *dev)
115 int error_return = 0;
118 /* Note: we keep on searching until we have found 'function 3' */
119 if(PCI_FUNC(dev->devfn) != 3)
123 if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) ||
124 (dev->device == PCI_DEVICE_ID_INTEL_82801EB_3))
129 /* Determine the address of the SMBus areas */
131 i801_smba = force_addr & 0xfff0;
133 pci_read_config_word(I801_dev, SMBBA, &i801_smba);
136 dev_err(&dev->dev, "SMB base address uninitialized"
137 "- upgrade BIOS or use force_addr=0xaddr\n");
142 if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
143 dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
145 error_return = -EBUSY;
149 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
150 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
151 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
153 /* If force_addr is set, we program the new address here. Just to make
154 sure, we disable the device first. */
156 pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
157 pci_write_config_word(I801_dev, SMBBA, i801_smba);
158 pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 0x01);
159 dev_warn(&dev->dev, "WARNING: I801 SMBus interface set to "
160 "new address %04x!\n", i801_smba);
161 } else if ((temp & 1) == 0) {
162 pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 1);
163 dev_warn(&dev->dev, "enabling SMBus device\n");
167 dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
169 dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");
171 pci_read_config_byte(I801_dev, SMBREV, &temp);
172 dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
173 dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);
179 static int i801_transaction(void)
185 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
186 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
187 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
190 /* Make sure the SMBus host is ready to start transmitting */
191 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
192 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
193 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting... \n",
195 outb_p(temp, SMBHSTSTS);
196 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
197 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
200 dev_dbg(&I801_dev->dev, "Successfull!\n");
204 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
206 /* We will always wait for a fraction of a second! */
209 temp = inb_p(SMBHSTSTS);
210 } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
212 /* If the SMBus is still busy, we give up */
213 if (timeout >= MAX_TIMEOUT) {
214 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
220 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
225 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
226 "until next hard reset. (sorry!)\n");
227 /* Clock stops and slave is stuck in mid-transmission */
232 dev_dbg(&I801_dev->dev, "Error: no response!\n");
235 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
236 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
238 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
239 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction"
242 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
243 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
244 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
249 /* All-inclusive block transaction function */
250 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
258 unsigned char hostc, errmask;
260 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
261 if (read_write == I2C_SMBUS_WRITE) {
262 /* set I2C_EN bit in configuration register */
263 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
264 pci_write_config_byte(I801_dev, SMBHSTCFG,
265 hostc | SMBHSTCFG_I2C_EN);
267 dev_err(&I801_dev->dev,
268 "I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
273 if (read_write == I2C_SMBUS_WRITE) {
274 len = data->block[0];
279 outb_p(len, SMBHSTDAT0);
280 outb_p(data->block[1], SMBBLKDAT);
282 len = 32; /* max for reads */
285 if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
286 /* set 32 byte buffer */
289 for (i = 1; i <= len; i++) {
290 if (i == len && read_write == I2C_SMBUS_READ)
291 smbcmd = I801_BLOCK_LAST;
293 smbcmd = I801_BLOCK_DATA;
294 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
296 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
297 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
298 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
299 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
301 /* Make sure the SMBus host is ready to start transmitting */
302 temp = inb_p(SMBHSTSTS);
304 /* Erronenous conditions before transaction:
305 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
308 /* Erronenous conditions during transaction:
309 * Failed, Bus_Err, Dev_Err, Intr */
312 if (temp & errmask) {
313 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
314 "Resetting... \n", temp);
315 outb_p(temp, SMBHSTSTS);
316 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
317 dev_err(&I801_dev->dev,
318 "Reset failed! (%02x)\n", temp);
323 /* if die in middle of block transaction, fail */
330 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
332 /* We will always wait for a fraction of a second! */
335 temp = inb_p(SMBHSTSTS);
338 while ((!(temp & 0x80))
339 && (timeout++ < MAX_TIMEOUT));
341 /* If the SMBus is still busy, we give up */
342 if (timeout >= MAX_TIMEOUT) {
344 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
349 dev_dbg(&I801_dev->dev,
350 "Error: Failed bus transaction\n");
351 } else if (temp & 0x08) {
353 dev_err(&I801_dev->dev, "Bus collision!\n");
354 } else if (temp & 0x04) {
356 dev_dbg(&I801_dev->dev, "Error: no response!\n");
359 if (i == 1 && read_write == I2C_SMBUS_READ) {
360 len = inb_p(SMBHSTDAT0);
365 data->block[0] = len;
368 /* Retrieve/store value in SMBBLKDAT */
369 if (read_write == I2C_SMBUS_READ)
370 data->block[i] = inb_p(SMBBLKDAT);
371 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
372 outb_p(data->block[i+1], SMBBLKDAT);
373 if ((temp & 0x9e) != 0x00)
374 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
376 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
377 dev_dbg(&I801_dev->dev,
378 "Bad status (%02x) at end of transaction\n",
381 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
382 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
383 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
384 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
391 if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
392 /* wait for INTR bit as advised by Intel */
395 temp = inb_p(SMBHSTSTS);
397 } while ((!(temp & 0x02))
398 && (timeout++ < MAX_TIMEOUT));
400 if (timeout >= MAX_TIMEOUT) {
401 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
403 outb_p(temp, SMBHSTSTS);
408 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
409 /* restore saved configuration register value */
410 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
415 /* Return -1 on error. */
416 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
417 unsigned short flags, char read_write, u8 command,
418 int size, union i2c_smbus_data * data)
426 hwpec = (flags & I2C_CLIENT_PEC) != 0;
430 case I2C_SMBUS_QUICK:
431 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
436 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
438 if (read_write == I2C_SMBUS_WRITE)
439 outb_p(command, SMBHSTCMD);
442 case I2C_SMBUS_BYTE_DATA:
443 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
445 outb_p(command, SMBHSTCMD);
446 if (read_write == I2C_SMBUS_WRITE)
447 outb_p(data->byte, SMBHSTDAT0);
448 xact = I801_BYTE_DATA;
450 case I2C_SMBUS_WORD_DATA:
451 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
453 outb_p(command, SMBHSTCMD);
454 if (read_write == I2C_SMBUS_WRITE) {
455 outb_p(data->word & 0xff, SMBHSTDAT0);
456 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
458 xact = I801_WORD_DATA;
460 case I2C_SMBUS_BLOCK_DATA:
461 case I2C_SMBUS_I2C_BLOCK_DATA:
463 case I2C_SMBUS_BLOCK_DATA_PEC:
464 if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
465 size = I2C_SMBUS_BLOCK_DATA_PEC;
467 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
469 outb_p(command, SMBHSTCMD);
472 case I2C_SMBUS_PROC_CALL:
474 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
479 if(isich4 && hwpec) {
480 if(size != I2C_SMBUS_QUICK &&
481 size != I2C_SMBUS_I2C_BLOCK_DATA)
482 outb_p(1, SMBAUXCTL); /* enable HW PEC */
486 ret = i801_block_transaction(data, read_write, size);
488 outb_p(xact | ENABLE_INT9, SMBHSTCNT);
489 ret = i801_transaction();
493 if(isich4 && hwpec) {
494 if(size != I2C_SMBUS_QUICK &&
495 size != I2C_SMBUS_I2C_BLOCK_DATA)
496 outb_p(0, SMBAUXCTL);
504 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
507 switch (xact & 0x7f) {
508 case I801_BYTE: /* Result put in SMBHSTDAT0 */
510 data->byte = inb_p(SMBHSTDAT0);
513 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
520 static u32 i801_func(struct i2c_adapter *adapter)
522 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
523 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
524 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
526 | (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC |
527 I2C_FUNC_SMBUS_HWPEC_CALC
533 static struct i2c_algorithm smbus_algorithm = {
534 .name = "Non-I2C SMBus adapter",
535 .id = I2C_ALGO_SMBUS,
536 .smbus_xfer = i801_access,
537 .functionality = i801_func,
540 static struct i2c_adapter i801_adapter = {
541 .owner = THIS_MODULE,
542 .class = I2C_ADAP_CLASS_SMBUS,
543 .algo = &smbus_algorithm,
547 static struct pci_device_id i801_ids[] = {
549 .vendor = PCI_VENDOR_ID_INTEL,
550 .device = PCI_DEVICE_ID_INTEL_82801AA_3,
551 .subvendor = PCI_ANY_ID,
552 .subdevice = PCI_ANY_ID,
555 .vendor = PCI_VENDOR_ID_INTEL,
556 .device = PCI_DEVICE_ID_INTEL_82801AB_3,
557 .subvendor = PCI_ANY_ID,
558 .subdevice = PCI_ANY_ID,
561 .vendor = PCI_VENDOR_ID_INTEL,
562 .device = PCI_DEVICE_ID_INTEL_82801BA_2,
563 .subvendor = PCI_ANY_ID,
564 .subdevice = PCI_ANY_ID,
567 .vendor = PCI_VENDOR_ID_INTEL,
568 .device = PCI_DEVICE_ID_INTEL_82801CA_3,
569 .subvendor = PCI_ANY_ID,
570 .subdevice = PCI_ANY_ID,
573 .vendor = PCI_VENDOR_ID_INTEL,
574 .device = PCI_DEVICE_ID_INTEL_82801DB_3,
575 .subvendor = PCI_ANY_ID,
576 .subdevice = PCI_ANY_ID,
579 .vendor = PCI_VENDOR_ID_INTEL,
580 .device = PCI_DEVICE_ID_INTEL_82801EB_3,
581 .subvendor = PCI_ANY_ID,
582 .subdevice = PCI_ANY_ID,
587 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
590 if (i801_setup(dev)) {
592 "I801 not detected, module not inserted.\n");
596 /* set up the driverfs linkage to our parent device */
597 i801_adapter.dev.parent = &dev->dev;
599 snprintf(i801_adapter.name, I2C_NAME_SIZE,
600 "SMBus I801 adapter at %04x", i801_smba);
601 return i2c_add_adapter(&i801_adapter);
604 static void __devexit i801_remove(struct pci_dev *dev)
606 i2c_del_adapter(&i801_adapter);
607 release_region(i801_smba, (isich4 ? 16 : 8));
610 static struct pci_driver i801_driver = {
611 .name = "i801 smbus",
612 .id_table = i801_ids,
614 .remove = __devexit_p(i801_remove),
617 static int __init i2c_i801_init(void)
619 return pci_module_init(&i801_driver);
622 static void __exit i2c_i801_exit(void)
624 pci_unregister_driver(&i801_driver);
627 MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
628 "Philip Edelbrock <phil@netroedge.com>, "
629 "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
630 MODULE_DESCRIPTION("I801 SMBus driver");
631 MODULE_LICENSE("GPL");
633 module_init(i2c_i801_init);
634 module_exit(i2c_i801_exit);