2 * linux/drivers/ide/arm/icside.c
4 * Copyright (c) 1996-2003 Russell King.
7 #include <linux/config.h>
8 #include <linux/string.h>
9 #include <linux/module.h>
10 #include <linux/ioport.h>
11 #include <linux/slab.h>
12 #include <linux/blkdev.h>
13 #include <linux/errno.h>
14 #include <linux/hdreg.h>
15 #include <linux/ide.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/device.h>
18 #include <linux/init.h>
21 #include <asm/ecard.h>
24 #define ICS_IDENT_OFFSET 0x2280
26 #define ICS_ARCIN_V5_INTRSTAT 0x000
27 #define ICS_ARCIN_V5_INTROFFSET 0x001
28 #define ICS_ARCIN_V5_IDEOFFSET 0xa00
29 #define ICS_ARCIN_V5_IDEALTOFFSET 0xae0
30 #define ICS_ARCIN_V5_IDESTEPPING 4
32 #define ICS_ARCIN_V6_IDEOFFSET_1 0x800
33 #define ICS_ARCIN_V6_INTROFFSET_1 0x880
34 #define ICS_ARCIN_V6_INTRSTAT_1 0x8a4
35 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x8e0
36 #define ICS_ARCIN_V6_IDEOFFSET_2 0xc00
37 #define ICS_ARCIN_V6_INTROFFSET_2 0xc80
38 #define ICS_ARCIN_V6_INTRSTAT_2 0xca4
39 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0xce0
40 #define ICS_ARCIN_V6_IDESTEPPING 4
43 unsigned int dataoffset;
44 unsigned int ctrloffset;
45 unsigned int stepping;
48 static struct cardinfo icside_cardinfo_v5 = {
49 ICS_ARCIN_V5_IDEOFFSET,
50 ICS_ARCIN_V5_IDEALTOFFSET,
51 ICS_ARCIN_V5_IDESTEPPING
54 static struct cardinfo icside_cardinfo_v6_1 = {
55 ICS_ARCIN_V6_IDEOFFSET_1,
56 ICS_ARCIN_V6_IDEALTOFFSET_1,
57 ICS_ARCIN_V6_IDESTEPPING
60 static struct cardinfo icside_cardinfo_v6_2 = {
61 ICS_ARCIN_V6_IDEOFFSET_2,
62 ICS_ARCIN_V6_IDEALTOFFSET_2,
63 ICS_ARCIN_V6_IDESTEPPING
69 unsigned long irq_port;
70 unsigned long slot_port;
72 /* parent device... until the IDE core gets one of its own */
77 #define ICS_TYPE_A3IN 0
78 #define ICS_TYPE_A3USER 1
80 #define ICS_TYPE_V5 15
81 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
83 /* ---------------- Version 5 PCB Support Functions --------------------- */
84 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
85 * Purpose : enable interrupts from card
87 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
89 struct icside_state *state = ec->irq_data;
90 unsigned int base = state->irq_port;
92 outb(0, base + ICS_ARCIN_V5_INTROFFSET);
95 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
96 * Purpose : disable interrupts from card
98 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
100 struct icside_state *state = ec->irq_data;
101 unsigned int base = state->irq_port;
103 inb(base + ICS_ARCIN_V5_INTROFFSET);
106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
107 .irqenable = icside_irqenable_arcin_v5,
108 .irqdisable = icside_irqdisable_arcin_v5,
112 /* ---------------- Version 6 PCB Support Functions --------------------- */
113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
114 * Purpose : enable interrupts from card
116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
118 struct icside_state *state = ec->irq_data;
119 unsigned int base = state->irq_port;
123 switch (state->channel) {
125 outb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
126 inb(base + ICS_ARCIN_V6_INTROFFSET_2);
129 outb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
130 inb(base + ICS_ARCIN_V6_INTROFFSET_1);
135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
136 * Purpose : disable interrupts from card
138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
140 struct icside_state *state = ec->irq_data;
144 inb (state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
145 inb (state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
149 * Purpose : detect an active interrupt from card
151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
153 struct icside_state *state = ec->irq_data;
155 return inb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
156 inb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
160 .irqenable = icside_irqenable_arcin_v6,
161 .irqdisable = icside_irqdisable_arcin_v6,
162 .irqpending = icside_irqpending_arcin_v6,
166 * Handle routing of interrupts. This is called before
167 * we write the command to the drive.
169 static void icside_maskproc(ide_drive_t *drive, int mask)
171 ide_hwif_t *hwif = HWIF(drive);
172 struct icside_state *state = hwif->hwif_data;
175 local_irq_save(flags);
177 state->channel = hwif->channel;
179 if (state->enabled && !mask) {
180 switch (hwif->channel) {
182 outb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
183 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
186 outb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
187 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
191 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
192 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
195 local_irq_restore(flags);
198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
202 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
203 * There is only one DMA controller per card, which means that only
204 * one drive can be accessed at one time. NOTE! We do not enforce that
205 * here, but we rely on the main IDE driver spotting that both
206 * interfaces use the same IRQ, which should guarantee this.
208 #define NR_ENTRIES 256
209 #define TABLE_SIZE (NR_ENTRIES * 8)
211 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
213 ide_hwif_t *hwif = drive->hwif;
214 struct icside_state *state = hwif->hwif_data;
215 struct scatterlist *sg = hwif->sg_table;
218 BUG_ON(hwif->sg_dma_active);
220 if (rq->flags & REQ_DRIVE_TASKFILE) {
221 ide_task_t *args = rq->special;
223 if (args->command_type == IDE_DRIVE_TASK_RAW_WRITE)
224 hwif->sg_dma_direction = DMA_TO_DEVICE;
226 hwif->sg_dma_direction = DMA_FROM_DEVICE;
228 memset(sg, 0, sizeof(*sg));
229 sg->page = virt_to_page(rq->buffer);
230 sg->offset = offset_in_page(rq->buffer);
231 sg->length = rq->nr_sectors * SECTOR_SIZE;
234 nents = blk_rq_map_sg(drive->queue, rq, sg);
236 if (rq_data_dir(rq) == READ)
237 hwif->sg_dma_direction = DMA_FROM_DEVICE;
239 hwif->sg_dma_direction = DMA_TO_DEVICE;
242 nents = dma_map_sg(state->dev, sg, nents, hwif->sg_dma_direction);
244 hwif->sg_nents = nents;
249 * Configure the IOMD to give the appropriate timings for the transfer
250 * mode being requested. We take the advice of the ATA standards, and
251 * calculate the cycle time based on the transfer mode, and the EIDE
252 * MW DMA specs that the drive provides in the IDENTIFY command.
254 * We have the following IOMD DMA modes to choose from:
256 * Type Active Recovery Cycle
257 * A 250 (250) 312 (550) 562 (800)
259 * C 125 (125) 125 (375) 250 (500)
262 * (figures in brackets are actual measured timings)
264 * However, we also need to take care of the read/write active and
268 * Mode Active -- Recovery -- Cycle IOMD type
269 * MW0 215 50 215 480 A
273 static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode)
275 int on = 0, cycle_time = 0, use_dma_info = 0;
278 * Limit the transfer speed to MW_DMA_2.
280 if (xfer_mode > XFER_MW_DMA_2)
281 xfer_mode = XFER_MW_DMA_2;
306 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
307 * take care to note the values in the ID...
309 if (use_dma_info && drive->id->eide_dma_time > cycle_time)
310 cycle_time = drive->id->eide_dma_time;
312 drive->drive_data = cycle_time;
314 if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
317 drive->drive_data = 480;
319 printk("%s: %s selected (peak %dMB/s)\n", drive->name,
320 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
322 drive->current_speed = xfer_mode;
327 static int icside_dma_host_off(ide_drive_t *drive)
332 static int icside_dma_off_quietly(ide_drive_t *drive)
334 drive->using_dma = 0;
335 return icside_dma_host_off(drive);
338 static int icside_dma_host_on(ide_drive_t *drive)
343 static int icside_dma_on(ide_drive_t *drive)
345 drive->using_dma = 1;
346 return icside_dma_host_on(drive);
349 static int icside_dma_check(ide_drive_t *drive)
351 struct hd_driveid *id = drive->id;
352 ide_hwif_t *hwif = HWIF(drive);
353 int xfer_mode = XFER_PIO_2;
356 if (!(id->capability & 1) || !hwif->autodma)
360 * Consult the list of known "bad" drives
362 if (__ide_dma_bad_drive(drive))
366 * Enable DMA on any drive that has multiword DMA
368 if (id->field_valid & 2) {
369 xfer_mode = ide_dma_speed(drive, 0);
374 * Consult the list of known "good" drives
376 if (__ide_dma_good_drive(drive)) {
377 if (id->eide_dma_time > 150)
379 xfer_mode = XFER_MW_DMA_1;
383 on = icside_set_speed(drive, xfer_mode);
386 return icside_dma_on(drive);
388 return icside_dma_off_quietly(drive);
391 static int icside_dma_end(ide_drive_t *drive)
393 ide_hwif_t *hwif = HWIF(drive);
394 struct icside_state *state = hwif->hwif_data;
396 drive->waiting_for_dma = 0;
398 disable_dma(hwif->hw.dma);
400 /* Teardown mappings after DMA has completed. */
401 dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
402 hwif->sg_dma_direction);
404 hwif->sg_dma_active = 0;
406 return get_dma_residue(hwif->hw.dma) != 0;
409 static int icside_dma_begin(ide_drive_t *drive)
411 ide_hwif_t *hwif = HWIF(drive);
413 /* We can not enable DMA on both channels simultaneously. */
414 BUG_ON(dma_channel_active(hwif->hw.dma));
415 enable_dma(hwif->hw.dma);
420 * dma_intr() is the handler for disk read/write DMA interrupts
422 static ide_startstop_t icside_dmaintr(ide_drive_t *drive)
427 dma_stat = icside_dma_end(drive);
428 stat = HWIF(drive)->INB(IDE_STATUS_REG);
429 if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | DRQ_STAT)) {
431 struct request *rq = HWGROUP(drive)->rq;
434 for (i = rq->nr_sectors; i > 0; ) {
435 i -= rq->current_nr_sectors;
436 DRIVER(drive)->end_request(drive, 1, rq->nr_sectors);
441 printk(KERN_ERR "%s: bad DMA status (dma_stat=%x)\n",
442 drive->name, dma_stat);
445 return DRIVER(drive)->error(drive, __FUNCTION__, stat);
449 icside_dma_common(ide_drive_t *drive, struct request *rq,
450 unsigned int dma_mode)
452 ide_hwif_t *hwif = HWIF(drive);
455 * We can not enable DMA on both channels.
457 BUG_ON(hwif->sg_dma_active);
458 BUG_ON(dma_channel_active(hwif->hw.dma));
460 icside_build_sglist(drive, rq);
463 * Ensure that we have the right interrupt routed.
465 icside_maskproc(drive, 0);
468 * Route the DMA signals to the correct interface.
470 outb(hwif->select_data, hwif->config_data);
473 * Select the correct timing for this drive.
475 set_dma_speed(hwif->hw.dma, drive->drive_data);
478 * Tell the DMA engine about the SG table and
481 set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
482 set_dma_mode(hwif->hw.dma, dma_mode);
484 drive->waiting_for_dma = 1;
489 static int icside_dma_read(ide_drive_t *drive)
491 struct request *rq = HWGROUP(drive)->rq;
494 if (icside_dma_common(drive, rq, DMA_MODE_READ))
497 if (drive->media != ide_disk)
500 BUG_ON(HWGROUP(drive)->handler != NULL);
503 * FIX ME to use only ACB ide_task_t args Struct
507 ide_task_t *args = rq->special;
508 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
511 if (rq->flags & REQ_DRIVE_TASKFILE) {
512 ide_task_t *args = rq->special;
513 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
514 } else if (drive->addressing == 1) {
515 cmd = WIN_READDMA_EXT;
520 /* issue cmd to drive */
521 ide_execute_command(drive, cmd, icside_dmaintr, 2*WAIT_CMD, NULL);
523 return icside_dma_begin(drive);
526 static int icside_dma_write(ide_drive_t *drive)
528 struct request *rq = HWGROUP(drive)->rq;
531 if (icside_dma_common(drive, rq, DMA_MODE_WRITE))
534 if (drive->media != ide_disk)
537 BUG_ON(HWGROUP(drive)->handler != NULL);
540 * FIX ME to use only ACB ide_task_t args Struct
544 ide_task_t *args = rq->special;
545 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
548 if (rq->flags & REQ_DRIVE_TASKFILE) {
549 ide_task_t *args = rq->special;
550 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
551 } else if (drive->addressing == 1) {
552 cmd = WIN_WRITEDMA_EXT;
558 /* issue cmd to drive */
559 ide_execute_command(drive, cmd, icside_dmaintr, 2*WAIT_CMD, NULL);
561 return icside_dma_begin(drive);
564 static int icside_dma_test_irq(ide_drive_t *drive)
566 ide_hwif_t *hwif = HWIF(drive);
567 struct icside_state *state = hwif->hwif_data;
569 return inb(state->irq_port +
571 ICS_ARCIN_V6_INTRSTAT_2 :
572 ICS_ARCIN_V6_INTRSTAT_1)) & 1;
575 static int icside_dma_verbose(ide_drive_t *drive)
577 printk(", %s (peak %dMB/s)",
578 ide_xfer_verbose(drive->current_speed),
579 2000 / drive->drive_data);
583 static int icside_dma_timeout(ide_drive_t *drive)
585 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
587 if (icside_dma_test_irq(drive))
590 ide_dump_status(drive, "DMA timeout",
591 HWIF(drive)->INB(IDE_STATUS_REG));
593 return icside_dma_end(drive);
596 static int icside_dma_lostirq(ide_drive_t *drive)
598 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
602 static int icside_dma_init(ide_hwif_t *hwif)
606 #ifdef CONFIG_IDEDMA_ICS_AUTO
610 printk(" %s: SG-DMA", hwif->name);
612 hwif->sg_table = kmalloc(sizeof(struct scatterlist) * NR_ENTRIES,
618 hwif->mwdma_mask = 7; /* MW0..2 */
619 hwif->swdma_mask = 7; /* SW0..2 */
621 hwif->dmatable_cpu = NULL;
622 hwif->dmatable_dma = 0;
623 hwif->speedproc = icside_set_speed;
624 hwif->autodma = autodma;
626 hwif->ide_dma_check = icside_dma_check;
627 hwif->ide_dma_host_off = icside_dma_host_off;
628 hwif->ide_dma_off_quietly = icside_dma_off_quietly;
629 hwif->ide_dma_host_on = icside_dma_host_on;
630 hwif->ide_dma_on = icside_dma_on;
631 hwif->ide_dma_read = icside_dma_read;
632 hwif->ide_dma_write = icside_dma_write;
633 hwif->ide_dma_begin = icside_dma_begin;
634 hwif->ide_dma_end = icside_dma_end;
635 hwif->ide_dma_test_irq = icside_dma_test_irq;
636 hwif->ide_dma_verbose = icside_dma_verbose;
637 hwif->ide_dma_timeout = icside_dma_timeout;
638 hwif->ide_dma_lostirq = icside_dma_lostirq;
640 hwif->drives[0].autodma = hwif->autodma;
641 hwif->drives[1].autodma = hwif->autodma;
643 printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
648 printk(" disabled, unable to allocate DMA table\n");
652 static void icside_dma_exit(ide_hwif_t *hwif)
654 if (hwif->sg_table) {
655 kfree(hwif->sg_table);
656 hwif->sg_table = NULL;
660 #define icside_dma_init(hwif) (0)
661 #define icside_dma_exit(hwif) do { } while (0)
664 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
669 for (index = 0; index < MAX_HWIFS; ++index) {
670 hwif = &ide_hwifs[index];
671 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
675 for (index = 0; index < MAX_HWIFS; ++index) {
676 hwif = &ide_hwifs[index];
677 if (!hwif->io_ports[IDE_DATA_OFFSET])
687 icside_setup(unsigned long base, struct cardinfo *info, struct expansion_card *ec)
689 unsigned long port = base + info->dataoffset;
692 hwif = icside_find_hwif(base);
696 memset(&hwif->hw, 0, sizeof(hw_regs_t));
698 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
699 hwif->hw.io_ports[i] = port;
700 hwif->io_ports[i] = port;
701 port += 1 << info->stepping;
703 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
704 hwif->io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
705 hwif->hw.irq = ec->irq;
708 hwif->chipset = ide_acorn;
709 hwif->gendev.parent = &ec->dev;
716 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
718 unsigned long slot_port;
721 slot_port = ecard_address(ec, ECARD_MEMC, 0);
723 state->irq_port = slot_port;
725 ec->irqaddr = (unsigned char *)ioaddr(slot_port + ICS_ARCIN_V5_INTRSTAT);
727 ec->irq_data = state;
728 ec->ops = &icside_ops_arcin_v5;
731 * Be on the safe side - disable interrupts
733 inb(slot_port + ICS_ARCIN_V5_INTROFFSET);
735 hwif = icside_setup(slot_port, &icside_cardinfo_v5, ec);
737 state->hwif[0] = hwif;
739 return hwif ? 0 : -ENODEV;
743 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
745 unsigned long slot_port, port;
746 ide_hwif_t *hwif, *mate;
747 unsigned int sel = 0;
749 slot_port = ecard_address(ec, ECARD_IOC, ECARD_FAST);
750 port = ecard_address(ec, ECARD_EASI, ECARD_FAST);
757 outb(sel, slot_port);
760 * Be on the safe side - disable interrupts
762 inb(port + ICS_ARCIN_V6_INTROFFSET_1);
763 inb(port + ICS_ARCIN_V6_INTROFFSET_2);
766 * Find and register the interfaces.
768 hwif = icside_setup(port, &icside_cardinfo_v6_1, ec);
769 mate = icside_setup(port, &icside_cardinfo_v6_2, ec);
774 state->irq_port = port;
775 state->slot_port = slot_port;
776 state->hwif[0] = hwif;
777 state->hwif[1] = mate;
779 ec->irq_data = state;
780 ec->ops = &icside_ops_arcin_v6;
782 hwif->maskproc = icside_maskproc;
784 hwif->hwif_data = state;
786 hwif->serialized = 1;
787 hwif->config_data = slot_port;
788 hwif->select_data = sel;
789 hwif->hw.dma = ec->dma;
791 mate->maskproc = icside_maskproc;
793 mate->hwif_data = state;
795 mate->serialized = 1;
796 mate->config_data = slot_port;
797 mate->select_data = sel | 1;
798 mate->hw.dma = ec->dma;
800 if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
801 icside_dma_init(hwif);
802 icside_dma_init(mate);
809 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
811 struct icside_state *state;
815 state = kmalloc(sizeof(struct icside_state), GFP_KERNEL);
821 memset(state, 0, sizeof(state));
822 state->type = ICS_TYPE_NOTYPE;
823 state->dev = &ec->dev;
825 idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
826 ecard_resource_len(ec, ECARD_RES_IOCFAST));
830 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
831 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
832 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
833 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
839 switch (state->type) {
841 printk(KERN_WARNING "icside: A3IN unsupported\n");
845 case ICS_TYPE_A3USER:
846 printk(KERN_WARNING "icside: A3USER unsupported\n");
851 ret = icside_register_v5(state, ec);
855 ret = icside_register_v6(state, ec);
859 printk(KERN_WARNING "icside: unknown interface type\n");
865 ecard_set_drvdata(ec, state);
872 static void __devexit icside_remove(struct expansion_card *ec)
874 struct icside_state *state = ecard_get_drvdata(ec);
876 switch (state->type) {
878 /* FIXME: tell IDE to stop using the interface */
880 /* Disable interrupts */
881 inb(state->slot_port + ICS_ARCIN_V5_INTROFFSET);
885 /* FIXME: tell IDE to stop using the interface */
886 icside_dma_exit(state->hwif[1]);
887 icside_dma_exit(state->hwif[0]);
889 if (ec->dma != NO_DMA)
892 /* Disable interrupts */
893 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
894 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
896 /* Reset the ROM pointer/EASI selection */
897 outb(0, state->slot_port);
901 ecard_set_drvdata(ec, NULL);
908 static void icside_shutdown(struct expansion_card *ec)
910 struct icside_state *state = ecard_get_drvdata(ec);
912 switch (state->type) {
914 /* Disable interrupts */
915 inb(state->slot_port + ICS_ARCIN_V5_INTROFFSET);
919 /* Disable interrupts */
920 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
921 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
923 /* Reset the ROM pointer/EASI selection */
924 outb(0, state->slot_port);
929 static const struct ecard_id icside_ids[] = {
930 { MANU_ICS, PROD_ICS_IDE },
931 { MANU_ICS2, PROD_ICS2_IDE },
935 static struct ecard_driver icside_driver = {
936 .probe = icside_probe,
937 .remove = __devexit_p(icside_remove),
938 .shutdown = icside_shutdown,
939 .id_table = icside_ids,
945 static int __init icside_init(void)
947 return ecard_register_driver(&icside_driver);
950 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
951 MODULE_LICENSE("GPL");
952 MODULE_DESCRIPTION("ICS IDE driver");
954 module_init(icside_init);