2 * IDE tuning and bus mastering support for the CS5510/CS5520
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information.
13 * *** This driver is strictly experimental ***
15 * (c) Copyright Red Hat Inc 2002
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2, or (at your option) any
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 * General Public License for more details.
27 * For the avoidance of doubt the "preferred form" of this code is one which
28 * is in an open non patent encumbered format. Where cryptographic key signing
29 * forms part of the process of creating an executable the information
30 * including keys needed to generate an equivalently functional executable
31 * are deemed to be part of the source code.
35 #include <linux/config.h>
36 #include <linux/module.h>
37 #include <linux/types.h>
38 #include <linux/kernel.h>
39 #include <linux/delay.h>
40 #include <linux/timer.h>
42 #include <linux/ioport.h>
43 #include <linux/blkdev.h>
44 #include <linux/hdreg.h>
46 #include <linux/interrupt.h>
47 #include <linux/init.h>
48 #include <linux/pci.h>
49 #include <linux/ide.h>
54 #define DISPLAY_CS5520_TIMINGS
56 #if defined(DISPLAY_CS5520_TIMINGS) && defined(CONFIG_PROC_FS)
57 #include <linux/stat.h>
58 #include <linux/proc_fs.h>
60 static u8 cs5520_proc = 0;
61 static struct pci_dev *bmide_dev;
63 static int cs5520_get_info(char *buffer, char **addr, off_t offset, int count)
66 unsigned long bmiba = pci_resource_start(bmide_dev, 2);
73 * at that point bibma+0x2 et bibma+0xa are byte registers
76 c0 = inb(bmiba + 0x02);
77 c1 = inb(bmiba + 0x0a);
79 p += sprintf(p, "\nCyrix CS55x0 IDE\n");
80 p += sprintf(p, "--------------- Primary Channel "
81 "---------------- Secondary Channel "
83 p += sprintf(p, " %sabled "
85 (c0&0x80) ? "dis" : " en",
86 (c1&0x80) ? "dis" : " en");
88 p += sprintf(p, "\n\nTimings: \n");
90 pci_read_config_word(bmide_dev, 0x62, ®16);
91 p += sprintf(p, "8bit CAT/CRT : %04x\n", reg16);
92 pci_read_config_dword(bmide_dev, 0x64, ®32);
93 p += sprintf(p, "16bit Primary : %08x\n", reg32);
94 pci_read_config_dword(bmide_dev, 0x68, ®32);
95 p += sprintf(p, "16bit Secondary: %08x\n", reg32);
97 len = (p - buffer) - offset;
98 *addr = buffer + offset;
100 return len > count ? count : len;
112 struct pio_clocks cs5520_pio_clocks[]={
120 static int cs5520_tune_chipset(ide_drive_t *drive, u8 xferspeed)
122 ide_hwif_t *hwif = HWIF(drive);
123 struct pci_dev *pdev = hwif->pci_dev;
124 u8 speed = min((u8)XFER_PIO_4, xferspeed);
127 int controller = drive->dn > 1 ? 1 : 0;
141 printk(KERN_ERR "cs55x0: bad ide timing.\n");
144 printk("PIO clocking = %d\n", pio);
146 /* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
148 /* 8bit command timing for channel */
149 pci_write_config_byte(pdev, 0x62 + controller,
150 (cs5520_pio_clocks[pio].recovery << 4) |
151 (cs5520_pio_clocks[pio].assert));
153 /* FIXME: should these use address ? */
154 /* Data read timing */
155 pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
156 (cs5520_pio_clocks[pio].recovery << 4) |
157 (cs5520_pio_clocks[pio].assert));
158 /* Write command timing */
159 pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
160 (cs5520_pio_clocks[pio].recovery << 4) |
161 (cs5520_pio_clocks[pio].assert));
163 /* Set the DMA enable/disable flag */
164 reg = inb(hwif->dma_base + 0x02 + 8*controller);
165 reg |= 1<<((drive->dn&1)+5);
166 outb(reg, hwif->dma_base + 0x02 + 8*controller);
168 error = ide_config_drive_speed(drive, speed);
169 /* ATAPI is harder so leave it for now */
170 if(!error && drive->media == ide_disk)
171 error = hwif->ide_dma_on(drive);
176 static void cs5520_tune_drive(ide_drive_t *drive, u8 pio)
178 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
179 cs5520_tune_chipset(drive, (XFER_PIO_0 + pio));
182 static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
184 ide_hwif_t *hwif = HWIF(drive);
186 /* Tune the drive for PIO modes up to PIO 4 */
187 cs5520_tune_drive(drive, 4);
188 /* Then tell the core to use DMA operations */
189 return hwif->ide_dma_on(drive);
193 static unsigned int __devinit init_chipset_cs5520(struct pci_dev *dev, const char *name)
195 #if defined(DISPLAY_CS5520_TIMINGS) && defined(CONFIG_PROC_FS)
199 ide_pci_create_host_proc("cs5520", cs5520_get_info);
201 #endif /* DISPLAY_CS5520_TIMINGS && CONFIG_PROC_FS */
206 * We provide a callback for our nonstandard DMA location
209 static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
211 unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
212 if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
214 ide_setup_dma(hwif, bmide, 8);
218 * We wrap the DMA activate to set the vdma flag. This is needed
219 * so that the IDE DMA layer issues PIO not DMA commands over the
223 static int cs5520_dma_on(ide_drive_t *drive)
229 static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
231 hwif->tuneproc = &cs5520_tune_drive;
232 hwif->speedproc = &cs5520_tune_chipset;
233 hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
234 hwif->ide_dma_on = &cs5520_dma_on;
241 hwif->drives[0].autotune = 1;
242 hwif->drives[1].autotune = 1;
247 hwif->ultra_mask = 0;
248 hwif->swdma_mask = 0;
249 hwif->mwdma_mask = 0;
251 hwif->drives[0].autodma = hwif->autodma;
252 hwif->drives[1].autodma = hwif->autodma;
255 #define DECLARE_CS_DEV(name_str) \
258 .init_chipset = init_chipset_cs5520, \
259 .init_setup_dma = cs5520_init_setup_dma, \
260 .init_hwif = init_hwif_cs5520, \
262 .autodma = AUTODMA, \
263 .bootable = ON_BOARD, \
264 .flags = IDEPCI_FLAG_ISA_PORTS, \
267 static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
268 /* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
269 /* 1 */ DECLARE_CS_DEV("Cyrix 5520")
273 * The 5510/5520 are a bit weird. They don't quite set up the way
274 * the PCI helper layer expects so we must do much of the set up
278 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
281 ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
283 ide_setup_pci_noise(dev, d);
285 /* We must not grab the entire device, it has 'ISA' space in its
286 BARS too and we will freak out other bits of the kernel */
287 if(pci_enable_device_bars(dev, 1<<2))
289 printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
293 if (pci_set_dma_mask(dev, 0xFFFFFFFF)) {
294 printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
297 init_chipset_cs5520(dev, d->name);
302 * Now the chipset is configured we can let the core
303 * do all the device setup for us
306 ide_pci_setup_ports(dev, d, 1, 14, &index);
308 if((index.b.low & 0xf0) != 0xf0)
309 probe_hwif_init(&ide_hwifs[index.b.low]);
310 if((index.b.high & 0xf0) != 0xf0)
311 probe_hwif_init(&ide_hwifs[index.b.high]);
315 static struct pci_device_id cs5520_pci_tbl[] = {
316 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
317 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
320 MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
322 static struct pci_driver driver = {
324 .id_table = cs5520_pci_tbl,
325 .probe = cs5520_init_one,
328 static int cs5520_ide_init(void)
330 return ide_pci_register_driver(&driver);
333 module_init(cs5520_ide_init);
335 MODULE_AUTHOR("Alan Cox");
336 MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
337 MODULE_LICENSE("GPL");