2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
13 * Note that final HPT370 support was done by force extraction of GPL.
15 * - add function for getting/setting power status of drive
16 * - the HPT370's state machine can get confused. reset it before each dma
17 * xfer to prevent that from happening.
18 * - reset state engine whenever we get an error.
19 * - check for busmaster state at end of dma.
20 * - use new highpoint timings.
21 * - detect bus speed using highpoint register.
22 * - use pll if we don't have a clock table. added a 66MHz table that's
23 * just 2x the 33MHz table.
24 * - removed turnaround. NOTE: we never want to switch between pll and
25 * pci clocks as the chip can glitch in those cases. the highpoint
26 * approved workaround slows everything down too much to be useful. in
27 * addition, we would have to serialize access to each chip.
28 * Adrian Sun <a.sun@sun.com>
30 * add drive timings for 66MHz PCI bus,
31 * fix ATA Cable signal detection, fix incorrect /proc info
32 * add /proc display for per-drive PIO/DMA/UDMA mode and
33 * per-channel ATA-33/66 Cable detect.
34 * Duncan Laurie <void@sun.com>
36 * fixup /proc output for multiple controllers
37 * Tim Hockin <thockin@sun.com>
40 * Reset the hpt366 on error, reset on dma
41 * Fix disabling Fast Interrupt hpt366.
42 * Mike Waychison <crlf@sun.com>
44 * Added support for 372N clocking and clock switching. The 372N needs
45 * different clocks on read/write. This requires overloading rw_disk and
46 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
48 * Alan Cox <alan@redhat.com>
53 #include <linux/config.h>
54 #include <linux/types.h>
55 #include <linux/module.h>
56 #include <linux/kernel.h>
57 #include <linux/delay.h>
58 #include <linux/timer.h>
60 #include <linux/ioport.h>
61 #include <linux/blkdev.h>
62 #include <linux/hdreg.h>
64 #include <linux/interrupt.h>
65 #include <linux/pci.h>
66 #include <linux/init.h>
67 #include <linux/ide.h>
69 #include <asm/uaccess.h>
75 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
76 #include <linux/stat.h>
77 #include <linux/proc_fs.h>
78 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
80 static unsigned int hpt_revision(struct pci_dev *dev);
81 static unsigned int hpt_minimum_revision(struct pci_dev *dev, int revision);
83 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
85 static u8 hpt366_proc = 0;
86 static struct pci_dev *hpt_devs[HPT366_MAX_DEVS];
87 static int n_hpt_devs;
89 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
92 char *chipset_nums[] = {"366", "366", "368",
94 "302", "371", "374" };
98 "HighPoint HPT366/368/370/372/374\n");
99 for (i = 0; i < n_hpt_devs; i++) {
100 struct pci_dev *dev = hpt_devs[i];
101 unsigned long iobase = dev->resource[4].start;
102 u32 class_rev = hpt_revision(dev);
105 p += sprintf(p, "\nController: %d\n", i);
106 p += sprintf(p, "Chipset: HPT%s\n", chipset_nums[class_rev]);
107 p += sprintf(p, "--------------- Primary Channel "
108 "--------------- Secondary Channel "
111 /* get the bus master status registers */
112 c0 = inb(iobase + 0x2);
113 c1 = inb(iobase + 0xa);
114 p += sprintf(p, "Enabled: %s"
116 (c0 & 0x80) ? "no" : "yes",
117 (c1 & 0x80) ? "no" : "yes");
119 if (hpt_minimum_revision(dev, 3)) {
121 cbl = inb(iobase + 0x7b);
122 outb(cbl | 1, iobase + 0x7b);
123 outb(cbl & ~1, iobase + 0x7b);
124 cbl = inb(iobase + 0x7a);
125 p += sprintf(p, "Cable: ATA-%d"
127 (cbl & 0x02) ? 33 : 66,
128 (cbl & 0x01) ? 33 : 66);
129 p += sprintf(p, "\n");
132 p += sprintf(p, "--------------- drive0 --------- drive1 "
133 "------- drive0 ---------- drive1 -------\n");
134 p += sprintf(p, "DMA capable: %s %s"
136 (c0 & 0x20) ? "yes" : "no ",
137 (c0 & 0x40) ? "yes" : "no ",
138 (c1 & 0x20) ? "yes" : "no ",
139 (c1 & 0x40) ? "yes" : "no ");
143 /* older revs don't have these registers mapped
145 pci_read_config_byte(dev, 0x43, &c0);
146 pci_read_config_byte(dev, 0x47, &c1);
147 pci_read_config_byte(dev, 0x4b, &c2);
148 pci_read_config_byte(dev, 0x4f, &c3);
150 p += sprintf(p, "Mode: %s %s"
152 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
153 (c0 & 0x80) ? "PIO " : "off ",
154 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
155 (c1 & 0x80) ? "PIO " : "off ",
156 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
157 (c2 & 0x80) ? "PIO " : "off ",
158 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
159 (c3 & 0x80) ? "PIO " : "off ");
162 p += sprintf(p, "\n");
164 /* p - buffer must be less than 4k! */
165 len = (p - buffer) - offset;
166 *addr = buffer + offset;
168 return len > count ? count : len;
170 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
172 static u32 hpt_revision (struct pci_dev *dev)
175 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
178 switch(dev->device) {
179 /* Remap new 372N onto 372 */
180 case PCI_DEVICE_ID_TTI_HPT372N:
181 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
182 case PCI_DEVICE_ID_TTI_HPT374:
183 class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
184 case PCI_DEVICE_ID_TTI_HPT371:
185 class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
186 case PCI_DEVICE_ID_TTI_HPT302:
187 class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
188 case PCI_DEVICE_ID_TTI_HPT372:
189 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
196 static u32 hpt_minimum_revision (struct pci_dev *dev, int revision)
198 unsigned int class_rev = hpt_revision(dev);
200 return ((int) (class_rev > revision) ? 1 : 0);
203 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
205 static u8 hpt3xx_ratemask (ide_drive_t *drive)
207 struct pci_dev *dev = HWIF(drive)->pci_dev;
210 if (hpt_minimum_revision(dev, 8)) { /* HPT374 */
211 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
212 } else if (hpt_minimum_revision(dev, 7)) { /* HPT371 */
213 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
214 } else if (hpt_minimum_revision(dev, 6)) { /* HPT302 */
215 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
216 } else if (hpt_minimum_revision(dev, 5)) { /* HPT372 */
217 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
218 } else if (hpt_minimum_revision(dev, 4)) { /* HPT370A */
219 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
220 } else if (hpt_minimum_revision(dev, 3)) { /* HPT370 */
221 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
222 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
223 } else { /* HPT366 and HPT368 */
224 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
226 if (!eighty_ninty_three(drive) && (mode))
227 mode = min(mode, (u8)1);
232 * Note for the future; the SATA hpt37x we must set
233 * either PIO or UDMA modes 0,4,5
236 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
238 struct pci_dev *dev = HWIF(drive)->pci_dev;
239 u8 mode = hpt3xx_ratemask(drive);
241 if (drive->media != ide_disk)
242 return min(speed, (u8)XFER_PIO_4);
246 speed = min(speed, (u8)XFER_UDMA_6);
249 speed = min(speed, (u8)XFER_UDMA_5);
250 if (hpt_minimum_revision(dev, 5))
252 if (check_in_drive_lists(drive, bad_ata100_5))
253 speed = min(speed, (u8)XFER_UDMA_4);
256 speed = min(speed, (u8)XFER_UDMA_4);
258 * CHECK ME, Does this need to be set to 5 ??
260 if (hpt_minimum_revision(dev, 3))
262 if ((check_in_drive_lists(drive, bad_ata66_4)) ||
263 (!(HPT366_ALLOW_ATA66_4)))
264 speed = min(speed, (u8)XFER_UDMA_3);
265 if ((check_in_drive_lists(drive, bad_ata66_3)) ||
266 (!(HPT366_ALLOW_ATA66_3)))
267 speed = min(speed, (u8)XFER_UDMA_2);
270 speed = min(speed, (u8)XFER_UDMA_2);
272 * CHECK ME, Does this need to be set to 5 ??
274 if (hpt_minimum_revision(dev, 3))
276 if (check_in_drive_lists(drive, bad_ata33))
277 speed = min(speed, (u8)XFER_MW_DMA_2);
281 speed = min(speed, (u8)XFER_MW_DMA_2);
287 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
289 struct hd_driveid *id = drive->id;
291 if (quirk_drives == list) {
293 if (strstr(id->model, *list++))
297 if (!strcmp(*list++,id->model))
303 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
305 for ( ; chipset_table->xfer_speed ; chipset_table++)
306 if (chipset_table->xfer_speed == speed)
307 return chipset_table->chipset_settings;
308 return chipset_table->chipset_settings;
311 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
313 struct pci_dev *dev = HWIF(drive)->pci_dev;
314 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
315 // u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
316 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
317 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
319 u32 reg1 = 0, reg2 = 0;
322 * Disable the "fast interrupt" prediction.
324 pci_read_config_byte(dev, regfast, &drive_fast);
326 if (drive_fast & 0x02)
327 pci_write_config_byte(dev, regfast, drive_fast & ~0x20);
329 if (drive_fast & 0x80)
330 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
333 reg2 = pci_bus_clock_list(speed,
334 (struct chipset_bus_clock_list_entry *) pci_get_drvdata(dev));
336 * Disable on-chip PIO FIFO/buffer
337 * (to avoid problems handling I/O errors later)
339 pci_read_config_dword(dev, regtime, ®1);
340 if (speed >= XFER_MW_DMA_0) {
341 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
343 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
347 pci_write_config_dword(dev, regtime, reg2);
349 return ide_config_drive_speed(drive, speed);
352 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
354 struct pci_dev *dev = HWIF(drive)->pci_dev;
355 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
356 // u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
357 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
358 u8 drive_pci = 0x40 + (drive->dn * 4);
359 u8 new_fast = 0, drive_fast = 0;
360 u32 list_conf = 0, drive_conf = 0;
361 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
364 * Disable the "fast interrupt" prediction.
365 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
367 pci_read_config_byte(dev, regfast, &drive_fast);
368 new_fast = drive_fast;
372 #ifdef HPT_DELAY_INTERRUPT
376 if ((new_fast & 0x01) == 0)
379 if (new_fast != drive_fast)
380 pci_write_config_byte(dev, regfast, new_fast);
382 list_conf = pci_bus_clock_list(speed,
383 (struct chipset_bus_clock_list_entry *)
384 pci_get_drvdata(dev));
386 pci_read_config_dword(dev, drive_pci, &drive_conf);
387 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
389 if (speed < XFER_MW_DMA_0) {
390 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
393 pci_write_config_dword(dev, drive_pci, list_conf);
395 return ide_config_drive_speed(drive, speed);
398 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
400 struct pci_dev *dev = HWIF(drive)->pci_dev;
401 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
402 // u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
403 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
404 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
405 u32 list_conf = 0, drive_conf = 0;
406 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
409 * Disable the "fast interrupt" prediction.
410 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
412 pci_read_config_byte(dev, regfast, &drive_fast);
414 pci_write_config_byte(dev, regfast, drive_fast);
416 list_conf = pci_bus_clock_list(speed,
417 (struct chipset_bus_clock_list_entry *)
418 pci_get_drvdata(dev));
419 pci_read_config_dword(dev, drive_pci, &drive_conf);
420 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
421 if (speed < XFER_MW_DMA_0)
422 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
423 pci_write_config_dword(dev, drive_pci, list_conf);
425 return ide_config_drive_speed(drive, speed);
428 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
430 struct pci_dev *dev = HWIF(drive)->pci_dev;
432 if (hpt_minimum_revision(dev, 8))
433 return hpt372_tune_chipset(drive, speed); /* not a typo */
435 else if (hpt_minimum_revision(dev, 7))
436 hpt371_tune_chipset(drive, speed);
437 else if (hpt_minimum_revision(dev, 6))
438 hpt302_tune_chipset(drive, speed);
440 else if (hpt_minimum_revision(dev, 5))
441 return hpt372_tune_chipset(drive, speed);
442 else if (hpt_minimum_revision(dev, 3))
443 return hpt370_tune_chipset(drive, speed);
444 else /* hpt368: hpt_minimum_revision(dev, 2) */
445 return hpt36x_tune_chipset(drive, speed);
448 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
450 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
451 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
455 * This allows the configuration of ide_pci chipset registers
456 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
457 * after the drive is reported by the OS. Initially for designed for
458 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
460 * check_in_drive_lists(drive, bad_ata66_4)
461 * check_in_drive_lists(drive, bad_ata66_3)
462 * check_in_drive_lists(drive, bad_ata33)
465 static int config_chipset_for_dma (ide_drive_t *drive)
467 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
472 (void) hpt3xx_tune_chipset(drive, speed);
473 return ide_dma_enable(drive);
476 static int hpt3xx_quirkproc (ide_drive_t *drive)
478 return ((int) check_in_drive_lists(drive, quirk_drives));
481 static void hpt3xx_intrproc (ide_drive_t *drive)
483 ide_hwif_t *hwif = HWIF(drive);
485 if (drive->quirk_list)
487 /* drives in the quirk_list may not like intr setups/cleanups */
488 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
491 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
493 struct pci_dev *dev = HWIF(drive)->pci_dev;
495 if (drive->quirk_list) {
496 if (hpt_minimum_revision(dev,3)) {
498 pci_read_config_byte(dev, 0x5a, ®5a);
499 if (((reg5a & 0x10) >> 4) != mask)
500 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
503 disable_irq(HWIF(drive)->irq);
505 enable_irq(HWIF(drive)->irq);
510 HWIF(drive)->OUTB(mask ? (drive->ctl | 2) :
516 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
518 ide_hwif_t *hwif = HWIF(drive);
519 struct hd_driveid *id = drive->id;
521 drive->init_speed = 0;
523 if (id && (id->capability & 1) && drive->autodma) {
524 /* Consult the list of known "bad" drives */
525 if (__ide_dma_bad_drive(drive))
527 if (id->field_valid & 4) {
528 if (id->dma_ultra & hwif->ultra_mask) {
529 /* Force if Capable UltraDMA */
530 int dma = config_chipset_for_dma(drive);
531 if ((id->field_valid & 2) && !dma)
534 } else if (id->field_valid & 2) {
536 if (id->dma_mword & hwif->mwdma_mask) {
537 /* Force if Capable regular DMA modes */
538 if (!config_chipset_for_dma(drive))
541 } else if (__ide_dma_good_drive(drive) &&
542 (id->eide_dma_time < 150)) {
543 /* Consult the list of known "good" drives */
544 if (!config_chipset_for_dma(drive))
549 return hwif->ide_dma_on(drive);
550 } else if ((id->capability & 8) || (id->field_valid & 2)) {
553 hpt3xx_tune_drive(drive, 5);
554 return hwif->ide_dma_off_quietly(drive);
556 /* IORDY not supported */
561 * This is specific to the HPT366 UDMA bios chipset
562 * by HighPoint|Triones Technologies, Inc.
564 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
566 struct pci_dev *dev = HWIF(drive)->pci_dev;
567 u8 reg50h = 0, reg52h = 0, reg5ah = 0;
569 pci_read_config_byte(dev, 0x50, ®50h);
570 pci_read_config_byte(dev, 0x52, ®52h);
571 pci_read_config_byte(dev, 0x5a, ®5ah);
572 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
573 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
575 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
577 /* how about we flush and reset, mmmkay? */
578 pci_write_config_byte(dev, 0x51, 0x1F);
579 /* fall through to a reset */
582 /* reset the chips state over and over.. */
583 pci_write_config_byte(dev, 0x51, 0x13);
585 return __ide_dma_lostirq(drive);
588 static void hpt370_clear_engine (ide_drive_t *drive)
590 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
591 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
595 static int hpt370_ide_dma_begin (ide_drive_t *drive)
597 #ifdef HPT_RESET_STATE_ENGINE
598 hpt370_clear_engine(drive);
600 return __ide_dma_begin(drive);
603 static int hpt370_ide_dma_end (ide_drive_t *drive)
605 ide_hwif_t *hwif = HWIF(drive);
606 u8 dma_stat = hwif->INB(hwif->dma_status);
608 if (dma_stat & 0x01) {
611 dma_stat = hwif->INB(hwif->dma_status);
613 if ((dma_stat & 0x01) != 0)
615 (void) HWIF(drive)->ide_dma_timeout(drive);
617 return __ide_dma_end(drive);
620 static void hpt370_lostirq_timeout (ide_drive_t *drive)
622 ide_hwif_t *hwif = HWIF(drive);
623 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
624 u8 dma_stat = 0, dma_cmd = 0;
626 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
627 printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
628 hpt370_clear_engine(drive);
629 /* get dma command mode */
630 dma_cmd = hwif->INB(hwif->dma_command);
632 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
633 dma_stat = hwif->INB(hwif->dma_status);
635 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
638 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
640 hpt370_lostirq_timeout(drive);
641 hpt370_clear_engine(drive);
642 return __ide_dma_timeout(drive);
645 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
647 hpt370_lostirq_timeout(drive);
648 hpt370_clear_engine(drive);
649 return __ide_dma_lostirq(drive);
652 /* returns 1 if DMA IRQ issued, 0 otherwise */
653 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
655 ide_hwif_t *hwif = HWIF(drive);
657 u8 reginfo = hwif->channel ? 0x56 : 0x52;
660 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
662 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
666 dma_stat = hwif->INB(hwif->dma_status);
667 /* return 1 if INTR asserted */
668 if ((dma_stat & 4) == 4)
671 if (!drive->waiting_for_dma)
672 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
673 drive->name, __FUNCTION__);
677 static int hpt374_ide_dma_end (ide_drive_t *drive)
679 struct pci_dev *dev = HWIF(drive)->pci_dev;
680 ide_hwif_t *hwif = HWIF(drive);
681 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
682 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
684 pci_read_config_byte(dev, 0x6a, &bwsr_stat);
685 pci_read_config_byte(dev, mscreg, &msc_stat);
686 if ((bwsr_stat & bwsr_mask) == bwsr_mask)
687 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
688 return __ide_dma_end(drive);
692 * hpt372n_set_clock - perform clock switching dance
693 * @drive: Drive to switch
694 * @mode: Switching mode (0x21 for write, 0x23 otherwise)
696 * Switch the DPLL clock on the HPT372N devices. This is a
700 static void hpt372n_set_clock(ide_drive_t *drive, int mode)
702 ide_hwif_t *hwif = HWIF(drive);
704 /* FIXME: should we check for DMA active and BUG() */
705 /* Tristate the bus */
706 outb(0x80, hwif->dma_base+0x73);
707 outb(0x80, hwif->dma_base+0x77);
709 /* Switch clock and reset channels */
710 outb(mode, hwif->dma_base+0x7B);
711 outb(0xC0, hwif->dma_base+0x79);
713 /* Reset state machines */
714 outb(0x37, hwif->dma_base+0x70);
715 outb(0x37, hwif->dma_base+0x74);
718 outb(0x00, hwif->dma_base+0x79);
720 /* Reconnect channels to bus */
721 outb(0x00, hwif->dma_base+0x73);
722 outb(0x00, hwif->dma_base+0x77);
726 * hpt372n_rw_disk - wrapper for I/O
727 * @drive: drive for command
728 * @rq: block request structure
729 * @block: block number
731 * This is called when a disk I/O is issued to the 372N instead
732 * of the default functionality. We need it because of the clock
737 static ide_startstop_t hpt372n_rw_disk(ide_drive_t *drive, struct request *rq, sector_t block)
741 if(rq_data_dir(rq) == READ)
746 if(HWIF(drive)->config_data != wantclock)
748 hpt372n_set_clock(drive, wantclock);
749 HWIF(drive)->config_data = wantclock;
751 return __ide_do_rw_disk(drive, rq, block);
755 * Since SUN Cobalt is attempting to do this operation, I should disclose
756 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
757 * HOTSWAP ATA Infrastructure.
760 static void hpt3xx_reset (ide_drive_t *drive)
763 unsigned long high_16 = pci_resource_start(HWIF(drive)->pci_dev, 4);
764 u8 reset = (HWIF(drive)->channel) ? 0x80 : 0x40;
767 pci_read_config_byte(HWIF(drive)->pci_dev, 0x59, ®59h);
768 pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h|reset);
769 pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h);
773 static int hpt3xx_tristate (ide_drive_t * drive, int state)
775 ide_hwif_t *hwif = HWIF(drive);
776 struct pci_dev *dev = hwif->pci_dev;
777 u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40;
778 u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
780 // hwif->bus_state = state;
782 pci_read_config_byte(dev, 0x59, ®59h);
783 pci_read_config_byte(dev, state_reg, ®XXh);
786 (void) ide_do_reset(drive);
787 pci_write_config_byte(dev, state_reg, regXXh|0x80);
788 pci_write_config_byte(dev, 0x59, reg59h|reset);
790 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
791 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
792 (void) ide_do_reset(drive);
798 * set/get power state for a drive.
799 * turning the power off does the following things:
800 * 1) soft-reset the drive
801 * 2) tri-states the ide bus
803 * when we turn things back on, we need to re-initialize things.
805 #define TRISTATE_BIT 0x8000
806 static int hpt370_busproc(ide_drive_t * drive, int state)
808 ide_hwif_t *hwif = HWIF(drive);
809 struct pci_dev *dev = hwif->pci_dev;
810 u8 tristate = 0, resetmask = 0, bus_reg = 0;
813 hwif->bus_state = state;
816 /* secondary channel */
820 /* primary channel */
826 pci_read_config_word(dev, tristate, &tri_reg);
827 pci_read_config_byte(dev, 0x59, &bus_reg);
829 /* set the state. we don't set it if we don't need to do so.
830 * make sure that the drive knows that it has failed if it's off */
833 hwif->drives[0].failures = 0;
834 hwif->drives[1].failures = 0;
835 if ((bus_reg & resetmask) == 0)
837 tri_reg &= ~TRISTATE_BIT;
838 bus_reg &= ~resetmask;
841 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
842 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
843 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
845 tri_reg &= ~TRISTATE_BIT;
846 bus_reg |= resetmask;
848 case BUSSTATE_TRISTATE:
849 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
850 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
851 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
853 tri_reg |= TRISTATE_BIT;
854 bus_reg |= resetmask;
857 pci_write_config_byte(dev, 0x59, bus_reg);
858 pci_write_config_word(dev, tristate, tri_reg);
863 static int __devinit init_hpt37x(struct pci_dev *dev)
870 unsigned long dmabase = pci_resource_start(dev, 4);
874 pci_read_config_byte(dev, 0x5a, ®5ah);
875 /* interrupt force enable */
876 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
880 did = inb(dmabase + 0x22);
881 rid = inb(dmabase + 0x28);
883 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
888 * default to pci clock. make sure MA15/16 are set to output
889 * to prevent drives having problems with 40-pin cables.
891 pci_write_config_byte(dev, 0x5b, 0x23);
894 * set up the PLL. we need to adjust it so that it's stable.
895 * freq = Tpll * 192 / Tpci
897 * Todo. For non x86 should probably check the dword is
898 * set to 0xABCDExxx indicating the BIOS saved f_CNT
900 pci_read_config_word(dev, 0x78, &freq);
904 * The 372N uses different PCI clock information and has
905 * some other complications
906 * On PCI33 timing we must clock switch
907 * On PCI66 timing we must NOT use the PCI clock
909 * Currently we always set up the PLL for the 372N
912 pci_set_drvdata(dev, NULL);
916 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
926 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll);
928 /* We always use the pll not the PCI clock on 372N */
941 if (pll == F_LOW_PCI_33) {
942 if (hpt_minimum_revision(dev,8))
943 pci_set_drvdata(dev, (void *) thirty_three_base_hpt374);
944 else if (hpt_minimum_revision(dev,5))
945 pci_set_drvdata(dev, (void *) thirty_three_base_hpt372);
946 else if (hpt_minimum_revision(dev,4))
947 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370a);
949 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370);
950 printk("HPT37X: using 33MHz PCI clock\n");
951 } else if (pll == F_LOW_PCI_40) {
953 } else if (pll == F_LOW_PCI_50) {
954 if (hpt_minimum_revision(dev,8))
955 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
956 else if (hpt_minimum_revision(dev,5))
957 pci_set_drvdata(dev, (void *) fifty_base_hpt372);
958 else if (hpt_minimum_revision(dev,4))
959 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
961 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
962 printk("HPT37X: using 50MHz PCI clock\n");
964 if (hpt_minimum_revision(dev,8))
966 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
968 else if (hpt_minimum_revision(dev,5))
969 pci_set_drvdata(dev, (void *) sixty_six_base_hpt372);
970 else if (hpt_minimum_revision(dev,4))
971 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a);
973 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370);
974 printk("HPT37X: using 66MHz PCI clock\n");
979 * only try the pll if we don't have a table for the clock
980 * speed that we're running at. NOTE: the internal PLL will
981 * result in slow reads when using a 33MHz PCI clock. we also
982 * don't like to use the PLL because it will cause glitches
983 * on PRST/SRST when the HPT state engine gets reset.
985 if (pci_get_drvdata(dev))
986 goto init_hpt37X_done;
989 * adjust PLL based upon PCI clock, enable it, and wait for
993 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
994 while (adjust++ < 6) {
995 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
998 /* wait for clock stabilization */
999 for (i = 0; i < 0x50000; i++) {
1000 pci_read_config_byte(dev, 0x5b, ®5bh);
1001 if (reg5bh & 0x80) {
1002 /* spin looking for the clock to destabilize */
1003 for (i = 0; i < 0x1000; ++i) {
1004 pci_read_config_byte(dev, 0x5b,
1006 if ((reg5bh & 0x80) == 0)
1009 pci_read_config_dword(dev, 0x5c, &pll);
1010 pci_write_config_dword(dev, 0x5c,
1012 pci_write_config_byte(dev, 0x5b, 0x21);
1013 if (hpt_minimum_revision(dev,8))
1014 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1015 else if (hpt_minimum_revision(dev,5))
1016 pci_set_drvdata(dev, (void *) fifty_base_hpt372);
1017 else if (hpt_minimum_revision(dev,4))
1018 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1020 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1021 printk("HPT37X: using 50MHz internal PLL\n");
1022 goto init_hpt37X_done;
1027 pll -= (adjust >> 1);
1029 pll += (adjust >> 1);
1033 /* reset state engine */
1034 pci_write_config_byte(dev, 0x50, 0x37);
1035 pci_write_config_byte(dev, 0x54, 0x37);
1040 static int __devinit init_hpt366(struct pci_dev *dev)
1046 * Disable the "fast interrupt" prediction.
1048 pci_read_config_byte(dev, 0x51, &drive_fast);
1049 if (drive_fast & 0x80)
1050 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1051 pci_read_config_dword(dev, 0x40, ®1);
1053 /* detect bus speed by looking at control reg timing: */
1054 switch((reg1 >> 8) & 7) {
1056 pci_set_drvdata(dev, (void *) forty_base_hpt366);
1059 pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
1063 pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
1067 if (!pci_get_drvdata(dev))
1069 printk(KERN_ERR "hpt366: unknown bus timing.\n");
1070 pci_set_drvdata(dev, NULL);
1075 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1080 if (dev->resource[PCI_ROM_RESOURCE].start)
1081 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
1082 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1084 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
1085 if (test != (L1_CACHE_BYTES / 4))
1086 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1087 (L1_CACHE_BYTES / 4));
1089 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
1091 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1093 pci_read_config_byte(dev, PCI_MIN_GNT, &test);
1095 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1097 pci_read_config_byte(dev, PCI_MAX_LAT, &test);
1099 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1101 if (hpt_minimum_revision(dev, 3)) {
1102 ret = init_hpt37x(dev);
1104 ret =init_hpt366(dev);
1109 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
1110 hpt_devs[n_hpt_devs++] = dev;
1114 ide_pci_create_host_proc("hpt366", hpt366_get_info);
1116 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
1121 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1123 struct pci_dev *dev = hwif->pci_dev;
1124 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1126 unsigned long dmabase = hwif->dma_base;
1131 did = inb(dmabase + 0x22);
1132 rid = inb(dmabase + 0x28);
1134 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1138 hwif->tuneproc = &hpt3xx_tune_drive;
1139 hwif->speedproc = &hpt3xx_tune_chipset;
1140 hwif->quirkproc = &hpt3xx_quirkproc;
1141 hwif->intrproc = &hpt3xx_intrproc;
1142 hwif->maskproc = &hpt3xx_maskproc;
1145 hwif->rw_disk = &hpt372n_rw_disk;
1148 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1149 * address lines to access an external eeprom. To read valid
1150 * cable detect state the pins must be enabled as inputs.
1152 if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) {
1154 * HPT374 PCI function 1
1155 * - set bit 15 of reg 0x52 to enable TCBLID as input
1156 * - set bit 15 of reg 0x56 to enable FCBLID as input
1159 pci_read_config_word(dev, 0x52, &mcr3);
1160 pci_read_config_word(dev, 0x56, &mcr6);
1161 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1162 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1163 /* now read cable id register */
1164 pci_read_config_byte(dev, 0x5a, &ata66);
1165 pci_write_config_word(dev, 0x52, mcr3);
1166 pci_write_config_word(dev, 0x56, mcr6);
1167 } else if (hpt_minimum_revision(dev, 3)) {
1169 * HPT370/372 and 374 pcifn 0
1170 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1173 pci_read_config_byte(dev, 0x5b, &scr2);
1174 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1175 /* now read cable id register */
1176 pci_read_config_byte(dev, 0x5a, &ata66);
1177 pci_write_config_byte(dev, 0x5b, scr2);
1179 pci_read_config_byte(dev, 0x5a, &ata66);
1183 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1184 ata66, (ata66 & regmask) ? "33" : "66",
1185 PCI_FUNC(hwif->pci_dev->devfn));
1188 #ifdef HPT_SERIALIZE_IO
1189 /* serialize access to this device */
1191 hwif->serialized = hwif->mate->serialized = 1;
1194 if (hpt_minimum_revision(dev,3)) {
1196 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1198 * set up ioctl for power status.
1199 * note: power affects both
1200 * drives on each channel
1202 hwif->resetproc = &hpt3xx_reset;
1203 hwif->busproc = &hpt370_busproc;
1204 // hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1205 } else if (hpt_minimum_revision(dev,2)) {
1206 hwif->resetproc = &hpt3xx_reset;
1207 hwif->busproc = &hpt3xx_tristate;
1209 hwif->resetproc = &hpt3xx_reset;
1210 hwif->busproc = &hpt3xx_tristate;
1213 if (!hwif->dma_base) {
1214 hwif->drives[0].autotune = 1;
1215 hwif->drives[1].autotune = 1;
1219 hwif->ultra_mask = 0x7f;
1220 hwif->mwdma_mask = 0x07;
1222 if (!(hwif->udma_four))
1223 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1224 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1226 if (hpt_minimum_revision(dev,8)) {
1227 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1228 hwif->ide_dma_end = &hpt374_ide_dma_end;
1229 } else if (hpt_minimum_revision(dev,5)) {
1230 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1231 hwif->ide_dma_end = &hpt374_ide_dma_end;
1232 } else if (hpt_minimum_revision(dev,3)) {
1233 hwif->ide_dma_begin = &hpt370_ide_dma_begin;
1234 hwif->ide_dma_end = &hpt370_ide_dma_end;
1235 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1236 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1237 } else if (hpt_minimum_revision(dev,2))
1238 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1240 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1244 hwif->drives[0].autodma = hwif->autodma;
1245 hwif->drives[1].autodma = hwif->autodma;
1248 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1250 u8 masterdma = 0, slavedma = 0;
1251 u8 dma_new = 0, dma_old = 0;
1252 u8 primary = hwif->channel ? 0x4b : 0x43;
1253 u8 secondary = hwif->channel ? 0x4f : 0x47;
1254 unsigned long flags;
1259 if(pci_get_drvdata(hwif->pci_dev) == NULL)
1261 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1265 dma_old = hwif->INB(dmabase+2);
1267 local_irq_save(flags);
1270 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1271 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1273 if (masterdma & 0x30) dma_new |= 0x20;
1274 if (slavedma & 0x30) dma_new |= 0x40;
1275 if (dma_new != dma_old)
1276 hwif->OUTB(dma_new, dmabase+2);
1278 local_irq_restore(flags);
1280 ide_setup_dma(hwif, dmabase, 8);
1283 static void __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1285 struct pci_dev *findev = NULL;
1287 if (PCI_FUNC(dev->devfn) & 1)
1290 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1291 if ((findev->vendor == dev->vendor) &&
1292 (findev->device == dev->device) &&
1293 ((findev->devfn - dev->devfn) == 1) &&
1294 (PCI_FUNC(findev->devfn) & 1)) {
1295 if (findev->irq != dev->irq) {
1296 /* FIXME: we need a core pci_set_interrupt() */
1297 findev->irq = dev->irq;
1298 printk(KERN_WARNING "%s: pci-config space interrupt "
1299 "fixed.\n", d->name);
1301 ide_setup_pci_devices(dev, findev, d);
1305 ide_setup_pci_device(dev, d);
1308 static void __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1310 ide_setup_pci_device(dev, d);
1313 static void __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1315 struct pci_dev *findev = NULL;
1316 u8 pin1 = 0, pin2 = 0;
1317 unsigned int class_rev;
1318 char *chipset_names[] = {"HPT366", "HPT366", "HPT368",
1319 "HPT370", "HPT370A", "HPT372",
1322 if (PCI_FUNC(dev->devfn) & 1)
1325 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1328 if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1332 d->name = chipset_names[class_rev];
1338 case 3: ide_setup_pci_device(dev, d);
1345 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1346 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1347 if ((findev->vendor == dev->vendor) &&
1348 (findev->device == dev->device) &&
1349 ((findev->devfn - dev->devfn) == 1) &&
1350 (PCI_FUNC(findev->devfn) & 1)) {
1351 pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1352 if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1353 d->bootable = ON_BOARD;
1354 printk("%s: onboard version of chipset, "
1355 "pin1=%d pin2=%d\n", d->name,
1358 ide_setup_pci_devices(dev, findev, d);
1362 ide_setup_pci_device(dev, d);
1367 * hpt366_init_one - called when an HPT366 is found
1368 * @dev: the hpt366 device
1369 * @id: the matching pci id
1371 * Called when the PCI registration layer (or the IDE initialization)
1372 * finds a device matching our IDE device tables.
1375 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1377 ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1379 d->init_setup(dev, d);
1383 static struct pci_device_id hpt366_pci_tbl[] = {
1384 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1385 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1386 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1387 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1388 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1389 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1392 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1394 static struct pci_driver driver = {
1395 .name = "HPT366_IDE",
1396 .id_table = hpt366_pci_tbl,
1397 .probe = hpt366_init_one,
1400 static int hpt366_ide_init(void)
1402 return ide_pci_register_driver(&driver);
1405 module_init(hpt366_ide_init);
1407 MODULE_AUTHOR("Andre Hedrick");
1408 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1409 MODULE_LICENSE("GPL");