3 * BRIEF MODULE DESCRIPTION
4 * IT8172 IDE controller support
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * stevel@mvista.com or source@mvista.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/config.h>
32 #include <linux/module.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/ioport.h>
36 #include <linux/pci.h>
37 #include <linux/hdreg.h>
38 #include <linux/ide.h>
39 #include <linux/delay.h>
40 #include <linux/init.h>
43 #include <asm/it8172/it8172_int.h>
50 static u8 it8172_ratemask (ide_drive_t *drive)
55 static void it8172_tune_drive (ide_drive_t *drive, u8 pio)
57 ide_hwif_t *hwif = HWIF(drive);
58 struct pci_dev *dev = hwif->pci_dev;
59 int is_slave = (hwif->drives[1] == drive);
64 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
65 spin_lock_irqsave(&ide_lock, flags);
66 pci_read_config_word(dev, 0x40, &drive_enables);
67 pci_read_config_dword(dev, 0x44, &drive_timing);
70 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
71 * are being left at the default values of 8 PCI clocks (242 nsec
72 * for a 33 MHz clock). These can be safely shortened at higher
73 * PIO modes. The DIOR/DIOW pulse width and recovery times only
74 * apply to PIO modes, not to the DMA modes.
78 * Enable port 0x44. The IT8172G spec is confused; it calls
79 * this register the "Slave IDE Timing Register", but in fact,
80 * it controls timing for both master and slave drives.
82 drive_enables |= 0x4000;
85 drive_enables &= 0xc006;
87 /* enable prefetch and IORDY sample-point */
88 drive_enables |= 0x0060;
90 drive_enables &= 0xc060;
92 /* enable prefetch and IORDY sample-point */
93 drive_enables |= 0x0006;
96 pci_write_config_word(dev, 0x40, drive_enables);
97 spin_unlock_irqrestore(&ide_lock, flags)
100 static u8 it8172_dma_2_pio (u8 xfer_rate)
129 static int it8172_tune_chipset (ide_drive_t *drive, u8 xferspeed)
131 ide_hwif_t *hwif = HWIF(drive);
132 struct pci_dev *dev = hwif->pci_dev;
133 u8 speed = ide_rate_filter(it8172_ratemask(drive), xferspeed);
134 int a_speed = 3 << (drive->dn * 4);
135 int u_flag = 1 << drive->dn;
139 pci_read_config_byte(dev, 0x48, ®48);
140 pci_read_config_byte(dev, 0x4a, ®4a);
143 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
144 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
145 * transfers on some drives, even though both numbers meet the minimum
146 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
147 * So the faster times are just commented out here. The good news is
148 * that the slower cycle time has very little affect on transfer
154 case XFER_UDMA_2: //u_speed = 2 << (drive->dn * 4); break;
157 case XFER_UDMA_1: //u_speed = 1 << (drive->dn * 4); break;
158 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
162 case XFER_SW_DMA_2: break;
166 case XFER_PIO_0: break;
170 if (speed >= XFER_UDMA_0) {
171 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
173 pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
175 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
176 pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
179 it8172_tune_drive(drive, it8172_dma_2_pio(speed));
180 return (ide_config_drive_speed(drive, speed));
183 static int it8172_config_chipset_for_dma (ide_drive_t *drive)
185 u8 speed = ide_dma_speed(drive, it8172_ratemask(drive));
188 u8 tspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
189 speed = it8172_dma_2_pio(XFER_PIO_0 + tspeed);
192 (void) it8172_tune_chipset(drive, speed);
193 return ide_dma_enable(drive);
196 static int it8172_config_drive_xfer_rate (ide_drive_t *drive)
198 ide_hwif_t *hwif = HWIF(drive);
199 struct hd_driveid *id = drive->id;
201 drive->init_speed = 0;
203 if (id && (id->capability & 1) && drive->autodma) {
204 /* Consult the list of known "bad" drives */
205 if (__ide_dma_bad_drive(drive))
207 if (id->field_valid & 4) {
208 if (id->dma_ultra & hwif->ultra_mask) {
209 /* Force if Capable UltraDMA */
210 int dma = it8172_config_chipset_for_dma(drive);
211 if ((id->field_valid & 2) && !dma)
214 } else if (id->field_valid & 2) {
216 if ((id->dma_mword & hwif->mwdma_mask) ||
217 (id->dma_1word & hwif->swdma_mask)) {
218 /* Force if Capable regular DMA modes */
219 if (!it8172_config_chipset_for_dma(drive))
222 } else if (__ide_dma_good_drive(drive) &&
223 (id->eide_dma_time < 150)) {
224 /* Consult the list of known "good" drives */
225 if (!it8172_config_chipset_for_dma(drive))
230 return hwif->ide_dma_on(drive);
231 } else if ((id->capability & 8) || (id->field_valid & 2)) {
234 it8172_tune_drive(drive, 5);
235 return hwif->ide_dma_off_quietly(drive);
237 /* IORDY not supported */
241 static unsigned int __init init_chipset_it8172 (struct pci_dev *dev, const char *name)
243 unsigned char progif;
246 * Place both IDE interfaces into PCI "native" mode
248 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
249 pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
251 return IT8172_IDE_IRQ;
255 static void __init init_hwif_it8172 (ide_hwif_t *hwif)
257 struct pci_dev* dev = hwif->pci_dev;
258 unsigned long cmdBase, ctrlBase;
261 hwif->tuneproc = &it8172_tune_drive;
262 hwif->speedproc = &it8172_tune_chipset;
264 cmdBase = dev->resource[0].start;
265 ctrlBase = dev->resource[1].start;
267 ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase | 2, NULL);
268 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
271 if (!hwif->dma_base) {
272 hwif->drives[0].autotune = 1;
273 hwif->drives[1].autotune = 1;
278 hwif->ultra_mask = 0x07;
279 hwif->mwdma_mask = 0x06;
280 hwif->swdma_mask = 0x04;
282 hwif->ide_dma_check = &it8172_config_drive_xfer_rate;
285 hwif->drives[0].autodma = hwif->autodma;
286 hwif->drives[1].autodma = hwif->autodma;
289 static int __devinit it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
291 if ((!(PCI_FUNC(dev->devfn) & 1) ||
292 (!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
293 return -EAGAIN; /* IT8172 is more than only a IDE controller */
294 ide_setup_pci_device(dev, &it8172_chipsets[id->driver_data]);
298 static struct pci_device_id it8172_pci_tbl[] = {
299 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
302 MODULE_DEVICE_TABLE(pci, it8172_pci_tbl);
304 static struct pci_driver driver = {
305 .name = "IT8172_IDE",
306 .id_table = it8172_pci_tbl,
307 .probe = it8172_init_one,
310 static int it8172_ide_init(void)
312 return ide_pci_register_driver(&driver);
315 module_init(it8172_ide_init);
317 MODULE_AUTHOR("SteveL@mvista.com");
318 MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");
319 MODULE_LICENSE("GPL");