2 * linux/drivers/ide/pci/it8212.c Version 0.07 November 2004
4 * Copyright (C) 2004 Red Hat <alan@redhat.com>
6 * May be copied or modified under the terms of the GNU General Public License
7 * Based in part on the ITE vendor provided SCSI driver.
9 * Documentation available from
10 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
11 * Some other documents are NDA.
13 * The ITE8212 isn't exactly a standard IDE controller. It has two
14 * modes. In pass through mode then it is an IDE controller. In its smart
15 * mode its actually quite a capable hardware raid controller disguised
16 * as an IDE controller. Smart mode only understands DMA read/write and
17 * identify, none of the fancier commands apply.
20 * o Rev 0x10 also requires master/slave hold the same DMA timings and
21 * cannot do ATAPI MWDMA.
22 * o The identify data for raid volumes lacks CHS info (technically ok)
23 * but also fails to set the LBA28 and other bits. We fix these in
24 * the IDE probe quirk code.
25 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
26 * raid then the controller firmware dies
27 * o Smart mode without RAID doesn't clear all the necessary identify
28 * bits to reduce the command set to the one used
30 * This has a few impacts on the driver
31 * - In pass through mode we do all the work you would expect
32 * - In smart mode the clocking set up is done by the controller generally
33 * but we must watch the other limits and filter.
34 * - There are a few extra vendor commands that actually talk to the
35 * controller but only work PIO with no IRQ.
37 * Vendor areas of the identify block in smart mode are used for the
38 * timing and policy set up. Each HDD in raid mode also has a serial
39 * block on the disk. The hardware extra commands are get/set chip status,
40 * rebuild, get rebuild status.
42 * In Linux the driver supports pass through mode as if the device was
43 * just another IDE controller. If the smart mode is running then
44 * volumes are managed by the controller firmware and each IDE "disk"
45 * is a raid volume. Even more cute - the controller can do automated
46 * hotplug and rebuild.
48 * The pass through controller itself is a little demented. It has a
49 * flaw that it has a single set of PIO/MWDMA timings per channel so
50 * non UDMA devices restrict each others performance. It also has a
51 * single clock source per channel so mixed UDMA100/133 performance
52 * isn't perfect and we have to pick a clock. Thankfully none of this
53 * matters in smart mode. ATAPI DMA is not currently supported.
55 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
58 * - ATAPI UDMA is ok but not MWDMA it seems
59 * - RAID configuration ioctls
62 #include <linux/config.h>
63 #include <linux/types.h>
64 #include <linux/module.h>
65 #include <linux/pci.h>
66 #include <linux/delay.h>
67 #include <linux/hdreg.h>
68 #include <linux/ide.h>
69 #include <linux/init.h>
75 unsigned int smart:1, /* Are we in smart raid mode */
76 timing10:1; /* Rev 0x10 */
77 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
78 u8 want[2][2]; /* Mode/Pri log for master slave */
79 /* We need these for switching the clock when DMA goes on/off
80 The high byte is the 66Mhz timing */
81 u16 pio[2]; /* Cached PIO values */
82 u16 mwdma[2]; /* Cached MWDMA values */
83 u16 udma[2]; /* Cached UDMA values (per drive) */
94 * We allow users to force the card into non raid mode without
95 * flashing the alternative BIOS. This is also neccessary right now
96 * for embedded platforms that cannot run a PC BIOS but are using this
100 static int it8212_noraid;
103 * it8212_program - program the PIO/MWDMA registers
104 * @drive: drive to tune
106 * Program the PIO/MWDMA timing for this channel according to the
110 static void it8212_program(ide_drive_t *drive, u16 timing)
112 ide_hwif_t *hwif = HWIF(drive);
113 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
114 int channel = hwif->channel;
117 /* Program PIO/MWDMA timing bits */
118 if(itdev->clock_mode == ATA_66)
121 conf = timing & 0xFF;
122 pci_write_config_byte(hwif->pci_dev, 0x54 + 4 * channel, conf);
126 * it8212_program_udma - program the UDMA registers
127 * @drive: drive to tune
129 * Program the UDMA timing for this drive according to the
133 static void it8212_program_udma(ide_drive_t *drive, u16 timing)
135 ide_hwif_t *hwif = HWIF(drive);
136 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
137 int channel = hwif->channel;
138 int unit = drive->select.b.unit;
141 /* Program UDMA timing bits */
142 if(itdev->clock_mode == ATA_66)
145 conf = timing & 0xFF;
146 if(itdev->timing10 == 0)
147 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + unit, conf);
149 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel, conf);
150 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + 1, conf);
156 * it8212_clock_strategy
157 * @hwif: hardware interface
159 * Select between the 50 and 66Mhz base clocks to get the best
160 * results for this interface.
163 static void it8212_clock_strategy(ide_drive_t *drive)
165 ide_hwif_t *hwif = HWIF(drive);
166 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
168 u8 unit = drive->select.b.unit;
169 ide_drive_t *pair = &hwif->drives[1-unit];
175 if(itdev->want[0][0] > itdev->want[1][0]) {
176 clock = itdev->want[0][1];
177 altclock = itdev->want[1][1];
179 clock = itdev->want[1][1];
180 altclock = itdev->want[0][1];
183 /* Master doesn't care does the slave ? */
187 /* Nobody cares - keep the same clock */
191 if(clock == itdev->clock_mode)
194 /* Load this into the controller ? */
196 itdev->clock_mode = ATA_66;
198 itdev->clock_mode = ATA_50;
201 pci_read_config_byte(hwif->pci_dev, 0x50, &v);
202 v &= ~(1 << (1 + hwif->channel));
203 v |= sel << (1 + hwif->channel);
204 pci_write_config_byte(hwif->pci_dev, 0x50, v);
207 * Reprogram the UDMA/PIO of the pair drive for the switch
208 * MWDMA will be dealt with by the dma switcher
210 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
211 it8212_program_udma(pair, itdev->udma[1-unit]);
212 it8212_program(pair, itdev->pio[1-unit]);
215 * Reprogram the UDMA/PIO of our drive for the switch.
216 * MWDMA will be dealt with by the dma switcher
218 if(itdev->udma[unit] != UDMA_OFF) {
219 it8212_program_udma(drive, itdev->udma[unit]);
220 it8212_program(drive, itdev->pio[unit]);
225 * it8212_ratemask - Compute available modes
228 * Compute the available speeds for the devices on the interface. This
229 * is all modes to ATA133 clipped by drive cable setup.
232 static byte it8212_ratemask (ide_drive_t *drive)
235 if (!eighty_ninty_three(drive))
236 mode = min(mode, (u8)1);
241 * it8212_tuneproc - tune a drive
242 * @drive: drive to tune
243 * @mode_wanted: the target operating mode
245 * Load the timing settings for this device mode into the
246 * controller. By the time we are called the mode has been
247 * modified as neccessary to handle the absence of seperate
248 * master/slave timers for MWDMA/PIO.
250 * This code is only used in pass through mode.
253 static void it8212_tuneproc (ide_drive_t *drive, byte mode_wanted)
255 ide_hwif_t *hwif = HWIF(drive);
256 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
257 int unit = drive->select.b.unit;
259 /* Spec says 89 ref driver uses 88 */
260 static u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
261 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
266 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
267 itdev->want[unit][1] = pio_want[mode_wanted];
268 itdev->want[unit][0] = 1; /* PIO is lowest priority */
269 itdev->pio[unit] = pio[mode_wanted];
270 it8212_clock_strategy(drive);
271 it8212_program(drive, itdev->pio[unit]);
275 * it8212_tune_mwdma - tune a channel for MWDMA
276 * @drive: drive to set up
277 * @mode_wanted: the target operating mode
279 * Load the timing settings for this device mode into the
280 * controller when doing MWDMA in pass through mode. The caller
281 * must manage the whole lack of per device MWDMA/PIO timings and
282 * the shared MWDMA/PIO timing register.
285 static void it8212_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
287 ide_hwif_t *hwif = HWIF(drive);
288 struct it8212_dev *itdev = (void *)ide_get_hwifdata(hwif);
289 int unit = drive->select.b.unit;
290 int channel = hwif->channel;
293 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
294 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
296 itdev->want[unit][1] = mwdma_want[mode_wanted];
297 itdev->want[unit][0] = 2; /* MWDMA is low priority */
298 itdev->mwdma[unit] = dma[mode_wanted];
299 itdev->udma[unit] = UDMA_OFF;
301 /* UDMA bits off - Revision 0x10 do them in pairs */
302 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
304 conf |= channel ? 0x60: 0x18;
306 conf |= 1 << (3 + 2 * channel + unit);
307 pci_write_config_byte(hwif->pci_dev, 0x50, conf);
309 it8212_clock_strategy(drive);
310 /* FIXME: do we need to program this ? */
311 /* it8212_program(drive, itdev->mwdma[unit]); */
315 * it8212_tune_udma - tune a channel for UDMA
316 * @drive: drive to set up
317 * @mode_wanted: the target operating mode
319 * Load the timing settings for this device mode into the
320 * controller when doing UDMA modes in pass through.
323 static void it8212_tune_udma (ide_drive_t *drive, byte mode_wanted)
325 ide_hwif_t *hwif = HWIF(drive);
326 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
327 int unit = drive->select.b.unit;
328 int channel = hwif->channel;
331 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
332 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
334 itdev->want[unit][1] = udma_want[mode_wanted];
335 itdev->want[unit][0] = 3; /* UDMA is high priority */
336 itdev->mwdma[unit] = MWDMA_OFF;
337 itdev->udma[unit] = udma[mode_wanted];
339 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
341 /* UDMA on. Again revision 0x10 must do the pair */
342 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
344 conf &= channel ? 0x9F: 0xE7;
346 conf &= ~ (1 << (3 + 2 * channel + unit));
347 pci_write_config_byte(hwif->pci_dev, 0x50, conf);
349 it8212_clock_strategy(drive);
350 it8212_program_udma(drive, itdev->udma[unit]);
355 * config_it8212_chipset_for_pio - set drive timings
356 * @drive: drive to tune
359 * Compute the best pio mode we can for a given device. We must
360 * pick a speed that does not cause problems with the other device
364 static void config_it8212_chipset_for_pio (ide_drive_t *drive, byte set_speed)
366 u8 unit = drive->select.b.unit;
367 ide_hwif_t *hwif = HWIF(drive);
368 ide_drive_t *pair = &hwif->drives[1-unit];
369 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
372 /* We have to deal with this mess in pairs */
374 pair_pio = ide_get_best_pio_mode(pair, 4, 5, NULL);
375 /* Trim PIO to the slowest of the master/slave */
376 if(pair_pio < set_pio)
379 it8212_tuneproc(drive, set_pio);
380 speed = XFER_PIO_0 + set_pio;
381 /* XXX - We trim to the lowest of the pair so the other drive
382 will always be fine at this point until we do hotplug passthru */
385 (void) ide_config_drive_speed(drive, speed);
388 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
390 config_it8212_chipset_for_pio(drive, set_speed);
394 * it8212_dma_read - DMA hook
395 * @drive: drive for DMA
397 * The IT8212 has a single timing register for MWDMA and for PIO
398 * operations. As we flip back and forth we have to reload the
399 * clock. In addition the rev 0x10 device only works if the same
400 * timing value is loaded into the master and slave UDMA clock
401 * so we must also reload that.
403 * FIXME: we could figure out in advance if we need to do reloads
406 static int it8212_dma_begin(ide_drive_t *drive)
408 ide_hwif_t *hwif = HWIF(drive);
409 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
410 int unit = drive->select.b.unit;
411 if(itdev->mwdma[unit] != MWDMA_OFF)
412 it8212_program(drive, itdev->mwdma[unit]);
413 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
414 it8212_program_udma(drive, itdev->udma[unit]);
415 return __ide_dma_begin(drive);
419 * it8212_dma_write - DMA hook
420 * @drive: drive for DMA stop
422 * The IT8212 has a single timing register for MWDMA and for PIO
423 * operations. As we flip back and forth we have to reload the
427 static int it8212_dma_end(ide_drive_t *drive)
429 ide_hwif_t *hwif = HWIF(drive);
430 int unit = drive->select.b.unit;
431 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
432 int ret = __ide_dma_end(drive);
433 if(itdev->mwdma[unit] != MWDMA_OFF)
434 it8212_program(drive, itdev->pio[unit]);
440 * it8212_tune_chipset - set controller timings
441 * @drive: Drive to set up
442 * @xferspeed: speed we want to achieve
444 * Tune the ITE chipset for the desired mode. If we can't achieve
445 * the desired mode then tune for a lower one, but ultimately
446 * make the thing work.
449 static int it8212_tune_chipset (ide_drive_t *drive, byte xferspeed)
452 ide_hwif_t *hwif = HWIF(drive);
453 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
454 u8 speed = ide_rate_filter(it8212_ratemask(drive), xferspeed);
462 it8212_tuneproc(drive, (speed - XFER_PIO_0));
464 /* MWDMA tuning is really hard because our MWDMA and PIO
465 timings are kept in the same place. We can switch in the
466 host dma on/off callbacks */
471 it8212_tune_mwdma(drive, (speed - XFER_MW_DMA_0));
481 it8212_tune_udma(drive, (speed - XFER_UDMA_0));
487 * In smart mode the clocking is done by the host controller
488 * snooping the mode we picked. The rest of it is not our problem
490 return (ide_config_drive_speed(drive, speed));
494 * config_chipset_for_dma - configure for DMA
495 * @drive: drive to configure
497 * Called by the IDE layer when it wants the timings set up.
500 static int config_chipset_for_dma (ide_drive_t *drive)
502 u8 speed = ide_dma_speed(drive, it8212_ratemask(drive));
504 config_chipset_for_pio(drive, !speed);
509 if (ide_set_xfer_rate(drive, speed))
512 if (!drive->init_speed)
513 drive->init_speed = speed;
515 return ide_dma_enable(drive);
519 * it8212_configure_drive_for_dma - set up for DMA transfers
520 * @drive: drive we are going to set up
522 * Set up the drive for DMA, tune the controller and drive as
523 * required. If the drive isn't suitable for DMA or we hit
524 * other problems then we will drop down to PIO and set up
528 static int it8212_config_drive_for_dma (ide_drive_t *drive)
530 ide_hwif_t *hwif = HWIF(drive);
531 struct hd_driveid *id = drive->id;
533 if ((id->capability & 1) != 0 && drive->autodma) {
534 /* Consult the list of known "bad" drives */
535 if (__ide_dma_bad_drive(drive))
538 if ((id->field_valid & 4) && it8212_ratemask(drive)) {
539 if (id->dma_ultra & hwif->ultra_mask) {
540 /* Force if Capable UltraDMA */
541 int dma = config_chipset_for_dma(drive);
542 if ((id->field_valid & 2) && !dma)
545 } else if (id->field_valid & 2) {
547 if ((id->dma_mword & hwif->mwdma_mask) ||
548 (id->dma_1word & hwif->swdma_mask)) {
549 /* Force if Capable regular DMA modes */
550 if (!config_chipset_for_dma(drive))
553 } else if (__ide_dma_good_drive(drive) &&
554 (id->eide_dma_time < 150)) {
555 /* Consult the list of known "good" drives */
556 if (!config_chipset_for_dma(drive))
561 return hwif->ide_dma_on(drive);
562 } else if ((id->capability & 8) || (id->field_valid & 2)) {
565 config_chipset_for_pio(drive, 1);
566 return hwif->ide_dma_off_quietly(drive);
568 /* IORDY not supported */
573 * init_chipset_it8212 - set up an ITE device
577 * PCI chipset level initialize. Nothing to do.
580 static unsigned int __devinit init_chipset_it8212(struct pci_dev *dev, const char *name)
586 * ata66_it8212 - check for 80 pin cable
587 * @hwif: interface to check
589 * Check for the presence of an ATA66 capable cable on the
590 * interface. Problematic as it seems some cards don't have
591 * the needed logic onboard.
594 static unsigned int __devinit ata66_it8212(ide_hwif_t *hwif)
596 /* The reference driver also only does disk side */
601 * it8212_fixup - post init callback
604 * This callback is run after the drives have been probed but
605 * before anything gets attached. It allows drivers to do any
606 * final tuning that is needed, or fixups to work around bugs.
609 static void __devinit it8212_fixups(ide_hwif_t *hwif)
611 struct it8212_dev *itdev = ide_get_hwifdata(hwif);
616 * If we are in pass through mode then not much
617 * needs to be done, but we do bother to clear the
618 * IRQ mask in case the drives are PIO (eg rev 0x10)
621 for (i = 0; i < 2; i++) {
622 ide_drive_t *drive = &hwif->drives[i];
629 * Perform fixups on smart mode. We need to "lose" some
630 * capabilities the firmware lacks but does not filter, and
631 * also patch up some capability bits that it forgets to set
635 for(i = 0; i < 2; i++) {
636 ide_drive_t *drive = &hwif->drives[i];
637 struct hd_driveid *id;
643 idbits = (u16 *)drive->id;
645 /* Check for RAID v native */
646 if(strstr(id->model, "Integrated Technology Express")) {
647 /* In raid mode the ident block is slightly buggy */
648 id->capability |= 3; /* LBA28, DMA */
649 id->command_set_2 |= 0x0400; /* LBA48 valid */
650 id->cfs_enable_2 |= 0x0400; /* LBA48 on */
651 /* Reporting logic */
652 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
654 idbits[147] ? "Bootable ":"",
657 printk("(%dK stripe)", idbits[146]);
660 /* Non RAID volume. Fixups to stop the core code
661 doing unsupported things */
662 id->field_valid &= 1;
664 id->command_set_1 = 0;
665 id->command_set_2 &= 0xC400;
667 id->cfs_enable_1 = 0;
668 id->cfs_enable_2 &= 0xC400;
669 id->csf_default &= 0xC000;
674 printk(KERN_INFO "%s: Performing identify fixups.\n",
682 * init_hwif_it8212 - set up hwif structs
683 * @hwif: interface to set up
685 * We do the basic set up of the interface structure. The IT8212
686 * requires several custom handlers so we override the default
687 * ide DMA handlers appropriately
690 static void __devinit init_hwif_it8212(ide_hwif_t *hwif)
692 struct it8212_dev *idev = kmalloc(sizeof(struct it8212_dev), GFP_KERNEL);
694 static char *mode[2] = { "pass through", "smart" };
697 printk(KERN_ERR "it8212: out of memory, falling back to legacy behaviour.\n");
700 memset(idev, 0, sizeof(struct it8212_dev));
701 ide_set_hwifdata(hwif, idev);
703 /* Force the card into bypass mode if so requested */
705 printk(KERN_INFO "it8212: forcing bypass mode.\n");
707 /* Reset local CPU, and set BIOS not ready */
708 pci_write_config_byte(hwif->pci_dev, 0x5E, 0x01);
710 /* Set to bypass mode, and reset PCI bus */
711 pci_write_config_byte(hwif->pci_dev, 0x50, 0x00);
713 pci_write_config_word(hwif->pci_dev, PCI_COMMAND,
714 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
715 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
717 pci_write_config_word(hwif->pci_dev, 0x40, 0xA0F3);
719 pci_write_config_dword(hwif->pci_dev,0x4C, 0x02040204);
720 pci_write_config_byte(hwif->pci_dev, 0x42, 0x36);
721 pci_write_config_byte(hwif->pci_dev, PCI_LATENCY_TIMER, 0);
724 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
728 /* Long I/O's although allowed in LBA48 space cause the
729 onboard firmware to enter the twighlight zone */
733 if(hwif->channel == 0)
734 printk(KERN_INFO "it8212: controller in %s mode.\n",
737 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
738 if (conf & (1 << (1 + hwif->channel)))
739 idev->clock_mode = ATA_50;
741 idev->clock_mode = ATA_66;
743 idev->want[0][1] = ATA_ANY;
744 idev->want[1][1] = ATA_ANY;
747 * Not in the docs but according to the reference driver
748 * this is neccessary.
751 pci_read_config_byte(hwif->pci_dev, 0x08, &conf);
756 printk(KERN_WARNING "it8212: Revision 0x10, workarounds activated.\n");
759 hwif->speedproc = &it8212_tune_chipset;
760 hwif->tuneproc = &it8212_tuneproc;
762 /* MWDMA/PIO clock switching for pass through mode */
764 hwif->ide_dma_begin = &it8212_dma_begin;
765 hwif->ide_dma_end = &it8212_dma_end;
771 hwif->ultra_mask = 0x7f;
772 hwif->mwdma_mask = 0x07;
773 hwif->swdma_mask = 0x07;
775 hwif->ide_dma_check = &it8212_config_drive_for_dma;
776 if (!(hwif->udma_four))
777 hwif->udma_four = ata66_it8212(hwif);
780 * The BIOS often doesn't set up DMA on this controller
781 * so we always do it.
785 hwif->drives[0].autodma = hwif->autodma;
786 hwif->drives[1].autodma = hwif->autodma;
791 hwif->drives[0].autotune = 1;
792 hwif->drives[1].autotune = 1;
796 #define DECLARE_ITE_DEV(name_str) \
799 .init_chipset = init_chipset_it8212, \
800 .init_hwif = init_hwif_it8212, \
802 .autodma = AUTODMA, \
803 .bootable = ON_BOARD, \
804 .fixup = it8212_fixups \
807 static ide_pci_device_t it8212_chipsets[] __devinitdata = {
808 /* 0 */ DECLARE_ITE_DEV("IT8212"),
812 * it8212_init_one - pci layer discovery entry
814 * @id: ident table entry
816 * Called by the PCI code when it finds an ITE8212 controller.
817 * We then use the IDE PCI generic helper to do most of the work.
820 static int __devinit it8212_init_one(struct pci_dev *dev, const struct pci_device_id *id)
822 ide_setup_pci_device(dev, &it8212_chipsets[id->driver_data]);
826 static struct pci_device_id it8212_pci_tbl[] = {
827 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
831 MODULE_DEVICE_TABLE(pci, it8212_pci_tbl);
833 static struct pci_driver driver = {
834 .name = "ITE8212 IDE",
835 .id_table = it8212_pci_tbl,
836 .probe = it8212_init_one,
839 static int __init it8212_ide_init(void)
841 return ide_pci_register_driver(&driver);
844 module_init(it8212_ide_init);
846 module_param_named(noraid, it8212_noraid, int, S_IRUGO);
847 MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode");
849 MODULE_AUTHOR("Alan Cox");
850 MODULE_DESCRIPTION("PCI driver module for the ITE 8212");
851 MODULE_LICENSE("GPL");