drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *
   6  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   7  *  compiled into the kernel if you have more than one card installed.
   8  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
   9  *  safe chipset tuning, including this support is harmless
  10  *
  11  *  Promise Ultra66 cards with BIOS v1.11 this
  12  *  compiled into the kernel if you have more than one card installed.
  13  *
  14  *  Promise Ultra100 cards.
  15  *
  16  *  The latest chipset code will support the following ::
  17  *  Three Ultra33 controllers and 12 drives.
  18  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  19  *  The 8/4 ratio is a BIOS code limit by promise.
  20  *
  21  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  22  *
  23  */
  24
  25 /*
  26  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  27  *  Author: Frank Tiernan (frankt@promise.com)
  28  *  Released under terms of General Public License
  29  */
  30
  31 #include <linux/config.h>
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/timer.h>
  37 #include <linux/mm.h>
  38 #include <linux/ioport.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/ide.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48
  49 #include "pdc202xx_old.h"
  50
  51 #define PDC202_DEBUG_CABLE      0
  52
  53 #if 0
  54         unsigned long bibma  = pci_resource_start(dev, 4);
  55         u8 hi = 0, lo = 0;
  56
  57         u8 sc1c = inb_p((u16)bibma + 0x1c);
  58         u8 sc1e = inb_p((u16)bibma + 0x1e);
  59         u8 sc1f = inb_p((u16)bibma + 0x1f);
  60
  61         p += sprintf(p, "Host Mode                            : %s\n",
  62                 (sc1f & 0x08) ? "Tri-Stated" : "Normal");
  63         p += sprintf(p, "Bus Clocking                         : %s\n",
  64                 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
  65                 ((sc1f & 0x80) == 0x80) ? "66 External" :
  66                 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
  67         p += sprintf(p, "IO pad select                        : %s mA\n",
  68                 ((sc1c & 0x03) == 0x03) ? "10" :
  69                 ((sc1c & 0x02) == 0x02) ? "8" :
  70                 ((sc1c & 0x01) == 0x01) ? "6" :
  71                 ((sc1c & 0x00) == 0x00) ? "4" : "??");
  72         SPLIT_BYTE(sc1e, hi, lo);
  73         p += sprintf(p, "Status Polling Period                : %d\n", hi);
  74         p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
  75 #endif
  76
  77 static u8 pdc202xx_ratemask (ide_drive_t *drive)
  78 {
  79         u8 mode;
  80
  81         switch(HWIF(drive)->pci_dev->device) {
  82                 case PCI_DEVICE_ID_PROMISE_20267:
  83                 case PCI_DEVICE_ID_PROMISE_20265:
  84                         mode = 3;
  85                         break;
  86                 case PCI_DEVICE_ID_PROMISE_20263:
  87                 case PCI_DEVICE_ID_PROMISE_20262:
  88                         mode = 2;
  89                         break;
  90                 case PCI_DEVICE_ID_PROMISE_20246:
  91                         return 1;
  92                 default:
  93                         return 0;
  94         }
  95         if (!eighty_ninty_three(drive))
  96                 mode = min(mode, (u8)1);
  97         return mode;
  98 }
  99
 100 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 101 {
 102         struct hd_driveid *id = drive->id;
 103
 104         if (pdc_quirk_drives == list) {
 105                 while (*list) {
 106                         if (strstr(id->model, *list++)) {
 107                                 return 2;
 108                         }
 109                 }
 110         } else {
 111                 while (*list) {
 112                         if (!strcmp(*list++,id->model)) {
 113                                 return 1;
 114                         }
 115                 }
 116         }
 117         return 0;
 118 }
 119
 120 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 121 {
 122         ide_hwif_t *hwif        = HWIF(drive);
 123         struct pci_dev *dev     = hwif->pci_dev;
 124         u8 drive_pci            = 0x60 + (drive->dn << 2);
 125         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 126
 127         u32                     drive_conf;
 128         u8                      AP, BP, CP, DP;
 129         u8                      TA = 0, TB = 0, TC = 0;
 130
 131         if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
 132                 return -1;
 133
 134         pci_read_config_dword(dev, drive_pci, &drive_conf);
 135         pci_read_config_byte(dev, (drive_pci), &AP);
 136         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 137         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 138         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 139
 140         if (speed < XFER_SW_DMA_0) {
 141                 if ((AP & 0x0F) || (BP & 0x07)) {
 142                         /* clear PIO modes of lower 8421 bits of A Register */
 143                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 144                         pci_read_config_byte(dev, (drive_pci), &AP);
 145
 146                         /* clear PIO modes of lower 421 bits of B Register */
 147                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 148                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 149
 150                         pci_read_config_byte(dev, (drive_pci), &AP);
 151                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 152                 }
 153         } else {
 154                 if ((BP & 0xF0) && (CP & 0x0F)) {
 155                         /* clear DMA modes of upper 842 bits of B Register */
 156                         /* clear PIO forced mode upper 1 bit of B Register */
 157                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 158                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 159
 160                         /* clear DMA modes of lower 8421 bits of C Register */
 161                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 162                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 163                 }
 164         }
 165
 166         pci_read_config_byte(dev, (drive_pci), &AP);
 167         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 168         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 169
 170         switch(speed) {
 171                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 172                 case XFER_UDMA_5:
 173                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 174                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 175                 case XFER_UDMA_3:
 176                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 177                 case XFER_UDMA_0:
 178                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 179                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 180                 case XFER_MW_DMA_0:
 181                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 182                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 183                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 184                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 185                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 186                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 187                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 188                 case XFER_PIO_0:
 189                 default:                TA = 0x09; TB = 0x13; break;
 190         }
 191
 192         if (speed < XFER_SW_DMA_0) {
 193                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 194                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 195         } else {
 196                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 197                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 198         }
 199
 200 #if PDC202XX_DEBUG_DRIVE_INFO
 201         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 202                 drive->name, ide_xfer_verbose(speed),
 203                 drive->dn, drive_conf);
 204                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 205         printk("0x%08x\n", drive_conf);
 206 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 207
 208         return (ide_config_drive_speed(drive, speed));
 209 }
 210
 211
 212 /*   0    1    2    3    4    5    6   7   8
 213  * 960, 480, 390, 300, 240, 180, 120, 90, 60
 214  *           180, 150, 120,  90,  60
 215  * DMA_Speed
 216  * 180, 120,  90,  90,  90,  60,  30
 217  *  11,   5,   4,   3,   2,   1,   0
 218  */
 219 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 220 {
 221         u8 speed = 0;
 222
 223         if (pio == 5) pio = 4;
 224         speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
 225
 226         pdc202xx_tune_chipset(drive, speed);
 227 }
 228
 229 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 230 {
 231         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 232         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 233         return (CIS & mask) ? 1 : 0;
 234 }
 235
 236 /*
 237  * Set the control register to use the 66MHz system
 238  * clock for UDMA 3/4/5 mode operation when necessary.
 239  *
 240  * It may also be possible to leave the 66MHz clock on
 241  * and readjust the timing parameters.
 242  */
 243 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 244 {
 245         unsigned long clock_reg = hwif->dma_master + 0x11;
 246         u8 clock = hwif->INB(clock_reg);
 247
 248         hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 249 }
 250
 251 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 252 {
 253         unsigned long clock_reg = hwif->dma_master + 0x11;
 254         u8 clock = hwif->INB(clock_reg);
 255
 256         hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 257 }
 258
 259 static int config_chipset_for_dma (ide_drive_t *drive)
 260 {
 261         struct hd_driveid *id   = drive->id;
 262         ide_hwif_t *hwif        = HWIF(drive);
 263         struct pci_dev *dev     = hwif->pci_dev;
 264         u32 drive_conf          = 0;
 265         u8 drive_pci            = 0x60 + (drive->dn << 2);
 266         u8 test1 = 0, test2 = 0, speed = -1;
 267         u8 AP = 0, cable = 0;
 268
 269         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 270                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 271
 272         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 273                 cable = pdc202xx_old_cable_detect(hwif);
 274         else
 275                 ultra_66 = 0;
 276
 277         if (ultra_66 && cable) {
 278                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 279                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 280         }
 281
 282         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 283                 pdc_old_disable_66MHz_clock(drive->hwif);
 284
 285         drive_pci = 0x60 + (drive->dn << 2);
 286         pci_read_config_dword(dev, drive_pci, &drive_conf);
 287         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 288                 goto chipset_is_set;
 289
 290         pci_read_config_byte(dev, drive_pci, &test1);
 291         if (!(test1 & SYNC_ERRDY_EN)) {
 292                 if (drive->select.b.unit & 0x01) {
 293                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 294                         if ((test2 & SYNC_ERRDY_EN) &&
 295                             !(test1 & SYNC_ERRDY_EN)) {
 296                                 pci_write_config_byte(dev, drive_pci,
 297                                         test1|SYNC_ERRDY_EN);
 298                         }
 299                 } else {
 300                         pci_write_config_byte(dev, drive_pci,
 301                                 test1|SYNC_ERRDY_EN);
 302                 }
 303         }
 304
 305 chipset_is_set:
 306
 307         if (drive->media == ide_disk) {
 308                 pci_read_config_byte(dev, (drive_pci), &AP);
 309                 if (id->capability & 4) /* IORDY_EN */
 310                         pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 311                 pci_read_config_byte(dev, (drive_pci), &AP);
 312                 if (drive->media == ide_disk)   /* PREFETCH_EN */
 313                         pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 314         }
 315
 316         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 317
 318         if (!(speed)) {
 319                 /* restore original pci-config space */
 320                 pci_write_config_dword(dev, drive_pci, drive_conf);
 321                 hwif->tuneproc(drive, 5);
 322                 return 0;
 323         }
 324
 325         (void) hwif->speedproc(drive, speed);
 326         return ide_dma_enable(drive);
 327 }
 328
 329 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 330 {
 331         ide_hwif_t *hwif        = HWIF(drive);
 332         struct hd_driveid *id   = drive->id;
 333
 334         drive->init_speed = 0;
 335
 336         if (id && (id->capability & 1) && drive->autodma) {
 337
 338                 if (ide_use_dma(drive)) {
 339                         if (config_chipset_for_dma(drive))
 340                                 return hwif->ide_dma_on(drive);
 341                 }
 342
 343                 goto fast_ata_pio;
 344
 345         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 346 fast_ata_pio:
 347                 hwif->tuneproc(drive, 5);
 348                 return hwif->ide_dma_off_quietly(drive);
 349         }
 350         /* IORDY not supported */
 351         return 0;
 352 }
 353
 354 static int pdc202xx_quirkproc (ide_drive_t *drive)
 355 {
 356         return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
 357 }
 358
 359 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 360 {
 361         if (drive->current_speed > XFER_UDMA_2)
 362                 pdc_old_enable_66MHz_clock(drive->hwif);
 363         if (drive->addressing == 1) {
 364                 struct request *rq      = HWGROUP(drive)->rq;
 365                 ide_hwif_t *hwif        = HWIF(drive);
 366 //              struct pci_dev *dev     = hwif->pci_dev;
 367 //              unsgned long high_16    = pci_resource_start(dev, 4);
 368                 unsigned long high_16   = hwif->dma_master;
 369                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 370                 u32 word_count  = 0;
 371                 u8 clock = hwif->INB(high_16 + 0x11);
 372
 373                 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
 374                 word_count = (rq->nr_sectors << 8);
 375                 word_count = (rq_data_dir(rq) == READ) ?
 376                                         word_count | 0x05000000 :
 377                                         word_count | 0x06000000;
 378                 hwif->OUTL(word_count, atapi_reg);
 379         }
 380         ide_dma_start(drive);
 381 }
 382
 383 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 384 {
 385         if (drive->addressing == 1) {
 386                 ide_hwif_t *hwif        = HWIF(drive);
 387 //              unsigned long high_16   = pci_resource_start(hwif->pci_dev, 4);
 388                 unsigned long high_16   = hwif->dma_master;
 389                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 390                 u8 clock                = 0;
 391
 392                 hwif->OUTL(0, atapi_reg); /* zero out extra */
 393                 clock = hwif->INB(high_16 + 0x11);
 394                 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
 395         }
 396         if (drive->current_speed > XFER_UDMA_2)
 397                 pdc_old_disable_66MHz_clock(drive->hwif);
 398         return __ide_dma_end(drive);
 399 }
 400
 401 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 402 {
 403         ide_hwif_t *hwif        = HWIF(drive);
 404 //      struct pci_dev *dev     = hwif->pci_dev;
 405 //      unsigned long high_16   = pci_resource_start(dev, 4);
 406         unsigned long high_16   = hwif->dma_master;
 407         u8 dma_stat             = hwif->INB(hwif->dma_status);
 408         u8 sc1d                 = hwif->INB((high_16 + 0x001d));
 409
 410         if (hwif->channel) {
 411                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 412                 if ((sc1d & 0x50) == 0x50)
 413                         goto somebody_else;
 414                 else if ((sc1d & 0x40) == 0x40)
 415                         return (dma_stat & 4) == 4;
 416         } else {
 417                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 418                 if ((sc1d & 0x05) == 0x05)
 419                         goto somebody_else;
 420                 else if ((sc1d & 0x04) == 0x04)
 421                         return (dma_stat & 4) == 4;
 422         }
 423 somebody_else:
 424         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 425 }
 426
 427 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 428 {
 429         if (HWIF(drive)->resetproc != NULL)
 430                 HWIF(drive)->resetproc(drive);
 431         return __ide_dma_lostirq(drive);
 432 }
 433
 434 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 435 {
 436         if (HWIF(drive)->resetproc != NULL)
 437                 HWIF(drive)->resetproc(drive);
 438         return __ide_dma_timeout(drive);
 439 }
 440
 441 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 442 {
 443 #ifdef CONFIG_BLK_DEV_IDEDMA
 444 //      unsigned long high_16   = hwif->dma_base - (8*(hwif->channel));
 445         unsigned long high_16   = hwif->dma_master;
 446 #else /* !CONFIG_BLK_DEV_IDEDMA */
 447         unsigned long high_16   = pci_resource_start(hwif->pci_dev, 4);
 448 #endif /* CONFIG_BLK_DEV_IDEDMA */
 449         u8 udma_speed_flag      = hwif->INB(high_16|0x001f);
 450
 451         hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
 452         mdelay(100);
 453         hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
 454         mdelay(2000);   /* 2 seconds ?! */
 455
 456         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 457                 hwif->channel ? "Secondary" : "Primary");
 458 }
 459
 460 static void pdc202xx_reset (ide_drive_t *drive)
 461 {
 462         ide_hwif_t *hwif        = HWIF(drive);
 463         ide_hwif_t *mate        = hwif->mate;
 464
 465         pdc202xx_reset_host(hwif);
 466         pdc202xx_reset_host(mate);
 467 #if 0
 468         /*
 469          * FIXME: Have to kick all the drives again :-/
 470          * What a pain in the ACE!
 471          */
 472         if (hwif->present) {
 473                 u16 hunit = 0;
 474                 for (hunit = 0; hunit < MAX_DRIVES; ++hunit) {
 475                         ide_drive_t *hdrive = &hwif->drives[hunit];
 476                         if (hdrive->present) {
 477                                 if (hwif->ide_dma_check)
 478                                         hwif->ide_dma_check(hdrive);
 479                                 else
 480                                         hwif->tuneproc(hdrive, 5);
 481                         }
 482                 }
 483         }
 484         if (mate->present) {
 485                 u16 munit = 0;
 486                 for (munit = 0; munit < MAX_DRIVES; ++munit) {
 487                         ide_drive_t *mdrive = &mate->drives[munit];
 488                         if (mdrive->present) {
 489                                 if (mate->ide_dma_check)
 490                                         mate->ide_dma_check(mdrive);
 491                                 else
 492                                         mate->tuneproc(mdrive, 5);
 493                         }
 494                 }
 495         }
 496 #else
 497         hwif->tuneproc(drive, 5);
 498 #endif
 499 }
 500
 501 /*
 502  * Since SUN Cobalt is attempting to do this operation, I should disclose
 503  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 504  * HOTSWAP ATA Infrastructure.
 505  */
 506 static int pdc202xx_tristate (ide_drive_t * drive, int state)
 507 {
 508         ide_hwif_t *hwif        = HWIF(drive);
 509 //      unsigned long high_16   = hwif->dma_base - (8*(hwif->channel));
 510         unsigned long high_16   = hwif->dma_master;
 511         u8 sc1f                 = hwif->INB(high_16|0x001f);
 512
 513         if (!hwif)
 514                 return -EINVAL;
 515
 516 //      hwif->bus_state = state;
 517
 518         if (state) {
 519                 hwif->OUTB(sc1f | 0x08, (high_16|0x001f));
 520         } else {
 521                 hwif->OUTB(sc1f & ~0x08, (high_16|0x001f));
 522         }
 523         return 0;
 524 }
 525
 526 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev, const char *name)
 527 {
 528         if (dev->resource[PCI_ROM_RESOURCE].start) {
 529                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 530                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 531                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
 532                         name, dev->resource[PCI_ROM_RESOURCE].start);
 533         }
 534
 535         /*
 536          * software reset -  this is required because the bios
 537          * will set UDMA timing on if the hdd supports it. The
 538          * user may want to turn udma off. A bug in the pdc20262
 539          * is that it cannot handle a downgrade in timing from
 540          * UDMA to DMA. Disk accesses after issuing a set
 541          * feature command will result in errors. A software
 542          * reset leaves the timing registers intact,
 543          * but resets the drives.
 544          */
 545 #if 0
 546         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 547             (dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
 548             (dev->device == PCI_DEVICE_ID_PROMISE_20263) ||
 549             (dev->device == PCI_DEVICE_ID_PROMISE_20262)) {
 550                 unsigned long high_16   = pci_resource_start(dev, 4);
 551                 byte udma_speed_flag    = inb(high_16 + 0x001f);
 552                 outb(udma_speed_flag | 0x10, high_16 + 0x001f);
 553                 mdelay(100);
 554                 outb(udma_speed_flag & ~0x10, high_16 + 0x001f);
 555                 mdelay(2000);   /* 2 seconds ?! */
 556         }
 557
 558 #endif
 559         return dev->irq;
 560 }
 561
 562 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 563 {
 564         struct pci_dev *dev = hwif->pci_dev;
 565
 566         /* PDC20265 has problems with large LBA48 requests */
 567         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 568             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 569                 hwif->rqsize = 256;
 570
 571         hwif->autodma = 0;
 572         hwif->tuneproc  = &config_chipset_for_pio;
 573         hwif->quirkproc = &pdc202xx_quirkproc;
 574
 575         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 576                 hwif->busproc   = &pdc202xx_tristate;
 577                 hwif->resetproc = &pdc202xx_reset;
 578         }
 579
 580         hwif->speedproc = &pdc202xx_tune_chipset;
 581
 582         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 583
 584         hwif->ultra_mask = 0x3f;
 585         hwif->mwdma_mask = 0x07;
 586         hwif->swdma_mask = 0x07;
 587
 588         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 589         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 590         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 591
 592         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 593                 if (!(hwif->udma_four))
 594                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 595                 hwif->ide_dma_start = &pdc202xx_old_ide_dma_start;
 596                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 597         }
 598         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 599
 600         if (!noautodma)
 601                 hwif->autodma = 1;
 602         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 603 #if PDC202_DEBUG_CABLE
 604         printk(KERN_DEBUG "%s: %s-pin cable\n",
 605                 hwif->name, hwif->udma_four ? "80" : "40");
 606 #endif /* PDC202_DEBUG_CABLE */
 607 }
 608
 609 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 610 {
 611         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 612
 613         if (hwif->channel) {
 614                 ide_setup_dma(hwif, dmabase, 8);
 615                 return;
 616         }
 617
 618         udma_speed_flag = hwif->INB((dmabase|0x1f));
 619         primary_mode    = hwif->INB((dmabase|0x1a));
 620         secondary_mode  = hwif->INB((dmabase|0x1b));
 621         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 622                 "Primary %s Mode " \
 623                 "Secondary %s Mode.\n", hwif->cds->name,
 624                 (udma_speed_flag & 1) ? "EN" : "DIS",
 625                 (primary_mode & 1) ? "MASTER" : "PCI",
 626                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 627
 628 #ifdef CONFIG_PDC202XX_BURST
 629         if (!(udma_speed_flag & 1)) {
 630                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 631                         hwif->cds->name, udma_speed_flag,
 632                         (udma_speed_flag|1));
 633                 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
 634                 printk("%sACTIVE\n",
 635                         (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
 636         }
 637 #endif /* CONFIG_PDC202XX_BURST */
 638 #ifdef CONFIG_PDC202XX_MASTER
 639         if (!(primary_mode & 1)) {
 640                 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
 641                         "0x%02x -> 0x%02x ", hwif->cds->name,
 642                         primary_mode, (primary_mode|1));
 643                 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
 644                 printk("%s\n",
 645                         (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
 646         }
 647
 648         if (!(secondary_mode & 1)) {
 649                 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
 650                         "0x%02x -> 0x%02x ", hwif->cds->name,
 651                         secondary_mode, (secondary_mode|1));
 652                 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
 653                 printk("%s\n",
 654                         (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
 655         }
 656 #endif /* CONFIG_PDC202XX_MASTER */
 657
 658         ide_setup_dma(hwif, dmabase, 8);
 659 }
 660
 661 static void __devinit init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d)
 662 {
 663         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 664                 u8 irq = 0, irq2 = 0;
 665                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 666                 /* 0xbc */
 667                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 668                 if (irq != irq2) {
 669                         pci_write_config_byte(dev,
 670                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 671                         printk(KERN_INFO "%s: pci-config space interrupt "
 672                                 "mirror fixed.\n", d->name);
 673                 }
 674         }
 675
 676 #if 0
 677         if (dev->device == PCI_DEVICE_ID_PROMISE_20262)
 678         if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
 679              (tmp & e->mask) != e->val))
 680
 681         if (d->enablebits[0].reg != d->enablebits[1].reg) {
 682                 d->enablebits[0].reg    = d->enablebits[1].reg;
 683                 d->enablebits[0].mask   = d->enablebits[1].mask;
 684                 d->enablebits[0].val    = d->enablebits[1].val;
 685         }
 686 #endif
 687
 688         ide_setup_pci_device(dev, d);
 689 }
 690
 691 static void __devinit init_setup_pdc20265(struct pci_dev *dev, ide_pci_device_t *d)
 692 {
 693         if ((dev->bus->self) &&
 694             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 695             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 696              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 697                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 698                         "attached to I2O RAID controller.\n");
 699                 return;
 700         }
 701
 702 #if 0
 703         {
 704                 u8 pri = 0, sec = 0;
 705
 706         if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
 707              (tmp & e->mask) != e->val))
 708
 709         if (d->enablebits[0].reg != d->enablebits[1].reg) {
 710                 d->enablebits[0].reg    = d->enablebits[1].reg;
 711                 d->enablebits[0].mask   = d->enablebits[1].mask;
 712                 d->enablebits[0].val    = d->enablebits[1].val;
 713         }
 714         }
 715 #endif
 716
 717         ide_setup_pci_device(dev, d);
 718 }
 719
 720 static void __devinit init_setup_pdc202xx(struct pci_dev *dev, ide_pci_device_t *d)
 721 {
 722         ide_setup_pci_device(dev, d);
 723 }
 724
 725 /**
 726  *      pdc202xx_init_one       -       called when a PDC202xx is found
 727  *      @dev: the pdc202xx device
 728  *      @id: the matching pci id
 729  *
 730  *      Called when the PCI registration layer (or the IDE initialization)
 731  *      finds a device matching our IDE device tables.
 732  */
 733
 734 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 735 {
 736         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 737
 738         d->init_setup(dev, d);
 739         return 0;
 740 }
 741
 742 static struct pci_device_id pdc202xx_pci_tbl[] = {
 743         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 744         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 745         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 746         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 747         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 748         { 0, },
 749 };
 750 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 751
 752 static struct pci_driver driver = {
 753         .name           = "Promise_Old_IDE",
 754         .id_table       = pdc202xx_pci_tbl,
 755         .probe          = pdc202xx_init_one,
 756 };
 757
 758 static int pdc202xx_ide_init(void)
 759 {
 760         return ide_pci_register_driver(&driver);
 761 }
 762
 763 module_init(pdc202xx_ide_init);
 764
 765 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 766 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 767 MODULE_LICENSE("GPL");