2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.36 Sept 11, 2002
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
6 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
7 * compiled into the kernel if you have more than one card installed.
8 * Note that BIOS v1.29 is reported to fix the problem. Since this is
9 * safe chipset tuning, including this support is harmless
11 * Promise Ultra66 cards with BIOS v1.11 this
12 * compiled into the kernel if you have more than one card installed.
14 * Promise Ultra100 cards.
16 * The latest chipset code will support the following ::
17 * Three Ultra33 controllers and 12 drives.
18 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
19 * The 8/4 ratio is a BIOS code limit by promise.
21 * UNLESS you enable "CONFIG_PDC202XX_BURST"
26 * Portions Copyright (C) 1999 Promise Technology, Inc.
27 * Author: Frank Tiernan (frankt@promise.com)
28 * Released under terms of General Public License
31 #include <linux/config.h>
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/timer.h>
38 #include <linux/ioport.h>
39 #include <linux/blkdev.h>
40 #include <linux/hdreg.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/ide.h>
49 #include "pdc202xx_old.h"
51 #define PDC202_DEBUG_CABLE 0
53 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
54 #include <linux/stat.h>
55 #include <linux/proc_fs.h>
57 static u8 pdc202xx_proc = 0;
58 #define PDC202_MAX_DEVS 5
59 static struct pci_dev *pdc202_devs[PDC202_MAX_DEVS];
60 static int n_pdc202_devs;
62 static char * pdc202xx_info (char *buf, struct pci_dev *dev)
66 unsigned long bibma = pci_resource_start(dev, 4);
67 u32 reg60h = 0, reg64h = 0, reg68h = 0, reg6ch = 0;
68 u16 reg50h = 0, pmask = (1<<10), smask = (1<<11);
72 * at that point bibma+0x2 et bibma+0xa are byte registers
75 u8 c0 = inb_p((u16)bibma + 0x02);
76 u8 c1 = inb_p((u16)bibma + 0x0a);
78 u8 sc11 = inb_p((u16)bibma + 0x11);
79 u8 sc1a = inb_p((u16)bibma + 0x1a);
80 u8 sc1b = inb_p((u16)bibma + 0x1b);
81 u8 sc1c = inb_p((u16)bibma + 0x1c);
82 u8 sc1d = inb_p((u16)bibma + 0x1d);
83 u8 sc1e = inb_p((u16)bibma + 0x1e);
84 u8 sc1f = inb_p((u16)bibma + 0x1f);
86 pci_read_config_word(dev, 0x50, ®50h);
87 pci_read_config_dword(dev, 0x60, ®60h);
88 pci_read_config_dword(dev, 0x64, ®64h);
89 pci_read_config_dword(dev, 0x68, ®68h);
90 pci_read_config_dword(dev, 0x6c, ®6ch);
92 p += sprintf(p, "\n ");
94 case PCI_DEVICE_ID_PROMISE_20267:
95 p += sprintf(p, "Ultra100"); break;
96 case PCI_DEVICE_ID_PROMISE_20265:
97 p += sprintf(p, "Ultra100 on M/B"); break;
98 case PCI_DEVICE_ID_PROMISE_20263:
99 p += sprintf(p, "FastTrak 66"); break;
100 case PCI_DEVICE_ID_PROMISE_20262:
101 p += sprintf(p, "Ultra66"); break;
102 case PCI_DEVICE_ID_PROMISE_20246:
103 p += sprintf(p, "Ultra33");
107 p += sprintf(p, "Ultra Series"); break;
109 p += sprintf(p, " Chipset.\n");
111 p += sprintf(p, "------------------------------- General Status "
112 "---------------------------------\n");
113 p += sprintf(p, "Burst Mode : %sabled\n",
114 (sc1f & 0x01) ? "en" : "dis");
115 p += sprintf(p, "Host Mode : %s\n",
116 (sc1f & 0x08) ? "Tri-Stated" : "Normal");
117 p += sprintf(p, "Bus Clocking : %s\n",
118 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
119 ((sc1f & 0x80) == 0x80) ? "66 External" :
120 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
121 p += sprintf(p, "IO pad select : %s mA\n",
122 ((sc1c & 0x03) == 0x03) ? "10" :
123 ((sc1c & 0x02) == 0x02) ? "8" :
124 ((sc1c & 0x01) == 0x01) ? "6" :
125 ((sc1c & 0x00) == 0x00) ? "4" : "??");
126 SPLIT_BYTE(sc1e, hi, lo);
127 p += sprintf(p, "Status Polling Period : %d\n", hi);
128 p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
129 p += sprintf(p, "--------------- Primary Channel "
130 "---------------- Secondary Channel "
132 p += sprintf(p, " %s %s\n",
133 (c0&0x80)?"disabled":"enabled ",
134 (c1&0x80)?"disabled":"enabled ");
135 p += sprintf(p, "66 Clocking %s %s\n",
136 (sc11&0x02)?"enabled ":"disabled",
137 (sc11&0x08)?"enabled ":"disabled");
138 p += sprintf(p, " Mode %s Mode %s\n",
139 (sc1a & 0x01) ? "MASTER" : "PCI ",
140 (sc1b & 0x01) ? "MASTER" : "PCI ");
141 p += sprintf(p, " %s %s\n",
142 (sc1d & 0x08) ? "Error " :
143 ((sc1d & 0x05) == 0x05) ? "Not My INTR " :
144 (sc1d & 0x04) ? "Interrupting" :
145 (sc1d & 0x02) ? "FIFO Full " :
146 (sc1d & 0x01) ? "FIFO Empty " : "????????????",
147 (sc1d & 0x80) ? "Error " :
148 ((sc1d & 0x50) == 0x50) ? "Not My INTR " :
149 (sc1d & 0x40) ? "Interrupting" :
150 (sc1d & 0x20) ? "FIFO Full " :
151 (sc1d & 0x10) ? "FIFO Empty " : "????????????");
152 p += sprintf(p, "--------------- drive0 --------- drive1 "
153 "-------- drive0 ---------- drive1 ------\n");
154 p += sprintf(p, "DMA enabled: %s %s "
156 (c0&0x20)?"yes":"no ", (c0&0x40)?"yes":"no ",
157 (c1&0x20)?"yes":"no ", (c1&0x40)?"yes":"no ");
158 p += sprintf(p, "DMA Mode: %s %s "
160 pdc202xx_ultra_verbose(reg60h, (reg50h & pmask)),
161 pdc202xx_ultra_verbose(reg64h, (reg50h & pmask)),
162 pdc202xx_ultra_verbose(reg68h, (reg50h & smask)),
163 pdc202xx_ultra_verbose(reg6ch, (reg50h & smask)));
164 p += sprintf(p, "PIO Mode: %s %s "
166 pdc202xx_pio_verbose(reg60h),
167 pdc202xx_pio_verbose(reg64h),
168 pdc202xx_pio_verbose(reg68h),
169 pdc202xx_pio_verbose(reg6ch));
171 p += sprintf(p, "--------------- Can ATAPI DMA ---------------\n");
176 static int pdc202xx_get_info (char *buffer, char **addr, off_t offset, int count)
181 for (i = 0; i < n_pdc202_devs; i++) {
182 struct pci_dev *dev = pdc202_devs[i];
183 p = pdc202xx_info(buffer, dev);
185 /* p - buffer must be less than 4k! */
186 len = (p - buffer) - offset;
187 *addr = buffer + offset;
189 return len > count ? count : len;
191 #endif /* defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS) */
194 static u8 pdc202xx_ratemask (ide_drive_t *drive)
198 switch(HWIF(drive)->pci_dev->device) {
199 case PCI_DEVICE_ID_PROMISE_20267:
200 case PCI_DEVICE_ID_PROMISE_20265:
203 case PCI_DEVICE_ID_PROMISE_20263:
204 case PCI_DEVICE_ID_PROMISE_20262:
207 case PCI_DEVICE_ID_PROMISE_20246:
212 if (!eighty_ninty_three(drive))
213 mode = min(mode, (u8)1);
217 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
219 struct hd_driveid *id = drive->id;
221 if (pdc_quirk_drives == list) {
223 if (strstr(id->model, *list++)) {
229 if (!strcmp(*list++,id->model)) {
237 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
239 ide_hwif_t *hwif = HWIF(drive);
240 struct pci_dev *dev = hwif->pci_dev;
241 u8 drive_pci = 0x60 + (drive->dn << 2);
242 u8 speed = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
246 u8 TA = 0, TB = 0, TC = 0;
248 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
251 pci_read_config_dword(dev, drive_pci, &drive_conf);
252 pci_read_config_byte(dev, (drive_pci), &AP);
253 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
254 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
255 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
257 if (speed < XFER_SW_DMA_0) {
258 if ((AP & 0x0F) || (BP & 0x07)) {
259 /* clear PIO modes of lower 8421 bits of A Register */
260 pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
261 pci_read_config_byte(dev, (drive_pci), &AP);
263 /* clear PIO modes of lower 421 bits of B Register */
264 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
265 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
267 pci_read_config_byte(dev, (drive_pci), &AP);
268 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
271 if ((BP & 0xF0) && (CP & 0x0F)) {
272 /* clear DMA modes of upper 842 bits of B Register */
273 /* clear PIO forced mode upper 1 bit of B Register */
274 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
275 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
277 /* clear DMA modes of lower 8421 bits of C Register */
278 pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
279 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
283 pci_read_config_byte(dev, (drive_pci), &AP);
284 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
285 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
288 case XFER_UDMA_6: speed = XFER_UDMA_5;
290 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
291 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
293 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
295 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
296 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
298 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
299 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
300 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
301 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
302 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
303 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
304 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
306 default: TA = 0x09; TB = 0x13; break;
309 if (speed < XFER_SW_DMA_0) {
310 pci_write_config_byte(dev, (drive_pci), AP|TA);
311 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
313 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
314 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
317 #if PDC202XX_DEBUG_DRIVE_INFO
318 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
319 drive->name, ide_xfer_verbose(speed),
320 drive->dn, drive_conf);
321 pci_read_config_dword(dev, drive_pci, &drive_conf);
322 printk("0x%08x\n", drive_conf);
323 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
325 return (ide_config_drive_speed(drive, speed));
330 * 960, 480, 390, 300, 240, 180, 120, 90, 60
331 * 180, 150, 120, 90, 60
333 * 180, 120, 90, 90, 90, 60, 30
334 * 11, 5, 4, 3, 2, 1, 0
336 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
340 if (pio == 5) pio = 4;
341 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
343 pdc202xx_tune_chipset(drive, speed);
346 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
348 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
349 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
350 return ((u8)(CIS & mask));
354 * Set the control register to use the 66MHz system
355 * clock for UDMA 3/4/5 mode operation when necessary.
357 * It may also be possible to leave the 66MHz clock on
358 * and readjust the timing parameters.
360 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
362 unsigned long clock_reg = hwif->dma_master + 0x11;
363 u8 clock = hwif->INB(clock_reg);
365 hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
368 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
370 unsigned long clock_reg = hwif->dma_master + 0x11;
371 u8 clock = hwif->INB(clock_reg);
373 hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
376 static int config_chipset_for_dma (ide_drive_t *drive)
378 struct hd_driveid *id = drive->id;
379 ide_hwif_t *hwif = HWIF(drive);
380 struct pci_dev *dev = hwif->pci_dev;
382 u8 drive_pci = 0x60 + (drive->dn << 2);
383 u8 test1 = 0, test2 = 0, speed = -1;
384 u8 AP = 0, cable = 0;
386 u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
387 (id->dma_ultra & 0x0008)) ? 1 : 0;
389 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
390 cable = pdc202xx_old_cable_detect(hwif);
394 if (ultra_66 && cable) {
395 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
396 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
399 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
400 pdc_old_disable_66MHz_clock(drive->hwif);
402 drive_pci = 0x60 + (drive->dn << 2);
403 pci_read_config_dword(dev, drive_pci, &drive_conf);
404 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
407 pci_read_config_byte(dev, drive_pci, &test1);
408 if (!(test1 & SYNC_ERRDY_EN)) {
409 if (drive->select.b.unit & 0x01) {
410 pci_read_config_byte(dev, drive_pci - 4, &test2);
411 if ((test2 & SYNC_ERRDY_EN) &&
412 !(test1 & SYNC_ERRDY_EN)) {
413 pci_write_config_byte(dev, drive_pci,
414 test1|SYNC_ERRDY_EN);
417 pci_write_config_byte(dev, drive_pci,
418 test1|SYNC_ERRDY_EN);
424 if (drive->media == ide_disk) {
425 pci_read_config_byte(dev, (drive_pci), &AP);
426 if (id->capability & 4) /* IORDY_EN */
427 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
428 pci_read_config_byte(dev, (drive_pci), &AP);
429 if (drive->media == ide_disk) /* PREFETCH_EN */
430 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
433 speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
436 /* restore original pci-config space */
437 pci_write_config_dword(dev, drive_pci, drive_conf);
438 hwif->tuneproc(drive, 5);
442 (void) hwif->speedproc(drive, speed);
443 return ide_dma_enable(drive);
446 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
448 ide_hwif_t *hwif = HWIF(drive);
449 struct hd_driveid *id = drive->id;
451 drive->init_speed = 0;
453 if (id && (id->capability & 1) && drive->autodma) {
454 /* Consult the list of known "bad" drives */
455 if (__ide_dma_bad_drive(drive))
457 if (id->field_valid & 4) {
458 if (id->dma_ultra & hwif->ultra_mask) {
459 /* Force if Capable UltraDMA */
460 int dma = config_chipset_for_dma(drive);
461 if ((id->field_valid & 2) && !dma)
464 } else if (id->field_valid & 2) {
466 if ((id->dma_mword & hwif->mwdma_mask) ||
467 (id->dma_1word & hwif->swdma_mask)) {
468 /* Force if Capable regular DMA modes */
469 if (!config_chipset_for_dma(drive))
472 } else if (__ide_dma_good_drive(drive) &&
473 (id->eide_dma_time < 150)) {
475 /* Consult the list of known "good" drives */
476 if (!config_chipset_for_dma(drive))
481 return hwif->ide_dma_on(drive);
482 } else if ((id->capability & 8) || (id->field_valid & 2)) {
485 hwif->tuneproc(drive, 5);
486 return hwif->ide_dma_off_quietly(drive);
488 /* IORDY not supported */
492 static int pdc202xx_quirkproc (ide_drive_t *drive)
494 return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
497 static int pdc202xx_old_ide_dma_begin(ide_drive_t *drive)
499 if (drive->current_speed > XFER_UDMA_2)
500 pdc_old_enable_66MHz_clock(drive->hwif);
501 if (drive->addressing == 1) {
502 struct request *rq = HWGROUP(drive)->rq;
503 ide_hwif_t *hwif = HWIF(drive);
504 // struct pci_dev *dev = hwif->pci_dev;
505 // unsgned long high_16 = pci_resource_start(dev, 4);
506 unsigned long high_16 = hwif->dma_master;
507 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
509 u8 clock = hwif->INB(high_16 + 0x11);
511 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
512 word_count = (rq->nr_sectors << 8);
513 word_count = (rq_data_dir(rq) == READ) ?
514 word_count | 0x05000000 :
515 word_count | 0x06000000;
516 hwif->OUTL(word_count, atapi_reg);
518 return __ide_dma_begin(drive);
521 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
523 if (drive->addressing == 1) {
524 ide_hwif_t *hwif = HWIF(drive);
525 // unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
526 unsigned long high_16 = hwif->dma_master;
527 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
530 hwif->OUTL(0, atapi_reg); /* zero out extra */
531 clock = hwif->INB(high_16 + 0x11);
532 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
534 if (drive->current_speed > XFER_UDMA_2)
535 pdc_old_disable_66MHz_clock(drive->hwif);
536 return __ide_dma_end(drive);
539 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
541 ide_hwif_t *hwif = HWIF(drive);
542 // struct pci_dev *dev = hwif->pci_dev;
543 // unsigned long high_16 = pci_resource_start(dev, 4);
544 unsigned long high_16 = hwif->dma_master;
545 u8 dma_stat = hwif->INB(hwif->dma_status);
546 u8 sc1d = hwif->INB((high_16 + 0x001d));
549 if ((sc1d & 0x50) == 0x50)
551 else if ((sc1d & 0x40) == 0x40)
552 return (dma_stat & 4) == 4;
554 if ((sc1d & 0x05) == 0x05)
556 else if ((sc1d & 0x04) == 0x04)
557 return (dma_stat & 4) == 4;
560 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
563 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
565 if (HWIF(drive)->resetproc != NULL)
566 HWIF(drive)->resetproc(drive);
567 return __ide_dma_lostirq(drive);
570 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
572 if (HWIF(drive)->resetproc != NULL)
573 HWIF(drive)->resetproc(drive);
574 return __ide_dma_timeout(drive);
577 static void pdc202xx_reset_host (ide_hwif_t *hwif)
579 #ifdef CONFIG_BLK_DEV_IDEDMA
580 // unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
581 unsigned long high_16 = hwif->dma_master;
582 #else /* !CONFIG_BLK_DEV_IDEDMA */
583 unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
584 #endif /* CONFIG_BLK_DEV_IDEDMA */
585 u8 udma_speed_flag = hwif->INB(high_16|0x001f);
587 hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
589 hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
590 mdelay(2000); /* 2 seconds ?! */
592 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
593 hwif->channel ? "Secondary" : "Primary");
596 void pdc202xx_reset (ide_drive_t *drive)
598 ide_hwif_t *hwif = HWIF(drive);
599 ide_hwif_t *mate = hwif->mate;
601 pdc202xx_reset_host(hwif);
602 pdc202xx_reset_host(mate);
605 * FIXME: Have to kick all the drives again :-/
606 * What a pain in the ACE!
610 for (hunit = 0; hunit < MAX_DRIVES; ++hunit) {
611 ide_drive_t *hdrive = &hwif->drives[hunit];
612 if (hdrive->present) {
613 if (hwif->ide_dma_check)
614 hwif->ide_dma_check(hdrive);
616 hwif->tuneproc(hdrive, 5);
622 for (munit = 0; munit < MAX_DRIVES; ++munit) {
623 ide_drive_t *mdrive = &mate->drives[munit];
624 if (mdrive->present) {
625 if (mate->ide_dma_check)
626 mate->ide_dma_check(mdrive);
628 mate->tuneproc(mdrive, 5);
633 hwif->tuneproc(drive, 5);
638 * Since SUN Cobalt is attempting to do this operation, I should disclose
639 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
640 * HOTSWAP ATA Infrastructure.
642 static int pdc202xx_tristate (ide_drive_t * drive, int state)
644 ide_hwif_t *hwif = HWIF(drive);
645 // unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
646 unsigned long high_16 = hwif->dma_master;
647 u8 sc1f = hwif->INB(high_16|0x001f);
652 // hwif->bus_state = state;
655 hwif->OUTB(sc1f | 0x08, (high_16|0x001f));
657 hwif->OUTB(sc1f & ~0x08, (high_16|0x001f));
662 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev, const char *name)
664 if (dev->resource[PCI_ROM_RESOURCE].start) {
665 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
666 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
667 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
668 name, dev->resource[PCI_ROM_RESOURCE].start);
671 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
672 pdc202_devs[n_pdc202_devs++] = dev;
674 if (!pdc202xx_proc) {
676 ide_pci_create_host_proc("pdc202xx", pdc202xx_get_info);
678 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
681 * software reset - this is required because the bios
682 * will set UDMA timing on if the hdd supports it. The
683 * user may want to turn udma off. A bug in the pdc20262
684 * is that it cannot handle a downgrade in timing from
685 * UDMA to DMA. Disk accesses after issuing a set
686 * feature command will result in errors. A software
687 * reset leaves the timing registers intact,
688 * but resets the drives.
691 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
692 (dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
693 (dev->device == PCI_DEVICE_ID_PROMISE_20263) ||
694 (dev->device == PCI_DEVICE_ID_PROMISE_20262)) {
695 unsigned long high_16 = pci_resource_start(dev, 4);
696 byte udma_speed_flag = inb(high_16 + 0x001f);
697 outb(udma_speed_flag | 0x10, high_16 + 0x001f);
699 outb(udma_speed_flag & ~0x10, high_16 + 0x001f);
700 mdelay(2000); /* 2 seconds ?! */
707 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
709 struct pci_dev *dev = hwif->pci_dev;
711 /* PDC20265 has problems with large LBA48 requests */
712 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
713 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
717 hwif->tuneproc = &config_chipset_for_pio;
718 hwif->quirkproc = &pdc202xx_quirkproc;
720 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
721 hwif->busproc = &pdc202xx_tristate;
722 hwif->resetproc = &pdc202xx_reset;
725 hwif->speedproc = &pdc202xx_tune_chipset;
727 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
729 hwif->ultra_mask = 0x3f;
730 hwif->mwdma_mask = 0x07;
731 hwif->swdma_mask = 0x07;
733 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
734 hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
735 hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
737 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
738 if (!(hwif->udma_four))
739 hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
740 hwif->ide_dma_begin = &pdc202xx_old_ide_dma_begin;
741 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
743 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
747 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
748 #if PDC202_DEBUG_CABLE
749 printk(KERN_DEBUG "%s: %s-pin cable\n",
750 hwif->name, hwif->udma_four ? "80" : "40");
751 #endif /* PDC202_DEBUG_CABLE */
754 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
756 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
759 ide_setup_dma(hwif, dmabase, 8);
763 udma_speed_flag = hwif->INB((dmabase|0x1f));
764 primary_mode = hwif->INB((dmabase|0x1a));
765 secondary_mode = hwif->INB((dmabase|0x1b));
766 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
768 "Secondary %s Mode.\n", hwif->cds->name,
769 (udma_speed_flag & 1) ? "EN" : "DIS",
770 (primary_mode & 1) ? "MASTER" : "PCI",
771 (secondary_mode & 1) ? "MASTER" : "PCI" );
773 #ifdef CONFIG_PDC202XX_BURST
774 if (!(udma_speed_flag & 1)) {
775 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
776 hwif->cds->name, udma_speed_flag,
777 (udma_speed_flag|1));
778 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
780 (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
782 #endif /* CONFIG_PDC202XX_BURST */
783 #ifdef CONFIG_PDC202XX_MASTER
784 if (!(primary_mode & 1)) {
785 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
786 "0x%02x -> 0x%02x ", hwif->cds->name,
787 primary_mode, (primary_mode|1));
788 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
790 (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
793 if (!(secondary_mode & 1)) {
794 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
795 "0x%02x -> 0x%02x ", hwif->cds->name,
796 secondary_mode, (secondary_mode|1));
797 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
799 (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
801 #endif /* CONFIG_PDC202XX_MASTER */
803 ide_setup_dma(hwif, dmabase, 8);
806 static void __devinit init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d)
808 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
809 u8 irq = 0, irq2 = 0;
810 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
812 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
814 pci_write_config_byte(dev,
815 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
816 printk(KERN_INFO "%s: pci-config space interrupt "
817 "mirror fixed.\n", d->name);
822 if (dev->device == PCI_DEVICE_ID_PROMISE_20262)
823 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
824 (tmp & e->mask) != e->val))
826 if (d->enablebits[0].reg != d->enablebits[1].reg) {
827 d->enablebits[0].reg = d->enablebits[1].reg;
828 d->enablebits[0].mask = d->enablebits[1].mask;
829 d->enablebits[0].val = d->enablebits[1].val;
833 ide_setup_pci_device(dev, d);
836 static void __devinit init_setup_pdc20265(struct pci_dev *dev, ide_pci_device_t *d)
838 if ((dev->bus->self) &&
839 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
840 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
841 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
842 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
843 "attached to I2O RAID controller.\n");
851 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
852 (tmp & e->mask) != e->val))
854 if (d->enablebits[0].reg != d->enablebits[1].reg) {
855 d->enablebits[0].reg = d->enablebits[1].reg;
856 d->enablebits[0].mask = d->enablebits[1].mask;
857 d->enablebits[0].val = d->enablebits[1].val;
862 ide_setup_pci_device(dev, d);
865 static void __devinit init_setup_pdc202xx(struct pci_dev *dev, ide_pci_device_t *d)
867 ide_setup_pci_device(dev, d);
871 * pdc202xx_init_one - called when a PDC202xx is found
872 * @dev: the pdc202xx device
873 * @id: the matching pci id
875 * Called when the PCI registration layer (or the IDE initialization)
876 * finds a device matching our IDE device tables.
879 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
881 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
883 d->init_setup(dev, d);
887 static struct pci_device_id pdc202xx_pci_tbl[] = {
888 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
889 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
890 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
891 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
892 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
895 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
897 static struct pci_driver driver = {
898 .name = "Promise_Old_IDE",
899 .id_table = pdc202xx_pci_tbl,
900 .probe = pdc202xx_init_one,
903 static int pdc202xx_ide_init(void)
905 return ide_pci_register_driver(&driver);
908 module_init(pdc202xx_ide_init);
910 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
911 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
912 MODULE_LICENSE("GPL");