4 #include <linux/config.h>
9 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
12 #define PDC202XX_DEBUG_DRIVE_INFO 0
14 static const char *pdc_quirk_drives[] = {
15 "QUANTUM FIREBALLlct08 08",
16 "QUANTUM FIREBALLP KA6.4",
17 "QUANTUM FIREBALLP KA9.1",
18 "QUANTUM FIREBALLP LM20.4",
19 "QUANTUM FIREBALLP KX13.6",
20 "QUANTUM FIREBALLP KX20.5",
21 "QUANTUM FIREBALLP KX27.3",
22 "QUANTUM FIREBALLP LM20.5",
26 static inline u8 *pdc202xx_pio_verbose (u32 drive_pci)
28 if ((drive_pci & 0x000ff000) == 0x000ff000) return("NOTSET");
29 if ((drive_pci & 0x00000401) == 0x00000401) return("PIO 4");
30 if ((drive_pci & 0x00000602) == 0x00000602) return("PIO 3");
31 if ((drive_pci & 0x00000803) == 0x00000803) return("PIO 2");
32 if ((drive_pci & 0x00000C05) == 0x00000C05) return("PIO 1");
33 if ((drive_pci & 0x00001309) == 0x00001309) return("PIO 0");
37 static inline u8 *pdc202xx_dma_verbose (u32 drive_pci)
39 if ((drive_pci & 0x00036000) == 0x00036000) return("MWDMA 2");
40 if ((drive_pci & 0x00046000) == 0x00046000) return("MWDMA 1");
41 if ((drive_pci & 0x00056000) == 0x00056000) return("MWDMA 0");
42 if ((drive_pci & 0x00056000) == 0x00056000) return("SWDMA 2");
43 if ((drive_pci & 0x00068000) == 0x00068000) return("SWDMA 1");
44 if ((drive_pci & 0x000BC000) == 0x000BC000) return("SWDMA 0");
48 static inline u8 *pdc202xx_ultra_verbose (u32 drive_pci, u16 slow_cable)
50 if ((drive_pci & 0x000ff000) == 0x000ff000)
52 if ((drive_pci & 0x00012000) == 0x00012000)
53 return((slow_cable) ? "UDMA 2" : "UDMA 4");
54 if ((drive_pci & 0x00024000) == 0x00024000)
55 return((slow_cable) ? "UDMA 1" : "UDMA 3");
56 if ((drive_pci & 0x00036000) == 0x00036000)
58 return(pdc202xx_dma_verbose(drive_pci));
62 #define SYNC_ERRDY_EN 0xC0
64 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
65 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
66 #define IORDY_EN 0x20 /* PIO: IOREADY */
67 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
69 #define PA3 0x08 /* PIO"A" timing */
70 #define PA2 0x04 /* PIO"A" timing */
71 #define PA1 0x02 /* PIO"A" timing */
72 #define PA0 0x01 /* PIO"A" timing */
76 #define MB2 0x80 /* DMA"B" timing */
77 #define MB1 0x40 /* DMA"B" timing */
78 #define MB0 0x20 /* DMA"B" timing */
80 #define PB4 0x10 /* PIO_FORCE 1:0 */
82 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
83 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
84 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
85 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
88 #define IORDYp_NO_SPEED 0x4F
89 #define SPEED_DIS 0x0F
96 #define MC3 0x08 /* DMA"C" timing */
97 #define MC2 0x04 /* DMA"C" timing */
98 #define MC1 0x02 /* DMA"C" timing */
99 #define MC0 0x01 /* DMA"C" timing */
101 #define DISPLAY_PDC202XX_TIMINGS
103 static void init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d);
104 static void init_setup_pdc20265(struct pci_dev *, ide_pci_device_t *);
105 static void init_setup_pdc202xx(struct pci_dev *, ide_pci_device_t *);
106 static unsigned int init_chipset_pdc202xx(struct pci_dev *, const char *);
107 static void init_hwif_pdc202xx(ide_hwif_t *);
108 static void init_dma_pdc202xx(ide_hwif_t *, unsigned long);
110 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
113 .init_setup = init_setup_pdc202ata4,
114 .init_chipset = init_chipset_pdc202xx,
115 .init_hwif = init_hwif_pdc202xx,
116 .init_dma = init_dma_pdc202xx,
119 #ifndef CONFIG_PDC202XX_FORCE
120 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
122 .bootable = OFF_BOARD,
126 .init_setup = init_setup_pdc202ata4,
127 .init_chipset = init_chipset_pdc202xx,
128 .init_hwif = init_hwif_pdc202xx,
129 .init_dma = init_dma_pdc202xx,
132 #ifndef CONFIG_PDC202XX_FORCE
133 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
135 .bootable = OFF_BOARD,
137 .flags = IDEPCI_FLAG_FORCE_PDC,
140 .init_setup = init_setup_pdc202ata4,
141 .init_chipset = init_chipset_pdc202xx,
142 .init_hwif = init_hwif_pdc202xx,
143 .init_dma = init_dma_pdc202xx,
146 #ifndef CONFIG_PDC202XX_FORCE
147 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
149 .bootable = OFF_BOARD,
153 .init_setup = init_setup_pdc20265,
154 .init_chipset = init_chipset_pdc202xx,
155 .init_hwif = init_hwif_pdc202xx,
156 .init_dma = init_dma_pdc202xx,
159 #ifndef CONFIG_PDC202XX_FORCE
160 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
162 .bootable = OFF_BOARD,
164 .flags = IDEPCI_FLAG_FORCE_PDC,
167 .init_setup = init_setup_pdc202xx,
168 .init_chipset = init_chipset_pdc202xx,
169 .init_hwif = init_hwif_pdc202xx,
170 .init_dma = init_dma_pdc202xx,
173 #ifndef CONFIG_PDC202XX_FORCE
174 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
176 .bootable = OFF_BOARD,
181 #endif /* PDC202XX_H */