4 #include <linux/config.h>
9 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
12 #define PDC202XX_DEBUG_DRIVE_INFO 0
14 static const char *pdc_quirk_drives[] = {
15 "QUANTUM FIREBALLlct08 08",
16 "QUANTUM FIREBALLP KA6.4",
17 "QUANTUM FIREBALLP KA9.1",
18 "QUANTUM FIREBALLP LM20.4",
19 "QUANTUM FIREBALLP KX13.6",
20 "QUANTUM FIREBALLP KX20.5",
21 "QUANTUM FIREBALLP KX27.3",
22 "QUANTUM FIREBALLP LM20.5",
27 #define SYNC_ERRDY_EN 0xC0
29 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
30 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
31 #define IORDY_EN 0x20 /* PIO: IOREADY */
32 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
34 #define PA3 0x08 /* PIO"A" timing */
35 #define PA2 0x04 /* PIO"A" timing */
36 #define PA1 0x02 /* PIO"A" timing */
37 #define PA0 0x01 /* PIO"A" timing */
41 #define MB2 0x80 /* DMA"B" timing */
42 #define MB1 0x40 /* DMA"B" timing */
43 #define MB0 0x20 /* DMA"B" timing */
45 #define PB4 0x10 /* PIO_FORCE 1:0 */
47 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
48 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
49 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
50 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
53 #define IORDYp_NO_SPEED 0x4F
54 #define SPEED_DIS 0x0F
61 #define MC3 0x08 /* DMA"C" timing */
62 #define MC2 0x04 /* DMA"C" timing */
63 #define MC1 0x02 /* DMA"C" timing */
64 #define MC0 0x01 /* DMA"C" timing */
66 static void init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d);
67 static void init_setup_pdc20265(struct pci_dev *, ide_pci_device_t *);
68 static void init_setup_pdc202xx(struct pci_dev *, ide_pci_device_t *);
69 static unsigned int init_chipset_pdc202xx(struct pci_dev *, const char *);
70 static void init_hwif_pdc202xx(ide_hwif_t *);
71 static void init_dma_pdc202xx(ide_hwif_t *, unsigned long);
73 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
76 .init_setup = init_setup_pdc202ata4,
77 .init_chipset = init_chipset_pdc202xx,
78 .init_hwif = init_hwif_pdc202xx,
79 .init_dma = init_dma_pdc202xx,
82 #ifndef CONFIG_PDC202XX_FORCE
83 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
85 .bootable = OFF_BOARD,
89 .init_setup = init_setup_pdc202ata4,
90 .init_chipset = init_chipset_pdc202xx,
91 .init_hwif = init_hwif_pdc202xx,
92 .init_dma = init_dma_pdc202xx,
95 #ifndef CONFIG_PDC202XX_FORCE
96 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
98 .bootable = OFF_BOARD,
100 .flags = IDEPCI_FLAG_FORCE_PDC,
103 .init_setup = init_setup_pdc202ata4,
104 .init_chipset = init_chipset_pdc202xx,
105 .init_hwif = init_hwif_pdc202xx,
106 .init_dma = init_dma_pdc202xx,
109 #ifndef CONFIG_PDC202XX_FORCE
110 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
112 .bootable = OFF_BOARD,
116 .init_setup = init_setup_pdc20265,
117 .init_chipset = init_chipset_pdc202xx,
118 .init_hwif = init_hwif_pdc202xx,
119 .init_dma = init_dma_pdc202xx,
122 #ifndef CONFIG_PDC202XX_FORCE
123 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
125 .bootable = OFF_BOARD,
127 .flags = IDEPCI_FLAG_FORCE_PDC,
130 .init_setup = init_setup_pdc202xx,
131 .init_chipset = init_chipset_pdc202xx,
132 .init_hwif = init_hwif_pdc202xx,
133 .init_dma = init_dma_pdc202xx,
136 #ifndef CONFIG_PDC202XX_FORCE
137 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
139 .bootable = OFF_BOARD,
144 #endif /* PDC202XX_H */