4 #include <linux/config.h>
9 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
12 #define PDC202XX_DEBUG_DRIVE_INFO 0
13 #define PDC202XX_DECODE_REGISTER_INFO 0
15 static const char *pdc_quirk_drives[] = {
16 "QUANTUM FIREBALLlct08 08",
17 "QUANTUM FIREBALLP KA6.4",
18 "QUANTUM FIREBALLP KA9.1",
19 "QUANTUM FIREBALLP LM20.4",
20 "QUANTUM FIREBALLP KX13.6",
21 "QUANTUM FIREBALLP KX20.5",
22 "QUANTUM FIREBALLP KX27.3",
23 "QUANTUM FIREBALLP LM20.5",
27 static inline u8 *pdc202xx_pio_verbose (u32 drive_pci)
29 if ((drive_pci & 0x000ff000) == 0x000ff000) return("NOTSET");
30 if ((drive_pci & 0x00000401) == 0x00000401) return("PIO 4");
31 if ((drive_pci & 0x00000602) == 0x00000602) return("PIO 3");
32 if ((drive_pci & 0x00000803) == 0x00000803) return("PIO 2");
33 if ((drive_pci & 0x00000C05) == 0x00000C05) return("PIO 1");
34 if ((drive_pci & 0x00001309) == 0x00001309) return("PIO 0");
38 static inline u8 *pdc202xx_dma_verbose (u32 drive_pci)
40 if ((drive_pci & 0x00036000) == 0x00036000) return("MWDMA 2");
41 if ((drive_pci & 0x00046000) == 0x00046000) return("MWDMA 1");
42 if ((drive_pci & 0x00056000) == 0x00056000) return("MWDMA 0");
43 if ((drive_pci & 0x00056000) == 0x00056000) return("SWDMA 2");
44 if ((drive_pci & 0x00068000) == 0x00068000) return("SWDMA 1");
45 if ((drive_pci & 0x000BC000) == 0x000BC000) return("SWDMA 0");
49 static inline u8 *pdc202xx_ultra_verbose (u32 drive_pci, u16 slow_cable)
51 if ((drive_pci & 0x000ff000) == 0x000ff000)
53 if ((drive_pci & 0x00012000) == 0x00012000)
54 return((slow_cable) ? "UDMA 2" : "UDMA 4");
55 if ((drive_pci & 0x00024000) == 0x00024000)
56 return((slow_cable) ? "UDMA 1" : "UDMA 3");
57 if ((drive_pci & 0x00036000) == 0x00036000)
59 return(pdc202xx_dma_verbose(drive_pci));
63 #define SYNC_ERRDY_EN 0xC0
65 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
66 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
67 #define IORDY_EN 0x20 /* PIO: IOREADY */
68 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
70 #define PA3 0x08 /* PIO"A" timing */
71 #define PA2 0x04 /* PIO"A" timing */
72 #define PA1 0x02 /* PIO"A" timing */
73 #define PA0 0x01 /* PIO"A" timing */
77 #define MB2 0x80 /* DMA"B" timing */
78 #define MB1 0x40 /* DMA"B" timing */
79 #define MB0 0x20 /* DMA"B" timing */
81 #define PB4 0x10 /* PIO_FORCE 1:0 */
83 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
84 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
85 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
86 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
89 #define IORDYp_NO_SPEED 0x4F
90 #define SPEED_DIS 0x0F
97 #define MC3 0x08 /* DMA"C" timing */
98 #define MC2 0x04 /* DMA"C" timing */
99 #define MC1 0x02 /* DMA"C" timing */
100 #define MC0 0x01 /* DMA"C" timing */
102 #if PDC202XX_DECODE_REGISTER_INFO
109 static void decode_registers (u8 registers, u8 value)
111 u8 bit = 0, bit1 = 0, bit2 = 0;
116 printk("A Register ");
117 if (value & 0x80) printk("SYNC_IN ");
118 if (value & 0x40) printk("ERRDY_EN ");
119 if (value & 0x20) printk("IORDY_EN ");
120 if (value & 0x10) printk("PREFETCH_EN ");
121 if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
122 if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
123 if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
124 if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
125 printk("PIO(A) = %d ", bit2);
129 printk("B Register ");
130 if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
131 if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
132 if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
133 printk("DMA(B) = %d ", bit1 >> 5);
134 if (value & 0x10) printk("PIO_FORCED/PB4 ");
135 if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
136 if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
137 if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
138 if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
139 printk("PIO(B) = %d ", bit2);
143 printk("C Register ");
144 if (value & 0x80) printk("DMARQp ");
145 if (value & 0x40) printk("IORDYp ");
146 if (value & 0x20) printk("DMAR_EN ");
147 if (value & 0x10) printk("DMAW_EN ");
149 if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
150 if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
151 if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
152 if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
153 printk("DMA(C) = %d ", bit2);
156 printk("D Register ");
161 printk("\n %s ", (registers & REG_D) ? "DP" :
162 (registers & REG_C) ? "CP" :
163 (registers & REG_B) ? "BP" :
164 (registers & REG_A) ? "AP" : "ERROR");
165 for (bit=128;bit>0;bit/=2)
166 printk("%s", (value & bit) ? "1" : "0");
170 #endif /* PDC202XX_DECODE_REGISTER_INFO */
172 #define DISPLAY_PDC202XX_TIMINGS
174 static void init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d);
175 static void init_setup_pdc20265(struct pci_dev *, ide_pci_device_t *);
176 static void init_setup_pdc202xx(struct pci_dev *, ide_pci_device_t *);
177 static unsigned int init_chipset_pdc202xx(struct pci_dev *, const char *);
178 static void init_hwif_pdc202xx(ide_hwif_t *);
179 static void init_dma_pdc202xx(ide_hwif_t *, unsigned long);
181 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
183 .vendor = PCI_VENDOR_ID_PROMISE,
184 .device = PCI_DEVICE_ID_PROMISE_20246,
186 .init_setup = init_setup_pdc202ata4,
187 .init_chipset = init_chipset_pdc202xx,
188 .init_hwif = init_hwif_pdc202xx,
189 .init_dma = init_dma_pdc202xx,
192 #ifndef CONFIG_PDC202XX_FORCE
193 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
195 .bootable = OFF_BOARD,
198 .vendor = PCI_VENDOR_ID_PROMISE,
199 .device = PCI_DEVICE_ID_PROMISE_20262,
201 .init_setup = init_setup_pdc202ata4,
202 .init_chipset = init_chipset_pdc202xx,
203 .init_hwif = init_hwif_pdc202xx,
204 .init_dma = init_dma_pdc202xx,
207 #ifndef CONFIG_PDC202XX_FORCE
208 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
210 .bootable = OFF_BOARD,
213 .vendor = PCI_VENDOR_ID_PROMISE,
214 .device = PCI_DEVICE_ID_PROMISE_20263,
216 .init_setup = init_setup_pdc202ata4,
217 .init_chipset = init_chipset_pdc202xx,
218 .init_hwif = init_hwif_pdc202xx,
219 .init_dma = init_dma_pdc202xx,
222 #ifndef CONFIG_PDC202XX_FORCE
223 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
225 .bootable = OFF_BOARD,
228 .vendor = PCI_VENDOR_ID_PROMISE,
229 .device = PCI_DEVICE_ID_PROMISE_20265,
231 .init_setup = init_setup_pdc20265,
232 .init_chipset = init_chipset_pdc202xx,
233 .init_hwif = init_hwif_pdc202xx,
234 .init_dma = init_dma_pdc202xx,
237 #ifndef CONFIG_PDC202XX_FORCE
238 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
240 .bootable = OFF_BOARD,
243 .vendor = PCI_VENDOR_ID_PROMISE,
244 .device = PCI_DEVICE_ID_PROMISE_20267,
246 .init_setup = init_setup_pdc202xx,
247 .init_chipset = init_chipset_pdc202xx,
248 .init_hwif = init_hwif_pdc202xx,
249 .init_dma = init_dma_pdc202xx,
252 #ifndef CONFIG_PDC202XX_FORCE
253 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
255 .bootable = OFF_BOARD,
260 #endif /* PDC202XX_H */