2 * linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
8 * May be copied or modified under the terms of the GNU General Public License
10 * PIO mode setting function for Intel chipsets.
11 * For use instead of BIOS settings.
19 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
20 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
21 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
22 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
24 * sitre = word40 & 0x4000; primary
25 * sitre = word42 & 0x4000; secondary
27 * 44 8421|8421 hdd|hdb
29 * 48 8421 hdd|hdc|hdb|hda udma enabled
41 * ata-33/82801AB ata-66/82801AA
42 * 00|00 udma 0 00|00 reserved
43 * 01|01 udma 1 01|01 udma 3
44 * 10|10 udma 2 10|10 udma 4
45 * 11|11 reserved 11|11 reserved
47 * 54 8421|8421 ata66 drive|ata66 enable
49 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
52 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
53 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
54 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
57 * Publically available from Intel web site. Errata documentation
58 * is also publically available. As an aide to anyone hacking on this
59 * driver the list of errata that are relevant is below.going back to
60 * PIIX4. Older device documentation is now a bit tricky to find.
65 * PIIX4 errata #9 - Only on ultra obscure hw
66 * ICH3 errata #13 - Not observed to affect real hw
69 * Things we must deal with
70 * PIIX4 errata #10 - BM IDE hang with non UDMA
71 * (must stop/start dma to recover)
72 * 440MX errata #15 - As PIIX4 errata #10
73 * PIIX4 errata #15 - Must not read control registers
74 * during a PIO transfer
75 * 440MX errata #13 - As PIIX4 errata #15
76 * ICH2 errata #21 - DMA mode 0 doesn't work right
77 * ICH0/1 errata #55 - As ICH2 errata #21
78 * ICH2 spec c #9 - Extra operations needed to handle
79 * drive hotswap [NOT YET SUPPORTED]
80 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
81 * and must be dword aligned
82 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
84 * Should have been BIOS fixed:
85 * 450NX: errata #19 - DMA hangs on old 450NX
86 * 450NX: errata #20 - DMA hangs on old 450NX
87 * 450NX: errata #25 - Corruption with DMA on old 450NX
88 * ICH3 errata #15 - IDE deadlock under high load
89 * (BIOS must set dev 31 fn 0 bit 23)
90 * ICH3 errata #18 - Don't use native mode
93 #include <linux/config.h>
94 #include <linux/types.h>
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/ioport.h>
98 #include <linux/pci.h>
99 #include <linux/hdreg.h>
100 #include <linux/ide.h>
101 #include <linux/delay.h>
102 #include <linux/init.h>
108 static int no_piix_dma;
111 * piix_ratemask - compute rate mask for PIIX IDE
112 * @drive: IDE drive to compute for
114 * Returns the available modes for the PIIX IDE controller.
117 static u8 piix_ratemask (ide_drive_t *drive)
119 struct pci_dev *dev = HWIF(drive)->pci_dev;
122 switch(dev->device) {
123 case PCI_DEVICE_ID_INTEL_82801EB_1:
126 /* UDMA 100 capable */
127 case PCI_DEVICE_ID_INTEL_82801BA_8:
128 case PCI_DEVICE_ID_INTEL_82801BA_9:
129 case PCI_DEVICE_ID_INTEL_82801CA_10:
130 case PCI_DEVICE_ID_INTEL_82801CA_11:
131 case PCI_DEVICE_ID_INTEL_82801E_11:
132 case PCI_DEVICE_ID_INTEL_82801DB_10:
133 case PCI_DEVICE_ID_INTEL_82801DB_11:
134 case PCI_DEVICE_ID_INTEL_82801EB_11:
135 case PCI_DEVICE_ID_INTEL_ESB_2:
136 case PCI_DEVICE_ID_INTEL_ICH6_19:
139 /* UDMA 66 capable */
140 case PCI_DEVICE_ID_INTEL_82801AA_1:
141 case PCI_DEVICE_ID_INTEL_82372FB_1:
144 /* UDMA 33 capable */
145 case PCI_DEVICE_ID_INTEL_82371AB:
146 case PCI_DEVICE_ID_INTEL_82443MX_1:
147 case PCI_DEVICE_ID_INTEL_82451NX:
148 case PCI_DEVICE_ID_INTEL_82801AB_1:
150 /* Non UDMA capable (MWDMA2) */
151 case PCI_DEVICE_ID_INTEL_82371SB_1:
152 case PCI_DEVICE_ID_INTEL_82371FB_1:
153 case PCI_DEVICE_ID_INTEL_82371FB_0:
154 case PCI_DEVICE_ID_INTEL_82371MX:
160 * If we are UDMA66 capable fall back to UDMA33
161 * if the drive cannot see an 80pin cable.
163 if (!eighty_ninty_three(drive))
164 mode = min(mode, (u8)1);
169 * piix_dma_2_pio - return the PIO mode matching DMA
170 * @xfer_rate: transfer speed
172 * Returns the nearest equivalent PIO timing for the PIO or DMA
173 * mode requested by the controller.
176 static u8 piix_dma_2_pio (u8 xfer_rate) {
206 * piix_tune_drive - tune a drive attached to a PIIX
207 * @drive: drive to tune
208 * @pio: desired PIO mode
210 * Set the interface PIO mode based upon the settings done by AMI BIOS
211 * (might be useful if drive is not registered in CMOS for any reason).
213 static void piix_tune_drive (ide_drive_t *drive, u8 pio)
215 ide_hwif_t *hwif = HWIF(drive);
216 struct pci_dev *dev = hwif->pci_dev;
217 int is_slave = (&hwif->drives[1] == drive);
218 int master_port = hwif->channel ? 0x42 : 0x40;
219 int slave_port = 0x44;
224 u8 timings[][2] = { { 0, 0 },
230 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
231 spin_lock_irqsave(&ide_lock, flags);
232 pci_read_config_word(dev, master_port, &master_data);
234 master_data = master_data | 0x4000;
236 /* enable PPE, IE and TIME */
237 master_data = master_data | 0x0070;
238 pci_read_config_byte(dev, slave_port, &slave_data);
239 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
240 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
242 master_data = master_data & 0xccf8;
244 /* enable PPE, IE and TIME */
245 master_data = master_data | 0x0007;
246 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
248 pci_write_config_word(dev, master_port, master_data);
250 pci_write_config_byte(dev, slave_port, slave_data);
251 spin_unlock_irqrestore(&ide_lock, flags);
255 * piix_tune_chipset - tune a PIIX interface
256 * @drive: IDE drive to tune
257 * @xferspeed: speed to configure
259 * Set a PIIX interface channel to the desired speeds. This involves
260 * requires the right timing data into the PIIX configuration space
261 * then setting the drive parameters appropriately
264 static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
266 ide_hwif_t *hwif = HWIF(drive);
267 struct pci_dev *dev = hwif->pci_dev;
268 u8 maslave = hwif->channel ? 0x42 : 0x40;
269 u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed);
270 int a_speed = 3 << (drive->dn * 4);
271 int u_flag = 1 << drive->dn;
272 int v_flag = 0x01 << drive->dn;
273 int w_flag = 0x10 << drive->dn;
277 u8 reg48, reg54, reg55;
279 pci_read_config_word(dev, maslave, ®4042);
280 sitre = (reg4042 & 0x4000) ? 1 : 0;
281 pci_read_config_byte(dev, 0x48, ®48);
282 pci_read_config_word(dev, 0x4a, ®4a);
283 pci_read_config_byte(dev, 0x54, ®54);
284 pci_read_config_byte(dev, 0x55, ®55);
288 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
291 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
292 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
295 case XFER_SW_DMA_2: break;
299 case XFER_PIO_0: break;
303 if (speed >= XFER_UDMA_0) {
304 if (!(reg48 & u_flag))
305 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
306 if (speed == XFER_UDMA_5) {
307 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
309 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
311 if ((reg4a & a_speed) != u_speed)
312 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
313 if (speed > XFER_UDMA_2) {
314 if (!(reg54 & v_flag))
315 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
317 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
320 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
322 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
324 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
326 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
329 piix_tune_drive(drive, piix_dma_2_pio(speed));
330 return (ide_config_drive_speed(drive, speed));
334 * piix_faulty_dma0 - check for DMA0 errata
335 * @hwif: IDE interface to check
337 * If an ICH/ICH0/ICH2 interface is is operating in multi-word
338 * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
339 * inadvertently provide an extra piece of secondary data to the primary
340 * device resulting in data corruption.
342 * With such a device this test function returns true. This allows
343 * our tuning code to follow Intel recommendations and use PIO on
347 static int piix_faulty_dma0(ide_hwif_t *hwif)
349 switch(hwif->pci_dev->device)
351 case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */
352 case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */
353 case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */
354 case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */
361 * piix_config_drive_for_dma - configure drive for DMA
362 * @drive: IDE drive to configure
364 * Set up a PIIX interface channel for the best available speed.
365 * We prefer UDMA if it is available and then MWDMA. If DMA is
366 * not available we switch to PIO and return 0.
369 static int piix_config_drive_for_dma (ide_drive_t *drive)
371 u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
373 /* Some ICH devices cannot support DMA mode 0 */
374 if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
377 /* If no DMA speed was available or the chipset has DMA bugs
378 then disable DMA and use PIO */
380 if (!speed || no_piix_dma) {
381 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
382 speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
385 (void) piix_tune_chipset(drive, speed);
386 return ide_dma_enable(drive);
390 * piix_config_drive_xfer_rate - set up an IDE device
391 * @drive: IDE drive to configure
393 * Set up the PIIX interface for the best available speed on this
394 * interface, preferring DMA to PIO.
397 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
399 ide_hwif_t *hwif = HWIF(drive);
400 struct hd_driveid *id = drive->id;
402 drive->init_speed = 0;
404 if ((id->capability & 1) && drive->autodma) {
406 if (ide_use_dma(drive)) {
407 if (piix_config_drive_for_dma(drive))
408 return hwif->ide_dma_on(drive);
413 } else if ((id->capability & 8) || (id->field_valid & 2)) {
415 /* Find best PIO mode. */
416 hwif->tuneproc(drive, 255);
417 return hwif->ide_dma_off_quietly(drive);
419 /* IORDY not supported */
424 * init_chipset_piix - set up the PIIX chipset
425 * @dev: PCI device to set up
426 * @name: Name of the device
428 * Initialize the PCI device as required. For the PIIX this turns
429 * out to be nice and simple
432 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
434 switch(dev->device) {
435 case PCI_DEVICE_ID_INTEL_82801EB_1:
436 case PCI_DEVICE_ID_INTEL_82801AA_1:
437 case PCI_DEVICE_ID_INTEL_82801AB_1:
438 case PCI_DEVICE_ID_INTEL_82801BA_8:
439 case PCI_DEVICE_ID_INTEL_82801BA_9:
440 case PCI_DEVICE_ID_INTEL_82801CA_10:
441 case PCI_DEVICE_ID_INTEL_82801CA_11:
442 case PCI_DEVICE_ID_INTEL_82801DB_10:
443 case PCI_DEVICE_ID_INTEL_82801DB_11:
444 case PCI_DEVICE_ID_INTEL_82801EB_11:
445 case PCI_DEVICE_ID_INTEL_82801E_11:
446 case PCI_DEVICE_ID_INTEL_ESB_2:
447 case PCI_DEVICE_ID_INTEL_ICH6_19:
449 unsigned int extra = 0;
450 pci_read_config_dword(dev, 0x54, &extra);
451 pci_write_config_dword(dev, 0x54, extra|0x400);
461 * init_hwif_piix - fill in the hwif for the PIIX
462 * @hwif: IDE interface
464 * Set up the ide_hwif_t for the PIIX interface according to the
465 * capabilities of the hardware.
468 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
470 u8 reg54h = 0, reg55h = 0, ata66 = 0;
471 u8 mask = hwif->channel ? 0xc0 : 0x30;
475 hwif->irq = hwif->channel ? 15 : 14;
476 #endif /* CONFIG_IA64 */
478 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
479 /* This is a painful system best to let it self tune for now */
484 hwif->tuneproc = &piix_tune_drive;
485 hwif->speedproc = &piix_tune_chipset;
486 hwif->drives[0].autotune = 1;
487 hwif->drives[1].autotune = 1;
493 hwif->ultra_mask = 0x3f;
494 hwif->mwdma_mask = 0x06;
495 hwif->swdma_mask = 0x04;
497 switch(hwif->pci_dev->device) {
498 case PCI_DEVICE_ID_INTEL_82371MX:
499 hwif->mwdma_mask = 0x80;
500 hwif->swdma_mask = 0x80;
501 case PCI_DEVICE_ID_INTEL_82371FB_0:
502 case PCI_DEVICE_ID_INTEL_82371FB_1:
503 case PCI_DEVICE_ID_INTEL_82371SB_1:
504 hwif->ultra_mask = 0x80;
506 case PCI_DEVICE_ID_INTEL_82371AB:
507 case PCI_DEVICE_ID_INTEL_82443MX_1:
508 case PCI_DEVICE_ID_INTEL_82451NX:
509 case PCI_DEVICE_ID_INTEL_82801AB_1:
510 hwif->ultra_mask = 0x07;
513 pci_read_config_byte(hwif->pci_dev, 0x54, ®54h);
514 pci_read_config_byte(hwif->pci_dev, 0x55, ®55h);
515 ata66 = (reg54h & mask) ? 1 : 0;
519 if (!(hwif->udma_four))
520 hwif->udma_four = ata66;
521 hwif->ide_dma_check = &piix_config_drive_xfer_rate;
525 hwif->drives[1].autodma = hwif->autodma;
526 hwif->drives[0].autodma = hwif->autodma;
530 * init_setup_piix - callback for IDE initialize
531 * @dev: PIIX PCI device
534 * Enable the xp fixup for the PIIX controller and then perform
535 * a standard ide PCI setup
538 static void __devinit init_setup_piix(struct pci_dev *dev, ide_pci_device_t *d)
540 ide_setup_pci_device(dev, d);
544 * piix_init_one - called when a PIIX is found
545 * @dev: the piix device
546 * @id: the matching pci id
548 * Called when the PCI registration layer (or the IDE initialization)
549 * finds a device matching our IDE device tables.
552 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
554 ide_pci_device_t *d = &piix_pci_info[id->driver_data];
556 d->init_setup(dev, d);
561 * piix_check_450nx - Check for problem 450NX setup
563 * Check for the present of 450NX errata #19 and errata #25. If
564 * they are found, disable use of DMA IDE
567 static void __devinit piix_check_450nx(void)
569 struct pci_dev *pdev = NULL;
572 while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
574 /* Look for 450NX PXB. Check for problem configurations
575 A PCI quirk checks bit 6 already */
576 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
577 pci_read_config_word(pdev, 0x41, &cfg);
578 /* Only on the original revision: IDE DMA can hang */
581 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
582 else if(cfg & (1<<14) && rev < 5)
586 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
588 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
591 static struct pci_device_id piix_pci_tbl[] = {
592 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
593 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
594 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
595 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
596 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
597 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
598 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
599 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
600 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
601 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
602 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
603 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
604 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
605 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
606 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
607 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
608 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
609 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
610 #ifdef CONFIG_BLK_DEV_IDE_SATA
611 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
613 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
614 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
617 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
619 static struct pci_driver driver = {
621 .id_table = piix_pci_tbl,
622 .probe = piix_init_one,
625 static int __init piix_ide_init(void)
628 return ide_pci_register_driver(&driver);
631 module_init(piix_ide_init);
633 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
634 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
635 MODULE_LICENSE("GPL");