2 * linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
8 * May be copied or modified under the terms of the GNU General Public License
10 * PIO mode setting function for Intel chipsets.
11 * For use instead of BIOS settings.
19 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
20 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
21 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
22 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
24 * sitre = word40 & 0x4000; primary
25 * sitre = word42 & 0x4000; secondary
27 * 44 8421|8421 hdd|hdb
29 * 48 8421 hdd|hdc|hdb|hda udma enabled
41 * ata-33/82801AB ata-66/82801AA
42 * 00|00 udma 0 00|00 reserved
43 * 01|01 udma 1 01|01 udma 3
44 * 10|10 udma 2 10|10 udma 4
45 * 11|11 reserved 11|11 reserved
47 * 54 8421|8421 ata66 drive|ata66 enable
49 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
52 * pci_read_config_word(HWIF(drive)->pci_dev, 0x48, ®48);
53 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
54 * pci_read_config_word(HWIF(drive)->pci_dev, 0x54, ®54);
57 * Publically available from Intel web site. Errata documentation
58 * is also publically available. As an aide to anyone hacking on this
59 * driver the list of errata that are relevant is below.going back to
60 * PIIX4. Older device documentation is now a bit tricky to find.
65 * PIIX4 errata #9 - Only on ultra obscure hw
66 * ICH3 errata #13 - Not observed to affect real hw
69 * Things we must deal with
70 * PIIX4 errata #10 - BM IDE hang with non UDMA
71 * (must stop/start dma to recover)
72 * 440MX errata #15 - As PIIX4 errata #10
73 * PIIX4 errata #15 - Must not read control registers
74 * during a PIO transfer
75 * 440MX errata #13 - As PIIX4 errata #15
76 * ICH2 errata #21 - DMA mode 0 doesn't work right
77 * ICH0/1 errata #55 - As ICH2 errata #21
78 * ICH2 spec c #9 - Extra operations needed to handle
79 * drive hotswap [NOT YET SUPPORTED]
80 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
81 * and must be dword aligned
82 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
84 * Should have been BIOS fixed:
85 * 450NX: errata #19 - DMA hangs on old 450NX
86 * 450NX: errata #20 - DMA hangs on old 450NX
87 * 450NX: errata #25 - Corruption with DMA on old 450NX
88 * ICH3 errata #15 - IDE deadlock under high load
89 * (BIOS must set dev 31 fn 0 bit 23)
90 * ICH3 errata #18 - Don't use native mode
93 #include <linux/config.h>
94 #include <linux/types.h>
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/ioport.h>
98 #include <linux/pci.h>
99 #include <linux/hdreg.h>
100 #include <linux/ide.h>
101 #include <linux/delay.h>
102 #include <linux/init.h>
108 static int no_piix_dma;
109 #if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
110 #include <linux/stat.h>
111 #include <linux/proc_fs.h>
113 static u8 piix_proc = 0;
114 #define PIIX_MAX_DEVS 5
115 static struct pci_dev *piix_devs[PIIX_MAX_DEVS];
116 static int n_piix_devs;
119 * piix_get_info - fill in /proc for PIIX ide
120 * @buffer: buffer to fill
121 * @addr: address of user start in buffer
122 * @offset: offset into 'file'
123 * @count: buffer count
125 * Walks the PIIX devices and outputs summary data on the tuning and
126 * anything else that will help with debugging
129 static int piix_get_info (char *buffer, char **addr, off_t offset, int count)
134 for (i = 0; i < n_piix_devs; i++) {
135 struct pci_dev *dev = piix_devs[i];
136 unsigned long bibma = pci_resource_start(dev, 4);
137 u16 reg40 = 0, psitre = 0, reg42 = 0, ssitre = 0;
138 u8 c0 = 0, c1 = 0, reg54 = 0, reg55 = 0;
139 u8 reg44 = 0, reg48 = 0, reg4a = 0, reg4b = 0;
141 p += sprintf(p, "\nController: %d\n", i);
142 p += sprintf(p, "\n Intel ");
143 switch(dev->device) {
144 case PCI_DEVICE_ID_INTEL_82801EB_1:
145 p += sprintf(p, "PIIX4 SATA 150 ");
147 case PCI_DEVICE_ID_INTEL_82801BA_8:
148 case PCI_DEVICE_ID_INTEL_82801BA_9:
149 case PCI_DEVICE_ID_INTEL_82801CA_10:
150 case PCI_DEVICE_ID_INTEL_82801CA_11:
151 case PCI_DEVICE_ID_INTEL_82801DB_10:
152 case PCI_DEVICE_ID_INTEL_82801DB_11:
153 case PCI_DEVICE_ID_INTEL_82801EB_11:
154 case PCI_DEVICE_ID_INTEL_82801E_11:
155 case PCI_DEVICE_ID_INTEL_ESB_2:
156 case PCI_DEVICE_ID_INTEL_ICH6_19:
157 p += sprintf(p, "PIIX4 Ultra 100 ");
159 case PCI_DEVICE_ID_INTEL_82372FB_1:
160 case PCI_DEVICE_ID_INTEL_82801AA_1:
161 p += sprintf(p, "PIIX4 Ultra 66 ");
163 case PCI_DEVICE_ID_INTEL_82451NX:
164 case PCI_DEVICE_ID_INTEL_82801AB_1:
165 case PCI_DEVICE_ID_INTEL_82443MX_1:
166 case PCI_DEVICE_ID_INTEL_82371AB:
167 p += sprintf(p, "PIIX4 Ultra 33 ");
169 case PCI_DEVICE_ID_INTEL_82371SB_1:
170 p += sprintf(p, "PIIX3 ");
172 case PCI_DEVICE_ID_INTEL_82371MX:
173 p += sprintf(p, "MPIIX ");
175 case PCI_DEVICE_ID_INTEL_82371FB_1:
176 case PCI_DEVICE_ID_INTEL_82371FB_0:
178 p += sprintf(p, "PIIX ");
181 p += sprintf(p, "Chipset.\n");
183 if (dev->device == PCI_DEVICE_ID_INTEL_82371MX)
186 pci_read_config_word(dev, 0x40, ®40);
187 pci_read_config_word(dev, 0x42, ®42);
188 pci_read_config_byte(dev, 0x44, ®44);
189 pci_read_config_byte(dev, 0x48, ®48);
190 pci_read_config_byte(dev, 0x4a, ®4a);
191 pci_read_config_byte(dev, 0x4b, ®4b);
192 pci_read_config_byte(dev, 0x54, ®54);
193 pci_read_config_byte(dev, 0x55, ®55);
195 psitre = (reg40 & 0x4000) ? 1 : 0;
196 ssitre = (reg42 & 0x4000) ? 1 : 0;
199 * at that point bibma+0x2 et bibma+0xa are byte registers
202 c0 = inb(bibma + 0x02);
203 c1 = inb(bibma + 0x0a);
205 p += sprintf(p, "--------------- Primary Channel "
206 "---------------- Secondary Channel "
208 p += sprintf(p, " %sabled "
210 (c0&0x80) ? "dis" : " en",
211 (c1&0x80) ? "dis" : " en");
212 p += sprintf(p, "--------------- drive0 --------- drive1 "
213 "-------- drive0 ---------- drive1 ------\n");
214 p += sprintf(p, "DMA enabled: %s %s "
216 (c0&0x20) ? "yes" : "no ",
217 (c0&0x40) ? "yes" : "no ",
218 (c1&0x20) ? "yes" : "no ",
219 (c1&0x40) ? "yes" : "no " );
220 p += sprintf(p, "UDMA enabled: %s %s "
222 (reg48&0x01) ? "yes" : "no ",
223 (reg48&0x02) ? "yes" : "no ",
224 (reg48&0x04) ? "yes" : "no ",
225 (reg48&0x08) ? "yes" : "no " );
226 p += sprintf(p, "UDMA enabled: %s %s "
229 (reg55&0x10) && (reg4a&0x01)) ? "5" :
230 ((reg54&0x11) && (reg4a&0x02)) ? "4" :
231 ((reg54&0x11) && (reg4a&0x01)) ? "3" :
234 (reg4a&0x00) ? "0" : "X",
236 (reg55&0x20) && (reg4a&0x10)) ? "5" :
237 ((reg54&0x22) && (reg4a&0x20)) ? "4" :
238 ((reg54&0x22) && (reg4a&0x10)) ? "3" :
241 (reg4a&0x00) ? "0" : "X",
243 (reg55&0x40) && (reg4b&0x03)) ? "5" :
244 ((reg54&0x44) && (reg4b&0x02)) ? "4" :
245 ((reg54&0x44) && (reg4b&0x01)) ? "3" :
248 (reg4b&0x00) ? "0" : "X",
250 (reg55&0x80) && (reg4b&0x30)) ? "5" :
251 ((reg54&0x88) && (reg4b&0x20)) ? "4" :
252 ((reg54&0x88) && (reg4b&0x10)) ? "3" :
255 (reg4b&0x00) ? "0" : "X");
257 p += sprintf(p, "UDMA\n");
258 p += sprintf(p, "DMA\n");
259 p += sprintf(p, "PIO\n");
262 * FIXME.... Add configuration junk data....blah blah......
265 return p-buffer; /* => must be less than 4k! */
267 #endif /* defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS) */
270 * piix_ratemask - compute rate mask for PIIX IDE
271 * @drive: IDE drive to compute for
273 * Returns the available modes for the PIIX IDE controller.
276 static u8 piix_ratemask (ide_drive_t *drive)
278 struct pci_dev *dev = HWIF(drive)->pci_dev;
281 switch(dev->device) {
282 case PCI_DEVICE_ID_INTEL_82801EB_1:
285 /* UDMA 100 capable */
286 case PCI_DEVICE_ID_INTEL_82801BA_8:
287 case PCI_DEVICE_ID_INTEL_82801BA_9:
288 case PCI_DEVICE_ID_INTEL_82801CA_10:
289 case PCI_DEVICE_ID_INTEL_82801CA_11:
290 case PCI_DEVICE_ID_INTEL_82801E_11:
291 case PCI_DEVICE_ID_INTEL_82801DB_10:
292 case PCI_DEVICE_ID_INTEL_82801DB_11:
293 case PCI_DEVICE_ID_INTEL_82801EB_11:
294 case PCI_DEVICE_ID_INTEL_ESB_2:
295 case PCI_DEVICE_ID_INTEL_ICH6_19:
298 /* UDMA 66 capable */
299 case PCI_DEVICE_ID_INTEL_82801AA_1:
300 case PCI_DEVICE_ID_INTEL_82372FB_1:
303 /* UDMA 33 capable */
304 case PCI_DEVICE_ID_INTEL_82371AB:
305 case PCI_DEVICE_ID_INTEL_82443MX_1:
306 case PCI_DEVICE_ID_INTEL_82451NX:
307 case PCI_DEVICE_ID_INTEL_82801AB_1:
309 /* Non UDMA capable (MWDMA2) */
310 case PCI_DEVICE_ID_INTEL_82371SB_1:
311 case PCI_DEVICE_ID_INTEL_82371FB_1:
312 case PCI_DEVICE_ID_INTEL_82371FB_0:
313 case PCI_DEVICE_ID_INTEL_82371MX:
319 * If we are UDMA66 capable fall back to UDMA33
320 * if the drive cannot see an 80pin cable.
322 if (!eighty_ninty_three(drive))
323 mode = min(mode, (u8)1);
328 * piix_dma_2_pio - return the PIO mode matching DMA
329 * @xfer_rate: transfer speed
331 * Returns the nearest equivalent PIO timing for the PIO or DMA
332 * mode requested by the controller.
335 static u8 piix_dma_2_pio (u8 xfer_rate) {
365 * piix_tune_drive - tune a drive attached to a PIIX
366 * @drive: drive to tune
367 * @pio: desired PIO mode
369 * Set the interface PIO mode based upon the settings done by AMI BIOS
370 * (might be useful if drive is not registered in CMOS for any reason).
372 static void piix_tune_drive (ide_drive_t *drive, u8 pio)
374 ide_hwif_t *hwif = HWIF(drive);
375 struct pci_dev *dev = hwif->pci_dev;
376 int is_slave = (&hwif->drives[1] == drive);
377 int master_port = hwif->channel ? 0x42 : 0x40;
378 int slave_port = 0x44;
383 u8 timings[][2] = { { 0, 0 },
389 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
390 spin_lock_irqsave(&ide_lock, flags);
391 pci_read_config_word(dev, master_port, &master_data);
393 master_data = master_data | 0x4000;
395 /* enable PPE, IE and TIME */
396 master_data = master_data | 0x0070;
397 pci_read_config_byte(dev, slave_port, &slave_data);
398 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
399 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
401 master_data = master_data & 0xccf8;
403 /* enable PPE, IE and TIME */
404 master_data = master_data | 0x0007;
405 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
407 pci_write_config_word(dev, master_port, master_data);
409 pci_write_config_byte(dev, slave_port, slave_data);
410 spin_unlock_irqrestore(&ide_lock, flags);
414 * piix_tune_chipset - tune a PIIX interface
415 * @drive: IDE drive to tune
416 * @xferspeed: speed to configure
418 * Set a PIIX interface channel to the desired speeds. This involves
419 * requires the right timing data into the PIIX configuration space
420 * then setting the drive parameters appropriately
423 static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
425 ide_hwif_t *hwif = HWIF(drive);
426 struct pci_dev *dev = hwif->pci_dev;
427 u8 maslave = hwif->channel ? 0x42 : 0x40;
428 u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed);
429 int a_speed = 3 << (drive->dn * 4);
430 int u_flag = 1 << drive->dn;
431 int v_flag = 0x01 << drive->dn;
432 int w_flag = 0x10 << drive->dn;
435 u16 reg4042, reg44, reg48, reg4a, reg54;
438 pci_read_config_word(dev, maslave, ®4042);
439 sitre = (reg4042 & 0x4000) ? 1 : 0;
440 pci_read_config_word(dev, 0x44, ®44);
441 pci_read_config_word(dev, 0x48, ®48);
442 pci_read_config_word(dev, 0x4a, ®4a);
443 pci_read_config_word(dev, 0x54, ®54);
444 pci_read_config_byte(dev, 0x55, ®55);
448 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
451 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
452 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
455 case XFER_SW_DMA_2: break;
459 case XFER_PIO_0: break;
463 if (speed >= XFER_UDMA_0) {
464 if (!(reg48 & u_flag))
465 pci_write_config_word(dev, 0x48, reg48|u_flag);
466 if (speed == XFER_UDMA_5) {
467 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
469 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
471 if (!(reg4a & u_speed)) {
472 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
473 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
475 if (speed > XFER_UDMA_2) {
476 if (!(reg54 & v_flag)) {
477 pci_write_config_word(dev, 0x54, reg54|v_flag);
480 pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
484 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
486 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
488 pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
490 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
493 piix_tune_drive(drive, piix_dma_2_pio(speed));
494 return (ide_config_drive_speed(drive, speed));
498 * piix_faulty_dma0 - check for DMA0 errata
499 * @hwif: IDE interface to check
501 * If an ICH/ICH0/ICH2 interface is is operating in multi-word
502 * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
503 * inadvertently provide an extra piece of secondary data to the primary
504 * device resulting in data corruption.
506 * With such a device this test function returns true. This allows
507 * our tuning code to follow Intel recommendations and use PIO on
511 static int piix_faulty_dma0(ide_hwif_t *hwif)
513 switch(hwif->pci_dev->device)
515 case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */
516 case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */
517 case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */
518 case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */
525 * piix_config_drive_for_dma - configure drive for DMA
526 * @drive: IDE drive to configure
528 * Set up a PIIX interface channel for the best available speed.
529 * We prefer UDMA if it is available and then MWDMA. If DMA is
530 * not available we switch to PIO and return 0.
533 static int piix_config_drive_for_dma (ide_drive_t *drive)
535 u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
537 /* Some ICH devices cannot support DMA mode 0 */
538 if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
541 /* If no DMA speed was available or the chipset has DMA bugs
542 then disable DMA and use PIO */
544 if (!speed || no_piix_dma) {
545 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
546 speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
549 (void) piix_tune_chipset(drive, speed);
550 return ide_dma_enable(drive);
554 * piix_config_drive_xfer_rate - set up an IDE device
555 * @drive: IDE drive to configure
557 * Set up the PIIX interface for the best available speed on this
558 * interface, preferring DMA to PIO.
561 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
563 ide_hwif_t *hwif = HWIF(drive);
564 struct hd_driveid *id = drive->id;
566 drive->init_speed = 0;
568 if ((id->capability & 1) && drive->autodma) {
569 /* Consult the list of known "bad" drives */
570 if (__ide_dma_bad_drive(drive))
572 if (id->field_valid & 4) {
573 if (id->dma_ultra & hwif->ultra_mask) {
574 /* Force if Capable UltraDMA */
575 if ((id->field_valid & 2) &&
576 (!piix_config_drive_for_dma(drive)))
579 } else if (id->field_valid & 2) {
581 if ((id->dma_mword & hwif->mwdma_mask) ||
582 (id->dma_1word & hwif->swdma_mask)) {
583 /* Force if Capable regular DMA modes */
584 if (!piix_config_drive_for_dma(drive))
587 } else if (__ide_dma_good_drive(drive) &&
588 (id->eide_dma_time < 150)) {
589 /* Consult the list of known "good" drives */
590 if (!piix_config_drive_for_dma(drive))
595 return hwif->ide_dma_on(drive);
596 } else if ((id->capability & 8) || (id->field_valid & 2)) {
599 hwif->tuneproc(drive, 255);
600 return hwif->ide_dma_off_quietly(drive);
602 /* IORDY not supported */
607 * init_chipset_piix - set up the PIIX chipset
608 * @dev: PCI device to set up
609 * @name: Name of the device
611 * Initialize the PCI device as required. For the PIIX this turns
612 * out to be nice and simple
615 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
617 switch(dev->device) {
618 case PCI_DEVICE_ID_INTEL_82801EB_1:
619 case PCI_DEVICE_ID_INTEL_82801AA_1:
620 case PCI_DEVICE_ID_INTEL_82801AB_1:
621 case PCI_DEVICE_ID_INTEL_82801BA_8:
622 case PCI_DEVICE_ID_INTEL_82801BA_9:
623 case PCI_DEVICE_ID_INTEL_82801CA_10:
624 case PCI_DEVICE_ID_INTEL_82801CA_11:
625 case PCI_DEVICE_ID_INTEL_82801DB_10:
626 case PCI_DEVICE_ID_INTEL_82801DB_11:
627 case PCI_DEVICE_ID_INTEL_82801EB_11:
628 case PCI_DEVICE_ID_INTEL_82801E_11:
629 case PCI_DEVICE_ID_INTEL_ESB_2:
630 case PCI_DEVICE_ID_INTEL_ICH6_19:
632 unsigned int extra = 0;
633 pci_read_config_dword(dev, 0x54, &extra);
634 pci_write_config_dword(dev, 0x54, extra|0x400);
640 #if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
641 piix_devs[n_piix_devs++] = dev;
645 ide_pci_create_host_proc("piix", piix_get_info);
647 #endif /* DISPLAY_PIIX_TIMINGS && CONFIG_PROC_FS */
652 * init_hwif_piix - fill in the hwif for the PIIX
653 * @hwif: IDE interface
655 * Set up the ide_hwif_t for the PIIX interface according to the
656 * capabilities of the hardware.
659 static void __init init_hwif_piix (ide_hwif_t *hwif)
661 u8 reg54h = 0, reg55h = 0, ata66 = 0;
662 u8 mask = hwif->channel ? 0xc0 : 0x30;
666 hwif->irq = hwif->channel ? 15 : 14;
667 #endif /* CONFIG_IA64 */
669 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
670 /* This is a painful system best to let it self tune for now */
675 hwif->tuneproc = &piix_tune_drive;
676 hwif->speedproc = &piix_tune_chipset;
677 hwif->drives[0].autotune = 1;
678 hwif->drives[1].autotune = 1;
684 hwif->ultra_mask = 0x3f;
685 hwif->mwdma_mask = 0x06;
686 hwif->swdma_mask = 0x04;
688 switch(hwif->pci_dev->device) {
689 case PCI_DEVICE_ID_INTEL_82371MX:
690 hwif->mwdma_mask = 0x80;
691 hwif->swdma_mask = 0x80;
692 case PCI_DEVICE_ID_INTEL_82371FB_0:
693 case PCI_DEVICE_ID_INTEL_82371FB_1:
694 case PCI_DEVICE_ID_INTEL_82371SB_1:
695 hwif->ultra_mask = 0x80;
697 case PCI_DEVICE_ID_INTEL_82371AB:
698 case PCI_DEVICE_ID_INTEL_82443MX_1:
699 case PCI_DEVICE_ID_INTEL_82451NX:
700 case PCI_DEVICE_ID_INTEL_82801AB_1:
701 hwif->ultra_mask = 0x07;
704 pci_read_config_byte(hwif->pci_dev, 0x54, ®54h);
705 pci_read_config_byte(hwif->pci_dev, 0x55, ®55h);
706 ata66 = (reg54h & mask) ? 1 : 0;
710 if (!(hwif->udma_four))
711 hwif->udma_four = ata66;
712 hwif->ide_dma_check = &piix_config_drive_xfer_rate;
716 hwif->drives[1].autodma = hwif->autodma;
717 hwif->drives[0].autodma = hwif->autodma;
721 * init_setup_piix - callback for IDE initialize
722 * @dev: PIIX PCI device
725 * Enable the xp fixup for the PIIX controller and then perform
726 * a standard ide PCI setup
729 static void __init init_setup_piix (struct pci_dev *dev, ide_pci_device_t *d)
731 ide_setup_pci_device(dev, d);
735 * piix_init_one - called when a PIIX is found
736 * @dev: the piix device
737 * @id: the matching pci id
739 * Called when the PCI registration layer (or the IDE initialization)
740 * finds a device matching our IDE device tables.
743 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
745 ide_pci_device_t *d = &piix_pci_info[id->driver_data];
747 if (dev->device != d->device)
749 d->init_setup(dev, d);
754 * piix_check_450nx - Check for problem 450NX setup
756 * Check for the present of 450NX errata #19 and errata #25. If
757 * they are found, disable use of DMA IDE
760 static void __init piix_check_450nx(void)
762 struct pci_dev *pdev = NULL;
765 while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
767 /* Look for 450NX PXB. Check for problem configurations
768 A PCI quirk checks bit 6 already */
769 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
770 pci_read_config_word(pdev, 0x41, &cfg);
771 /* Only on the original revision: IDE DMA can hang */
774 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
775 else if(cfg & (1<<14) && rev < 5)
779 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
781 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
784 static struct pci_device_id piix_pci_tbl[] = {
785 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
786 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
787 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
788 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
789 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
790 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
791 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
792 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
793 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
794 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
795 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
796 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
797 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
798 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
799 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
800 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
801 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
802 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
803 #ifndef CONFIG_SCSI_SATA
804 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
805 #endif /* !CONFIG_SCSI_SATA */
806 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
807 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
810 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
812 static struct pci_driver driver = {
814 .id_table = piix_pci_tbl,
815 .probe = piix_init_one,
818 static int __init piix_ide_init(void)
821 return ide_pci_register_driver(&driver);
824 module_init(piix_ide_init);
826 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
827 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
828 MODULE_LICENSE("GPL");