2 * linux/drivers/ide/pci/serverworks.c Version 0.8 25 Ebr 2003
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Portions copyright (c) 2001 Sun Microsystems
10 * RCC/ServerWorks IDE driver for Linux
12 * OSB4: `Open South Bridge' IDE Interface (fn 1)
13 * supports UDMA mode 2 (33 MB/s)
15 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
16 * all revisions support UDMA mode 4 (66 MB/s)
17 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
19 * *** The CSB5 does not provide ANY register ***
20 * *** to detect 80-conductor cable presence. ***
22 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
25 * Available under NDA only. Errata info very hard to get.
29 #include <linux/config.h>
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/ioport.h>
34 #include <linux/pci.h>
35 #include <linux/hdreg.h>
36 #include <linux/ide.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
42 #include "serverworks.h"
44 static u8 svwks_revision = 0;
45 static struct pci_dev *isa_dev;
47 #if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS)
48 #include <linux/stat.h>
49 #include <linux/proc_fs.h>
51 static u8 svwks_proc = 0;
52 #define SVWKS_MAX_DEVS 2
53 static struct pci_dev *svwks_devs[SVWKS_MAX_DEVS];
54 static int n_svwks_devs;
56 static int svwks_get_info (char *buffer, char **addr, off_t offset, int count)
62 "ServerWorks OSB4/CSB5/CSB6\n");
64 for (i = 0; i < n_svwks_devs; i++) {
65 struct pci_dev *dev = svwks_devs[i];
66 unsigned long bibma = pci_resource_start(dev, 4);
71 pci_read_config_dword(dev, 0x40, ®40);
72 pci_read_config_dword(dev, 0x44, ®44);
73 pci_read_config_word(dev, 0x48, ®48);
74 pci_read_config_byte(dev, 0x54, ®54);
75 pci_read_config_word(dev, 0x56, ®56);
78 * at that point bibma+0x2 et bibma+0xa are byte registers
81 c0 = inb_p(bibma + 0x02);
82 c1 = inb_p(bibma + 0x0a);
84 p += sprintf(p, "\n ServerWorks ");
86 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
87 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
88 p += sprintf(p, "CSB6 ");
90 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
91 p += sprintf(p, "CSB5 ");
93 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
94 p += sprintf(p, "OSB4 ");
97 p += sprintf(p, "%04x ", dev->device);
100 p += sprintf(p, "Chipset (rev %02x)\n", svwks_revision);
102 p += sprintf(p, "------------------------------- "
104 "---------------------------------\n");
105 p += sprintf(p, "--------------- Primary Channel "
106 "---------------- Secondary Channel "
108 p += sprintf(p, " %sabled"
110 (c0&0x80) ? "dis" : " en",
111 (c1&0x80) ? "dis" : " en");
112 p += sprintf(p, "--------------- drive0 --------- drive1 "
113 "-------- drive0 ---------- drive1 ------\n");
114 p += sprintf(p, "DMA enabled: %s %s"
116 (c0&0x20) ? "yes" : "no ",
117 (c0&0x40) ? "yes" : "no ",
118 (c1&0x20) ? "yes" : "no ",
119 (c1&0x40) ? "yes" : "no " );
120 p += sprintf(p, "UDMA enabled: %s %s"
122 (reg54 & 0x01) ? "yes" : "no ",
123 (reg54 & 0x02) ? "yes" : "no ",
124 (reg54 & 0x04) ? "yes" : "no ",
125 (reg54 & 0x08) ? "yes" : "no " );
126 p += sprintf(p, "UDMA enabled: %s %s"
128 ((reg56&0x0005)==0x0005)?"5":
129 ((reg56&0x0004)==0x0004)?"4":
130 ((reg56&0x0003)==0x0003)?"3":
131 ((reg56&0x0002)==0x0002)?"2":
132 ((reg56&0x0001)==0x0001)?"1":
133 ((reg56&0x000F))?"?":"0",
134 ((reg56&0x0050)==0x0050)?"5":
135 ((reg56&0x0040)==0x0040)?"4":
136 ((reg56&0x0030)==0x0030)?"3":
137 ((reg56&0x0020)==0x0020)?"2":
138 ((reg56&0x0010)==0x0010)?"1":
139 ((reg56&0x00F0))?"?":"0",
140 ((reg56&0x0500)==0x0500)?"5":
141 ((reg56&0x0400)==0x0400)?"4":
142 ((reg56&0x0300)==0x0300)?"3":
143 ((reg56&0x0200)==0x0200)?"2":
144 ((reg56&0x0100)==0x0100)?"1":
145 ((reg56&0x0F00))?"?":"0",
146 ((reg56&0x5000)==0x5000)?"5":
147 ((reg56&0x4000)==0x4000)?"4":
148 ((reg56&0x3000)==0x3000)?"3":
149 ((reg56&0x2000)==0x2000)?"2":
150 ((reg56&0x1000)==0x1000)?"1":
151 ((reg56&0xF000))?"?":"0");
152 p += sprintf(p, "DMA enabled: %s %s"
154 ((reg44&0x00002000)==0x00002000)?"2":
155 ((reg44&0x00002100)==0x00002100)?"1":
156 ((reg44&0x00007700)==0x00007700)?"0":
157 ((reg44&0x0000FF00)==0x0000FF00)?"X":"?",
158 ((reg44&0x00000020)==0x00000020)?"2":
159 ((reg44&0x00000021)==0x00000021)?"1":
160 ((reg44&0x00000077)==0x00000077)?"0":
161 ((reg44&0x000000FF)==0x000000FF)?"X":"?",
162 ((reg44&0x20000000)==0x20000000)?"2":
163 ((reg44&0x21000000)==0x21000000)?"1":
164 ((reg44&0x77000000)==0x77000000)?"0":
165 ((reg44&0xFF000000)==0xFF000000)?"X":"?",
166 ((reg44&0x00200000)==0x00200000)?"2":
167 ((reg44&0x00210000)==0x00210000)?"1":
168 ((reg44&0x00770000)==0x00770000)?"0":
169 ((reg44&0x00FF0000)==0x00FF0000)?"X":"?");
171 p += sprintf(p, "PIO enabled: %s %s"
173 ((reg40&0x00002000)==0x00002000)?"4":
174 ((reg40&0x00002200)==0x00002200)?"3":
175 ((reg40&0x00003400)==0x00003400)?"2":
176 ((reg40&0x00004700)==0x00004700)?"1":
177 ((reg40&0x00005D00)==0x00005D00)?"0":"?",
178 ((reg40&0x00000020)==0x00000020)?"4":
179 ((reg40&0x00000022)==0x00000022)?"3":
180 ((reg40&0x00000034)==0x00000034)?"2":
181 ((reg40&0x00000047)==0x00000047)?"1":
182 ((reg40&0x0000005D)==0x0000005D)?"0":"?",
183 ((reg40&0x20000000)==0x20000000)?"4":
184 ((reg40&0x22000000)==0x22000000)?"3":
185 ((reg40&0x34000000)==0x34000000)?"2":
186 ((reg40&0x47000000)==0x47000000)?"1":
187 ((reg40&0x5D000000)==0x5D000000)?"0":"?",
188 ((reg40&0x00200000)==0x00200000)?"4":
189 ((reg40&0x00220000)==0x00220000)?"3":
190 ((reg40&0x00340000)==0x00340000)?"2":
191 ((reg40&0x00470000)==0x00470000)?"1":
192 ((reg40&0x005D0000)==0x005D0000)?"0":"?");
195 p += sprintf(p, "\n");
197 /* p - buffer must be less than 4k! */
198 len = (p - buffer) - offset;
199 *addr = buffer + offset;
201 return len > count ? count : len;
203 #endif /* defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS) */
205 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
208 if (!strcmp(*list++, drive->id->model))
213 static u8 svwks_ratemask (ide_drive_t *drive)
215 struct pci_dev *dev = HWIF(drive)->pci_dev;
219 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
221 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
224 pci_read_config_dword(isa_dev, 0x64, ®);
227 * Don't enable UDMA on disk devices for the moment
229 if(drive->media == ide_disk)
231 /* Check the OSB4 DMA33 enable bit */
232 return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
233 } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
235 } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
237 pci_read_config_byte(dev, 0x5A, &btr);
239 if (!eighty_ninty_three(drive))
240 mode = min(mode, (u8)1);
241 /* If someone decides to do UDMA133 on CSB5 the same
242 issue will bite so be inclusive */
243 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
246 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
247 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
248 (!(PCI_FUNC(dev->devfn) & 1)))
253 static u8 svwks_csb_check (struct pci_dev *dev)
255 switch (dev->device) {
256 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
257 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
258 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
265 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
267 u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
268 u8 dma_modes[] = { 0x77, 0x21, 0x20 };
269 u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
270 u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
271 u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
273 ide_hwif_t *hwif = HWIF(drive);
274 struct pci_dev *dev = hwif->pci_dev;
276 u8 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
277 u8 unit = (drive->select.b.unit & 0x01);
278 u8 csb5 = svwks_csb_check(dev);
279 u8 ultra_enable = 0, ultra_timing = 0;
280 u8 dma_timing = 0, pio_timing = 0;
283 if (xferspeed == 255) /* PIO auto-tuning */
284 speed = XFER_PIO_0 + pio;
286 speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
288 /* If we are about to put a disk into UDMA mode we screwed up.
289 Our code assumes we never _ever_ do this on an OSB4 */
291 if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
292 drive->media == ide_disk && speed >= XFER_UDMA_0)
295 pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
296 pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
297 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
298 pci_read_config_word(dev, 0x4A, &csb5_pio);
299 pci_read_config_byte(dev, 0x54, &ultra_enable);
301 /* Per Specified Design by OEM, and ASIC Architect */
302 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
303 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
304 if (!drive->init_speed) {
305 u8 dma_stat = hwif->INB(hwif->dma_status);
308 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
309 ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
310 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
312 } else if ((dma_timing) &&
313 ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
314 u8 dmaspeed = dma_timing;
317 if ((dmaspeed & 0x20) == 0x20)
318 dmaspeed = XFER_MW_DMA_2;
319 else if ((dmaspeed & 0x21) == 0x21)
320 dmaspeed = XFER_MW_DMA_1;
321 else if ((dmaspeed & 0x77) == 0x77)
322 dmaspeed = XFER_MW_DMA_0;
325 drive->current_speed = drive->init_speed = dmaspeed;
327 } else if (pio_timing) {
328 u8 piospeed = pio_timing;
331 if ((piospeed & 0x20) == 0x20)
332 piospeed = XFER_PIO_4;
333 else if ((piospeed & 0x22) == 0x22)
334 piospeed = XFER_PIO_3;
335 else if ((piospeed & 0x34) == 0x34)
336 piospeed = XFER_PIO_2;
337 else if ((piospeed & 0x47) == 0x47)
338 piospeed = XFER_PIO_1;
339 else if ((piospeed & 0x5d) == 0x5d)
340 piospeed = XFER_PIO_0;
342 goto oem_setup_failed;
343 drive->current_speed = drive->init_speed = piospeed;
353 ultra_timing &= ~(0x0F << (4*unit));
354 ultra_enable &= ~(0x01 << drive->dn);
355 csb5_pio &= ~(0x0F << (4*drive->dn));
363 pio_timing |= pio_modes[speed - XFER_PIO_0];
364 csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn));
370 pio_timing |= pio_modes[pio];
371 csb5_pio |= (pio << (4*drive->dn));
372 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
381 pio_timing |= pio_modes[pio];
382 csb5_pio |= (pio << (4*drive->dn));
383 dma_timing |= dma_modes[2];
384 ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
385 ultra_enable |= (0x01 << drive->dn);
390 pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
392 pci_write_config_word(dev, 0x4A, csb5_pio);
394 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
395 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
396 pci_write_config_byte(dev, 0x54, ultra_enable);
398 return (ide_config_drive_speed(drive, speed));
401 static void config_chipset_for_pio (ide_drive_t *drive)
403 u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
404 u16 xfer_pio = drive->id->eide_pio_modes;
405 u8 timing, speed, pio;
407 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
412 if (drive->id->eide_pio_iordy > 0)
415 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
418 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
419 (drive->id->eide_pio_modes & 2) ? 0x04 :
420 (drive->id->eide_pio_modes & 1) ? 0x03 :
421 (drive->id->tPIO & 2) ? 0x02 :
422 (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
424 timing = (xfer_pio >= pio) ? xfer_pio : pio;
427 case 4: speed = XFER_PIO_4;break;
428 case 3: speed = XFER_PIO_3;break;
429 case 2: speed = XFER_PIO_2;break;
430 case 1: speed = XFER_PIO_1;break;
432 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
435 (void) svwks_tune_chipset(drive, speed);
436 drive->current_speed = speed;
439 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
442 (void) svwks_tune_chipset(drive, 255);
444 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
447 static int config_chipset_for_dma (ide_drive_t *drive)
449 u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
452 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
454 (void) svwks_tune_chipset(drive, speed);
455 return ide_dma_enable(drive);
458 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
460 ide_hwif_t *hwif = HWIF(drive);
461 struct hd_driveid *id = drive->id;
463 drive->init_speed = 0;
465 if ((id->capability & 1) && drive->autodma) {
466 /* Consult the list of known "bad" drives */
467 if (__ide_dma_bad_drive(drive))
469 if (id->field_valid & 4) {
470 if (id->dma_ultra & hwif->ultra_mask) {
471 /* Force if Capable UltraDMA */
472 int dma = config_chipset_for_dma(drive);
473 if ((id->field_valid & 2) && !dma)
476 /* UDMA disabled by mask, try other DMA modes */
478 } else if (id->field_valid & 2) {
480 if ((id->dma_mword & hwif->mwdma_mask) ||
481 (id->dma_1word & hwif->swdma_mask)) {
482 /* Force if Capable regular DMA modes */
483 if (!config_chipset_for_dma(drive))
486 } else if (__ide_dma_good_drive(drive) &&
487 (id->eide_dma_time < 150)) {
488 /* Consult the list of known "good" drives */
489 if (!config_chipset_for_dma(drive))
494 return hwif->ide_dma_on(drive);
495 } else if ((id->capability & 8) || (id->field_valid & 2)) {
498 config_chipset_for_pio(drive);
499 // hwif->tuneproc(drive, 5);
500 return hwif->ide_dma_off_quietly(drive);
502 /* IORDY not supported */
506 /* This can go soon */
508 static int svwks_ide_dma_end (ide_drive_t *drive)
510 return __ide_dma_end(drive);
513 static unsigned int __init init_chipset_svwks (struct pci_dev *dev, const char *name)
518 /* save revision id to determine DMA capability */
519 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
521 /* force Master Latency Timer value to 64 PCICLKs */
522 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
524 /* OSB4 : South Bridge and IDE */
525 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
526 isa_dev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
527 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
529 pci_read_config_dword(isa_dev, 0x64, ®);
530 reg &= ~0x00002000; /* disable 600ns interrupt mask */
531 if(!(reg & 0x00004000))
532 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
533 reg |= 0x00004000; /* enable UDMA/33 support */
534 pci_write_config_dword(isa_dev, 0x64, reg);
538 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
539 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
540 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
541 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
543 /* Third Channel Test */
544 if (!(PCI_FUNC(dev->devfn) & 1)) {
545 struct pci_dev * findev = NULL;
547 findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
548 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
550 pci_read_config_dword(findev, 0x4C, ®4c);
551 reg4c &= ~0x000007FF;
554 pci_write_config_dword(findev, 0x4C, reg4c);
556 outb_p(0x06, 0x0c00);
557 dev->irq = inb_p(0x0c01);
559 printk("%s: device class (0x%04x)\n",
561 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
562 dev->class &= ~0x000F0F00;
563 // dev->class |= ~0x00000400;
564 dev->class |= ~0x00010100;
569 struct pci_dev * findev = NULL;
572 findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
573 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
575 pci_read_config_byte(findev, 0x41, ®41);
577 pci_write_config_byte(findev, 0x41, reg41);
580 * This is a device pin issue on CSB6.
581 * Since there will be a future raid mode,
582 * early versions of the chipset require the
583 * interrupt pin to be set, and it is a compatibility
586 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
589 // pci_read_config_dword(dev, 0x40, &pioreg)
590 // pci_write_config_dword(dev, 0x40, 0x99999999);
591 // pci_read_config_dword(dev, 0x44, &dmareg);
592 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
593 /* setup the UDMA Control register
595 * 1. clear bit 6 to enable DMA
596 * 2. enable DMA modes with bits 0-1
600 * 11 : udma2/udma4/udma5
602 pci_read_config_byte(dev, 0x5A, &btr);
604 if (!(PCI_FUNC(dev->devfn) & 1))
607 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
608 pci_write_config_byte(dev, 0x5A, btr);
612 #if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS)
613 svwks_devs[n_svwks_devs++] = dev;
617 ide_pci_create_host_proc("svwks", svwks_get_info);
619 #endif /* DISPLAY_SVWKS_TIMINGS && CONFIG_PROC_FS */
621 return (dev->irq) ? dev->irq : 0;
624 static unsigned int __init ata66_svwks_svwks (ide_hwif_t *hwif)
629 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
630 * of the subsystem device ID indicate presence of an 80-pin cable.
631 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
632 * Bit 15 set = secondary IDE channel has 80-pin cable.
633 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
634 * Bit 14 set = primary IDE channel has 80-pin cable.
636 static unsigned int __init ata66_svwks_dell (ide_hwif_t *hwif)
638 struct pci_dev *dev = hwif->pci_dev;
639 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
640 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
641 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
642 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
643 return ((1 << (hwif->channel + 14)) &
644 dev->subsystem_device) ? 1 : 0;
648 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
649 * detect issue by attaching the drives directly to the board.
650 * This check follows the Dell precedent (how scary is that?!)
652 * WARNING: this only works on Alpine hardware!
654 static unsigned int __init ata66_svwks_cobalt (ide_hwif_t *hwif)
656 struct pci_dev *dev = hwif->pci_dev;
657 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
658 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
659 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
660 return ((1 << (hwif->channel + 14)) &
661 dev->subsystem_device) ? 1 : 0;
665 static unsigned int __init ata66_svwks (ide_hwif_t *hwif)
667 struct pci_dev *dev = hwif->pci_dev;
669 /* Per Specified Design by OEM, and ASIC Architect */
670 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
671 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
675 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
676 return ata66_svwks_svwks (hwif);
679 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
680 return ata66_svwks_dell (hwif);
683 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
684 return ata66_svwks_cobalt (hwif);
690 static void __init init_hwif_svwks (ide_hwif_t *hwif)
695 hwif->irq = hwif->channel ? 15 : 14;
697 hwif->tuneproc = &svwks_tune_drive;
698 hwif->speedproc = &svwks_tune_chipset;
702 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
703 hwif->ultra_mask = 0x3f;
705 hwif->mwdma_mask = 0x07;
707 hwif->swdma_mask = 0x07;
708 #endif /* CAN_SW_DMA */
712 if (!hwif->dma_base) {
713 hwif->drives[0].autotune = 1;
714 hwif->drives[1].autotune = 1;
718 hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
719 if (hwif->pci_dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
720 hwif->ide_dma_end = &svwks_ide_dma_end;
721 else if (!(hwif->udma_four))
722 hwif->udma_four = ata66_svwks(hwif);
726 dma_stat = hwif->INB(hwif->dma_status);
727 hwif->drives[0].autodma = (dma_stat & 0x20);
728 hwif->drives[1].autodma = (dma_stat & 0x40);
729 hwif->drives[0].autotune = (!(dma_stat & 0x20));
730 hwif->drives[1].autotune = (!(dma_stat & 0x40));
731 // hwif->drives[0].autodma = hwif->autodma;
732 // hwif->drives[1].autodma = hwif->autodma;
736 * We allow the BM-DMA driver to only work on enabled interfaces.
738 static void __init init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase)
740 struct pci_dev *dev = hwif->pci_dev;
742 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
743 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
744 (!(PCI_FUNC(dev->devfn) & 1)) && (hwif->channel))
747 ide_setup_dma(hwif, dmabase, 8);
750 static void __init init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
752 ide_setup_pci_device(dev, d);
755 static void __init init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
757 if (!(PCI_FUNC(dev->devfn) & 1)) {
758 d->bootable = NEVER_BOARD;
759 if (dev->resource[0].start == 0x01f1)
760 d->bootable = ON_BOARD;
763 if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_CSB6) &&
764 (!(PCI_FUNC(dev->devfn) & 1)))
765 d->autodma = AUTODMA;
768 d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
769 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
770 (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
772 ide_setup_pci_device(dev, d);
777 * svwks_init_one - called when a OSB/CSB is found
778 * @dev: the svwks device
779 * @id: the matching pci id
781 * Called when the PCI registration layer (or the IDE initialization)
782 * finds a device matching our IDE device tables.
785 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
787 ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
789 d->init_setup(dev, d);
793 static struct pci_device_id svwks_pci_tbl[] = {
794 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
795 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
796 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
797 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
800 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
802 static struct pci_driver driver = {
803 .name = "Serverworks_IDE",
804 .id_table = svwks_pci_tbl,
805 .probe = svwks_init_one,
808 static int svwks_ide_init(void)
810 return ide_pci_register_driver(&driver);
813 module_init(svwks_ide_init);
815 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
816 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
817 MODULE_LICENSE("GPL");