2 * Copyright (c) 2003 Silicon Graphics, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
17 * Mountain View, CA 94043, or:
21 * For further information regarding this notice, see:
23 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/hdreg.h>
31 #include <linux/init.h>
32 #include <linux/kernel.h>
33 #include <linux/timer.h>
35 #include <linux/ioport.h>
36 #include <linux/blkdev.h>
39 #include <linux/ide.h>
41 /* IOC4 Specific Definitions */
42 #define IOC4_CMD_OFFSET 0x100
43 #define IOC4_CTRL_OFFSET 0x120
44 #define IOC4_DMA_OFFSET 0x140
45 #define IOC4_INTR_OFFSET 0x0
47 #define IOC4_TIMING 0x00
48 #define IOC4_DMA_PTR_L 0x01
49 #define IOC4_DMA_PTR_H 0x02
50 #define IOC4_DMA_ADDR_L 0x03
51 #define IOC4_DMA_ADDR_H 0x04
52 #define IOC4_BC_DEV 0x05
53 #define IOC4_BC_MEM 0x06
54 #define IOC4_DMA_CTRL 0x07
55 #define IOC4_DMA_END_ADDR 0x08
57 /* Bits in the IOC4 Control/Status Register */
58 #define IOC4_S_DMA_START 0x01
59 #define IOC4_S_DMA_STOP 0x02
60 #define IOC4_S_DMA_DIR 0x04
61 #define IOC4_S_DMA_ACTIVE 0x08
62 #define IOC4_S_DMA_ERROR 0x10
63 #define IOC4_ATA_MEMERR 0x02
65 /* Read/Write Directions */
66 #define IOC4_DMA_WRITE 0x04
67 #define IOC4_DMA_READ 0x00
69 /* Interrupt Register Offsets */
70 #define IOC4_INTR_REG 0x03
71 #define IOC4_INTR_SET 0x05
72 #define IOC4_INTR_CLEAR 0x07
74 #define IOC4_IDE_CACHELINE_SIZE 128
75 #define IOC4_CMD_CTL_BLK_SIZE 0x20
76 #define IOC4_SUPPORTED_FIRMWARE_REV 46
90 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
91 /* IOC4 has only 1 IDE channel */
92 #define IOC4_PRD_BYTES 16
93 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
97 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
98 unsigned long ctrl_port, unsigned long irq_port)
100 unsigned long reg = data_port;
103 /* Registers are word (32 bit) aligned */
104 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
105 hw->io_ports[i] = reg + i * 4;
108 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
111 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
115 sgiioc4_maskproc(ide_drive_t * drive, int mask)
117 ide_hwif_t *hwif = HWIF(drive);
118 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
124 sgiioc4_checkirq(ide_hwif_t * hwif)
127 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4);
137 sgiioc4_clearirq(ide_drive_t * drive)
140 ide_hwif_t *hwif = HWIF(drive);
141 unsigned long other_ir =
142 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
144 /* Code to check for PCI error conditions */
145 intr_reg = hwif->INL(other_ir);
146 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
148 * Using hwif->INB to read the IDE_STATUS_REG has a side effect
149 * of clearing the interrupt. The first read should clear it
150 * if it is set. The second read should return a "clear" status
151 * if it got cleared. If not, then spin for a bit trying to
154 u8 stat = hwif->INB(IDE_STATUS_REG);
156 stat = hwif->INB(IDE_STATUS_REG);
157 while ((stat & 0x80) && (count++ < 100)) {
159 stat = hwif->INB(IDE_STATUS_REG);
162 if (intr_reg & 0x02) {
163 /* Error when transferring DMA data on PCI bus */
164 u32 pci_err_addr_low, pci_err_addr_high,
168 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET]);
170 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + 4);
171 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
174 "%s(%s) : PCI Bus Error when doing DMA:"
175 " status-cmd reg is 0x%x\n",
176 __FUNCTION__, drive->name, pci_stat_cmd_reg);
178 "%s(%s) : PCI Error Address is 0x%x%x\n",
179 __FUNCTION__, drive->name,
180 pci_err_addr_high, pci_err_addr_low);
181 /* Clear the PCI Error indicator */
182 pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
186 /* Clear the Interrupt, Error bits on the IOC4 */
187 hwif->OUTL(0x03, other_ir);
189 intr_reg = hwif->INL(other_ir);
196 sgiioc4_ide_dma_begin(ide_drive_t * drive)
198 ide_hwif_t *hwif = HWIF(drive);
199 unsigned int reg = hwif->INL(hwif->dma_base + IOC4_DMA_CTRL * 4);
200 unsigned int temp_reg = reg | IOC4_S_DMA_START;
202 hwif->OUTL(temp_reg, hwif->dma_base + IOC4_DMA_CTRL * 4);
208 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
214 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
215 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
217 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
222 /* Stops the IOC4 DMA Engine */
224 sgiioc4_ide_dma_end(ide_drive_t * drive)
226 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
227 ide_hwif_t *hwif = HWIF(drive);
228 u64 dma_base = hwif->dma_base;
230 unsigned long *ending_dma = (unsigned long *) hwif->dma_base2;
232 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
234 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
236 if (ioc4_dma & IOC4_S_DMA_STOP) {
238 "%s(%s): IOC4 DMA STOP bit is still 1 :"
239 "ioc4_dma_reg 0x%x\n",
240 __FUNCTION__, drive->name, ioc4_dma);
245 * The IOC4 will DMA 1's to the ending dma area to indicate that
246 * previous data DMA is complete. This is necessary because of relaxed
247 * ordering between register reads and DMA writes on the Altix.
249 while ((cnt++ < 200) && (!valid)) {
250 for (num = 0; num < 16; num++) {
251 if (ending_dma[num]) {
259 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
264 bc_dev = hwif->INL(dma_base + IOC4_BC_DEV * 4);
265 bc_mem = hwif->INL(dma_base + IOC4_BC_MEM * 4);
267 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
268 if (bc_dev > bc_mem + 8) {
270 "%s(%s): WARNING!! byte_count_dev %d "
271 "!= byte_count_mem %d\n",
272 __FUNCTION__, drive->name, bc_dev, bc_mem);
276 drive->waiting_for_dma = 0;
277 ide_destroy_dmatable(drive);
283 sgiioc4_ide_dma_check(ide_drive_t * drive)
285 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) {
287 "Couldnot set %s in Multimode-2 DMA mode | "
288 "Drive %s using PIO instead\n",
289 drive->name, drive->name);
290 drive->using_dma = 0;
292 drive->using_dma = 1;
298 sgiioc4_ide_dma_on(ide_drive_t * drive)
300 drive->using_dma = 1;
302 return HWIF(drive)->ide_dma_host_on(drive);
306 sgiioc4_ide_dma_off_quietly(ide_drive_t * drive)
308 drive->using_dma = 0;
310 return HWIF(drive)->ide_dma_host_off(drive);
313 /* returns 1 if dma irq issued, 0 otherwise */
315 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
317 return sgiioc4_checkirq(HWIF(drive));
321 sgiioc4_ide_dma_host_on(ide_drive_t * drive)
323 if (drive->using_dma)
330 sgiioc4_ide_dma_host_off(ide_drive_t * drive)
332 sgiioc4_clearirq(drive);
338 sgiioc4_ide_dma_verbose(ide_drive_t * drive)
340 if (drive->using_dma == 1)
341 printk(", UDMA(16)");
349 sgiioc4_ide_dma_lostirq(ide_drive_t * drive)
351 HWIF(drive)->resetproc(drive);
353 return __ide_dma_lostirq(drive);
357 sgiioc4_resetproc(ide_drive_t * drive)
359 sgiioc4_ide_dma_end(drive);
360 sgiioc4_clearirq(drive);
364 sgiioc4_INB(unsigned long port)
366 u8 reg = (u8) inb(port);
368 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
369 if (reg & 0x51) { /* Not busy...check for interrupt */
370 unsigned long other_ir = port - 0x110;
371 unsigned int intr_reg = (u32) inl(other_ir);
373 /* Clear the Interrupt, Error bits on the IOC4 */
374 if (intr_reg & 0x03) {
375 outl(0x03, other_ir);
376 intr_reg = (u32) inl(other_ir);
384 /* Creates a dma map for the scatter-gather list entries */
386 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
388 int num_ports = sizeof (ioc4_dma_regs_t);
390 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
391 dma_base, dma_base + num_ports - 1);
393 if (!request_region(dma_base, num_ports, hwif->name)) {
395 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
397 __FUNCTION__, hwif->name, (void *) dma_base,
398 (void *) dma_base + num_ports - 1);
399 goto dma_alloc_failure;
402 hwif->dma_base = dma_base;
403 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
404 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
405 &hwif->dmatable_dma);
407 if (!hwif->dmatable_cpu)
408 goto dma_alloc_failure;
411 kmalloc(sizeof (struct scatterlist) * IOC4_PRD_ENTRIES, GFP_KERNEL);
414 goto dma_sgalloc_failure;
416 hwif->dma_base2 = (unsigned long)
417 pci_alloc_consistent(hwif->pci_dev,
418 IOC4_IDE_CACHELINE_SIZE,
419 (dma_addr_t *) &(hwif->dma_status));
421 if (!hwif->dma_base2)
422 goto dma_base2alloc_failure;
426 dma_base2alloc_failure:
427 kfree(hwif->sg_table);
430 pci_free_consistent(hwif->pci_dev,
431 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
432 hwif->dmatable_cpu, hwif->dmatable_dma);
434 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
435 __FUNCTION__, hwif->name);
437 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
440 /* Disable DMA because we couldnot allocate any DMA maps */
445 /* Initializes the IOC4 DMA Engine */
447 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
450 ide_hwif_t *hwif = HWIF(drive);
451 u64 dma_base = hwif->dma_base;
452 u32 dma_addr, ending_dma_addr;
454 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
456 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
458 "%s(%s):Warning!! DMA from previous transfer was still active\n",
459 __FUNCTION__, drive->name);
460 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
461 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
463 if (ioc4_dma & IOC4_S_DMA_STOP)
465 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
466 __FUNCTION__, drive->name);
469 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
470 if (ioc4_dma & IOC4_S_DMA_ERROR) {
472 "%s(%s) : Warning!! - DMA Error during Previous"
473 " transfer | status 0x%x\n",
474 __FUNCTION__, drive->name, ioc4_dma);
475 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
476 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
478 if (ioc4_dma & IOC4_S_DMA_STOP)
480 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
481 __FUNCTION__, drive->name);
484 /* Address of the Scatter Gather List */
485 dma_addr = cpu_to_le32(hwif->dmatable_dma);
486 hwif->OUTL(dma_addr, dma_base + IOC4_DMA_PTR_L * 4);
488 /* Address of the Ending DMA */
489 memset((unsigned int *) hwif->dma_base2, 0, IOC4_IDE_CACHELINE_SIZE);
490 ending_dma_addr = cpu_to_le32(hwif->dma_status);
491 hwif->OUTL(ending_dma_addr, dma_base + IOC4_DMA_END_ADDR * 4);
493 hwif->OUTL(dma_direction, dma_base + IOC4_DMA_CTRL * 4);
494 drive->waiting_for_dma = 1;
497 /* IOC4 Scatter Gather list Format */
498 /* 128 Bit entries to support 64 bit addresses in the future */
499 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
500 /* --------------------------------------------------------------------- */
501 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
502 /* --------------------------------------------------------------------- */
503 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
504 /* --------------------------------------------------------------------- */
505 /* Creates the scatter gather list, DMA Table */
507 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
509 ide_hwif_t *hwif = HWIF(drive);
510 unsigned int *table = hwif->dmatable_cpu;
511 unsigned int count = 0, i = 1;
512 struct scatterlist *sg;
514 if (HWGROUP(drive)->rq->flags & REQ_DRIVE_TASKFILE)
515 hwif->sg_nents = i = ide_raw_build_sglist(drive, rq);
517 hwif->sg_nents = i = ide_build_sglist(drive, rq);
520 return 0; /* sglist of length Zero */
523 while (i && sg_dma_len(sg)) {
526 cur_addr = sg_dma_address(sg);
527 cur_len = sg_dma_len(sg);
530 if (count++ >= IOC4_PRD_ENTRIES) {
532 "%s: DMA table too small\n",
534 goto use_pio_instead;
537 0x10000 - (cur_addr & 0xffff);
539 if (bcount > cur_len)
542 /* put the addr, length in
543 * the IOC4 dma-table format */
546 *table = cpu_to_be32(cur_addr);
551 xcount = bcount & 0xffff;
552 *table = cpu_to_be32(xcount);
566 *table |= cpu_to_be32(0x80000000);
571 pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
572 hwif->sg_dma_direction);
574 return 0; /* revert to PIO for this request */
578 sgiioc4_ide_dma_read(ide_drive_t * drive)
580 struct request *rq = HWGROUP(drive)->rq;
581 unsigned int count = 0;
583 if (!(count = sgiioc4_build_dma_table(drive, rq, PCI_DMA_FROMDEVICE))) {
584 /* try PIO instead of DMA */
587 /* Writes FROM the IOC4 TO Main Memory */
588 sgiioc4_configure_for_dma(IOC4_DMA_WRITE, drive);
594 sgiioc4_ide_dma_write(ide_drive_t * drive)
596 struct request *rq = HWGROUP(drive)->rq;
597 unsigned int count = 0;
599 if (!(count = sgiioc4_build_dma_table(drive, rq, PCI_DMA_TODEVICE))) {
600 /* try PIO instead of DMA */
604 sgiioc4_configure_for_dma(IOC4_DMA_READ, drive);
605 /* Writes TO the IOC4 FROM Main Memory */
611 ide_init_sgiioc4(ide_hwif_t * hwif)
616 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
617 hwif->mwdma_mask = 0x2; /* Multimode-2 DMA */
618 hwif->swdma_mask = 0x2;
619 hwif->identify = NULL;
620 hwif->tuneproc = NULL; /* Sets timing for PIO mode */
621 hwif->speedproc = NULL; /* Sets timing for DMA &/or PIO modes */
622 hwif->selectproc = NULL;/* Use the default routine to select drive */
623 hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
624 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
625 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
627 hwif->intrproc = NULL; /* Enable or Disable interrupt from drive */
628 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
629 hwif->quirkproc = NULL;
630 hwif->busproc = NULL;
632 hwif->ide_dma_read = &sgiioc4_ide_dma_read;
633 hwif->ide_dma_write = &sgiioc4_ide_dma_write;
634 hwif->ide_dma_begin = &sgiioc4_ide_dma_begin;
635 hwif->ide_dma_end = &sgiioc4_ide_dma_end;
636 hwif->ide_dma_check = &sgiioc4_ide_dma_check;
637 hwif->ide_dma_on = &sgiioc4_ide_dma_on;
638 hwif->ide_dma_off_quietly = &sgiioc4_ide_dma_off_quietly;
639 hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
640 hwif->ide_dma_host_on = &sgiioc4_ide_dma_host_on;
641 hwif->ide_dma_host_off = &sgiioc4_ide_dma_host_off;
642 hwif->ide_dma_verbose = &sgiioc4_ide_dma_verbose;
643 hwif->ide_dma_lostirq = &sgiioc4_ide_dma_lostirq;
644 hwif->ide_dma_timeout = &__ide_dma_timeout;
645 hwif->INB = &sgiioc4_INB;
649 sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
651 unsigned long base, ctl, dma_base, irqport;
655 for (h = 0; h < MAX_HWIFS; ++h) {
656 hwif = &ide_hwifs[h];
657 /* Find an empty HWIF */
658 if (hwif->chipset == ide_unknown)
662 /* Get the CmdBlk and CtrlBlk Base Registers */
663 base = pci_resource_start(dev, 0) + IOC4_CMD_OFFSET;
664 ctl = pci_resource_start(dev, 0) + IOC4_CTRL_OFFSET;
665 irqport = pci_resource_start(dev, 0) + IOC4_INTR_OFFSET;
666 dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
668 if (!request_region(base, IOC4_CMD_CTL_BLK_SIZE, hwif->name)) {
670 "%s : %s -- ERROR, Port Addresses "
671 "0x%p to 0x%p ALREADY in use\n",
672 __FUNCTION__, hwif->name, (void *) base,
673 (void *) base + IOC4_CMD_CTL_BLK_SIZE);
677 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
678 /* Initialize the IO registers */
679 sgiioc4_init_hwif_ports(&hwif->hw, base, ctl, irqport);
680 memcpy(hwif->io_ports, hwif->hw.io_ports,
681 sizeof (hwif->io_ports));
682 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
685 hwif->irq = dev->irq;
686 hwif->chipset = ide_pci;
688 hwif->channel = 0; /* Single Channel chip */
689 hwif->cds = (struct ide_pci_device_s *) d;
690 hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
692 /* Initializing chipset IRQ Registers */
693 hwif->OUTL(0x03, irqport + IOC4_INTR_SET * 4);
695 ide_init_sgiioc4(hwif);
698 ide_dma_sgiioc4(hwif, dma_base);
700 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
701 hwif->name, d->name);
703 probe_hwif_init(hwif);
705 /* Create /proc/ide entries */
706 create_proc_ide_interfaces();
711 static unsigned int __init
712 pci_init_sgiioc4(struct pci_dev *dev, ide_pci_device_t * d)
714 unsigned int class_rev;
716 if (pci_enable_device(dev)) {
718 "Failed to enable device %s at slot %s\n",
719 d->name, dev->slot_name);
724 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
726 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
727 d->name, dev->slot_name, class_rev);
728 if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) {
729 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
730 "firmware is obsolete - please upgrade to revision"
731 "46 or higher\n", d->name, dev->slot_name);
735 return sgiioc4_ide_setup_pci_device(dev, d);
738 static ide_pci_device_t sgiioc4_chipsets[] __devinitdata = {
742 .init_hwif = ide_init_sgiioc4,
743 .init_dma = ide_dma_sgiioc4,
746 /* SGI IOC4 doesn't have enablebits. */
747 .bootable = ON_BOARD,
752 sgiioc4_init_one(struct pci_dev *dev, const struct pci_device_id *id)
754 pci_init_sgiioc4(dev, &sgiioc4_chipsets[id->driver_data]);
758 static struct pci_device_id sgiioc4_pci_tbl[] = {
759 {PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC4, PCI_ANY_ID,
760 PCI_ANY_ID, 0x0b4000, 0xFFFFFF, 0},
763 MODULE_DEVICE_TABLE(pci, sgiioc4_pci_tbl);
765 static struct pci_driver driver = {
766 .name = "SGI-IOC4_IDE",
767 .id_table = sgiioc4_pci_tbl,
768 .probe = sgiioc4_init_one,
772 sgiioc4_ide_init(void)
774 return ide_pci_register_driver(&driver);
777 module_init(sgiioc4_ide_init);
779 MODULE_AUTHOR("Aniket Malatpure - Silicon Graphics Inc. (SGI)");
780 MODULE_DESCRIPTION("PCI driver module for SGI IOC4 Base-IO Card");
781 MODULE_LICENSE("GPL");