2 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation available under NDA only
13 * If you are using Marvell SATA-IDE adapters with Maxtor drives
14 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
16 * If you are using WD drives with SATA bridges you must set the
17 * drive to "Single". "Master" will hang
19 * If you have strange problems with nVidia chipset systems please
20 * see the SI support documentation and update your system BIOS
24 #include <linux/config.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
35 #undef SIIMAGE_VIRTUAL_DMAPIO
36 #undef SIIMAGE_LARGE_DMA
39 * pdev_is_sata - check if device is SATA
40 * @pdev: PCI device to check
42 * Returns true if this is a SATA controller
45 static int pdev_is_sata(struct pci_dev *pdev)
49 case PCI_DEVICE_ID_SII_3112:
50 case PCI_DEVICE_ID_SII_1210SA:
51 case PCI_DEVICE_ID_ATI_IXP300_SATA:
52 case PCI_DEVICE_ID_ATI_IXP400_SATA:
54 case PCI_DEVICE_ID_SII_680:
62 * is_sata - check if hwif is SATA
63 * @hwif: interface to check
65 * Returns true if this is a SATA controller
68 static inline int is_sata(ide_hwif_t *hwif)
70 return pdev_is_sata(hwif->pci_dev);
74 * siimage_selreg - return register base
78 * Turn a config register offset into the right address in either
79 * PCI space or MMIO space to access the control register in question
80 * Thankfully this is a configuration operation so isnt performance
84 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
86 unsigned long base = (unsigned long)hwif->hwif_data;
89 base += (hwif->channel << 6);
91 base += (hwif->channel << 4);
96 * siimage_seldev - return register base
100 * Turn a config register offset into the right address in either
101 * PCI space or MMIO space to access the control register in question
102 * including accounting for the unit shift.
105 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
107 ide_hwif_t *hwif = HWIF(drive);
108 unsigned long base = (unsigned long)hwif->hwif_data;
111 base += (hwif->channel << 6);
113 base += (hwif->channel << 4);
114 base |= drive->select.b.unit << drive->select.b.unit;
119 * siimage_ratemask - Compute available modes
122 * Compute the available speeds for the devices on the interface.
123 * For the CMD680 this depends on the clocking mode (scsc), for the
124 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
125 * as a limit if there is no 80pin cable present.
128 static byte siimage_ratemask (ide_drive_t *drive)
130 ide_hwif_t *hwif = HWIF(drive);
131 u8 mode = 0, scsc = 0;
132 unsigned long base = (unsigned long) hwif->hwif_data;
135 scsc = hwif->INB(base + 0x4A);
137 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
141 if(strstr(drive->id->model, "Maxtor"))
146 if ((scsc & 0x30) == 0x10) /* 133 */
148 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
150 else if ((scsc & 0x30) == 0x00) /* 100 */
152 else /* Disabled ? */
155 if (!eighty_ninty_three(drive))
156 mode = min(mode, (u8)1);
161 * siimage_taskfile_timing - turn timing data to a mode
162 * @hwif: interface to query
164 * Read the timing data for the interface and return the
165 * mode that is being used.
168 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
171 unsigned long addr = siimage_selreg(hwif, 2);
174 timing = hwif->INW(addr);
176 pci_read_config_word(hwif->pci_dev, addr, &timing);
179 case 0x10c1: return 4;
180 case 0x10c3: return 3;
182 case 0x1281: return 2;
183 case 0x2283: return 1;
190 * simmage_tuneproc - tune a drive
191 * @drive: drive to tune
192 * @mode_wanted: the target operating mode
194 * Load the timing settings for this device mode into the
195 * controller. If we are in PIO mode 3 or 4 turn on IORDY
196 * monitoring (bit 9). The TF timing is bits 31:16
199 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
201 ide_hwif_t *hwif = HWIF(drive);
204 unsigned long addr = siimage_seldev(drive, 0x04);
205 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
207 /* cheat for now and use the docs */
208 switch(mode_wanted) {
233 hwif->OUTW(speedt, addr);
234 hwif->OUTW(speedp, tfaddr);
235 /* Now set up IORDY */
236 if(mode_wanted == 3 || mode_wanted == 4)
237 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
239 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
243 pci_write_config_word(hwif->pci_dev, addr, speedp);
244 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
245 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
247 /* Set IORDY for mode 3 or 4 */
248 if(mode_wanted == 3 || mode_wanted == 4)
250 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
255 * config_siimage_chipset_for_pio - set drive timings
256 * @drive: drive to tune
259 * Compute the best pio mode we can for a given device. Also honour
260 * the timings for the driver when dealing with mixed devices. Some
261 * of this is ugly but its all wrapped up here
263 * The SI680 can also do VDMA - we need to start using that
265 * FIXME: we use the BIOS channel timings to avoid driving the task
266 * files too fast at the disk. We need to compute the master/slave
267 * drive PIO mode properly so that we can up the speed on a hotplug
271 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
273 u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
274 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
276 /* WARNING PIO timing mess is going to happen b/w devices, argh */
277 if ((channel_timings != set_pio) && (set_pio > channel_timings))
278 set_pio = channel_timings;
280 siimage_tuneproc(drive, set_pio);
281 speed = XFER_PIO_0 + set_pio;
283 (void) ide_config_drive_speed(drive, speed);
286 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
288 config_siimage_chipset_for_pio(drive, set_speed);
292 * siimage_tune_chipset - set controller timings
293 * @drive: Drive to set up
294 * @xferspeed: speed we want to achieve
296 * Tune the SII chipset for the desired mode. If we can't achieve
297 * the desired mode then tune for a lower one, but ultimately
298 * make the thing work.
301 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
303 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
304 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
305 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
307 ide_hwif_t *hwif = HWIF(drive);
308 u16 ultra = 0, multi = 0;
309 u8 mode = 0, unit = drive->select.b.unit;
310 u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed);
311 unsigned long base = (unsigned long)hwif->hwif_data;
312 u8 scsc = 0, addr_mask = ((hwif->channel) ?
313 ((hwif->mmio) ? 0xF4 : 0x84) :
314 ((hwif->mmio) ? 0xB4 : 0x80));
316 unsigned long ma = siimage_seldev(drive, 0x08);
317 unsigned long ua = siimage_seldev(drive, 0x0C);
320 scsc = hwif->INB(base + 0x4A);
321 mode = hwif->INB(base + addr_mask);
322 multi = hwif->INW(ma);
323 ultra = hwif->INW(ua);
325 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
326 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
327 pci_read_config_word(hwif->pci_dev, ma, &multi);
328 pci_read_config_word(hwif->pci_dev, ua, &ultra);
331 mode &= ~((unit) ? 0x30 : 0x03);
333 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
335 scsc = is_sata(hwif) ? 1 : scsc;
343 siimage_tuneproc(drive, (speed - XFER_PIO_0));
344 mode |= ((unit) ? 0x10 : 0x01);
349 multi = dma[speed - XFER_MW_DMA_0];
350 mode |= ((unit) ? 0x20 : 0x02);
351 config_siimage_chipset_for_pio(drive, 0);
361 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
362 (ultra5[speed - XFER_UDMA_0]));
363 mode |= ((unit) ? 0x30 : 0x03);
364 config_siimage_chipset_for_pio(drive, 0);
371 hwif->OUTB(mode, base + addr_mask);
372 hwif->OUTW(multi, ma);
373 hwif->OUTW(ultra, ua);
375 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
376 pci_write_config_word(hwif->pci_dev, ma, multi);
377 pci_write_config_word(hwif->pci_dev, ua, ultra);
379 return (ide_config_drive_speed(drive, speed));
383 * config_chipset_for_dma - configure for DMA
384 * @drive: drive to configure
386 * Called by the IDE layer when it wants the timings set up.
387 * For the CMD680 we also need to set up the PIO timings and
391 static int config_chipset_for_dma (ide_drive_t *drive)
393 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
395 config_chipset_for_pio(drive, !speed);
400 if (ide_set_xfer_rate(drive, speed))
403 if (!drive->init_speed)
404 drive->init_speed = speed;
406 return ide_dma_enable(drive);
410 * siimage_configure_drive_for_dma - set up for DMA transfers
411 * @drive: drive we are going to set up
413 * Set up the drive for DMA, tune the controller and drive as
414 * required. If the drive isn't suitable for DMA or we hit
415 * other problems then we will drop down to PIO and set up
419 static int siimage_config_drive_for_dma (ide_drive_t *drive)
421 ide_hwif_t *hwif = HWIF(drive);
422 struct hd_driveid *id = drive->id;
424 if ((id->capability & 1) != 0 && drive->autodma) {
426 if (ide_use_dma(drive)) {
427 if (config_chipset_for_dma(drive))
428 return hwif->ide_dma_on(drive);
433 } else if ((id->capability & 8) || (id->field_valid & 2)) {
435 config_chipset_for_pio(drive, 1);
436 return hwif->ide_dma_off_quietly(drive);
438 /* IORDY not supported */
442 /* returns 1 if dma irq issued, 0 otherwise */
443 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
445 ide_hwif_t *hwif = HWIF(drive);
447 unsigned long addr = siimage_selreg(hwif, 1);
449 /* return 1 if INTR asserted */
450 if ((hwif->INB(hwif->dma_status) & 4) == 4)
453 /* return 1 if Device INTR asserted */
454 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
456 return 0; //return 1;
462 * siimage_mmio_ide_dma_count - DMA bytes done
465 * If we are doing VDMA the CMD680 requires a little bit
466 * of more careful handling and we have to read the counts
467 * off ourselves. For non VDMA life is normal.
470 static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
472 #ifdef SIIMAGE_VIRTUAL_DMAPIO
473 struct request *rq = HWGROUP(drive)->rq;
474 ide_hwif_t *hwif = HWIF(drive);
475 u32 count = (rq->nr_sectors * SECTOR_SIZE);
477 unsigned long addr = siimage_selreg(hwif, 0x1C);
479 hwif->OUTL(count, addr);
480 rcount = hwif->INL(addr);
482 printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
483 drive->name, count, rcount, rq->nr_sectors);
485 #endif /* SIIMAGE_VIRTUAL_DMAPIO */
486 return __ide_dma_count(drive);
491 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
492 * @drive: drive we are testing
494 * Check if we caused an IDE DMA interrupt. We may also have caused
495 * SATA status interrupts, if so we clean them up and continue.
498 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
500 ide_hwif_t *hwif = HWIF(drive);
501 unsigned long base = (unsigned long)hwif->hwif_data;
502 unsigned long addr = siimage_selreg(hwif, 0x1);
504 if (SATA_ERROR_REG) {
505 u32 ext_stat = hwif->INL(base + 0x10);
507 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
508 u32 sata_error = hwif->INL(SATA_ERROR_REG);
509 hwif->OUTL(sata_error, SATA_ERROR_REG);
510 watchdog = (sata_error & 0x00680000) ? 1 : 0;
512 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
513 "watchdog = %d, %s\n",
514 drive->name, sata_error, watchdog,
519 watchdog = (ext_stat & 0x8000) ? 1 : 0;
523 if (!(ext_stat & 0x0404) && !watchdog)
527 /* return 1 if INTR asserted */
528 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
531 /* return 1 if Device INTR asserted */
532 if ((hwif->INB(addr) & 8) == 8)
533 return 0; //return 1;
539 * siimage_busproc - bus isolation ioctl
540 * @drive: drive to isolate/restore
541 * @state: bus state to set
543 * Used by the SII3112 to handle bus isolation. As this is a
544 * SATA controller the work required is quite limited, we
545 * just have to clean up the statistics
548 static int siimage_busproc (ide_drive_t * drive, int state)
550 ide_hwif_t *hwif = HWIF(drive);
552 unsigned long addr = siimage_selreg(hwif, 0);
555 stat_config = hwif->INL(addr);
557 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
561 hwif->drives[0].failures = 0;
562 hwif->drives[1].failures = 0;
565 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
566 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
568 case BUSSTATE_TRISTATE:
569 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
570 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
575 hwif->bus_state = state;
580 * siimage_reset_poll - wait for sata reset
581 * @drive: drive we are resetting
583 * Poll the SATA phy and see whether it has come back from the dead
587 static int siimage_reset_poll (ide_drive_t *drive)
589 if (SATA_STATUS_REG) {
590 ide_hwif_t *hwif = HWIF(drive);
592 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
593 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
594 hwif->name, hwif->INL(SATA_STATUS_REG));
595 HWGROUP(drive)->polling = 0;
605 * siimage_pre_reset - reset hook
606 * @drive: IDE device being reset
608 * For the SATA devices we need to handle recalibration/geometry
612 static void siimage_pre_reset (ide_drive_t *drive)
614 if (drive->media != ide_disk)
617 if (is_sata(HWIF(drive)))
619 drive->special.b.set_geometry = 0;
620 drive->special.b.recalibrate = 0;
625 * siimage_reset - reset a device on an siimage controller
626 * @drive: drive to reset
628 * Perform a controller level reset fo the device. For
629 * SATA we must also check the PHY.
632 static void siimage_reset (ide_drive_t *drive)
634 ide_hwif_t *hwif = HWIF(drive);
636 unsigned long addr = siimage_selreg(hwif, 0);
639 reset = hwif->INB(addr);
640 hwif->OUTB((reset|0x03), addr);
643 hwif->OUTB(reset, addr);
644 (void) hwif->INB(addr);
646 pci_read_config_byte(hwif->pci_dev, addr, &reset);
647 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
649 pci_write_config_byte(hwif->pci_dev, addr, reset);
650 pci_read_config_byte(hwif->pci_dev, addr, &reset);
653 if (SATA_STATUS_REG) {
654 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
655 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
656 hwif->name, sata_stat, __FUNCTION__);
658 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
659 hwif->name, sata_stat);
667 * proc_reports_siimage - add siimage controller to proc
669 * @clocking: SCSC value
670 * @name: controller name
672 * Report the clocking mode of the controller and add it to
673 * the /proc interface layer
676 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
678 if (!pdev_is_sata(dev)) {
679 printk(KERN_INFO "%s: BASE CLOCK ", name);
682 case 0x03: printk("DISABLED!\n"); break;
683 case 0x02: printk("== 2X PCI\n"); break;
684 case 0x01: printk("== 133\n"); break;
685 case 0x00: printk("== 100\n"); break;
691 * setup_mmio_siimage - switch an SI controller into MMIO
692 * @dev: PCI device we are configuring
695 * Attempt to put the device into mmio mode. There are some slight
696 * complications here with certain systems where the mmio bar isnt
697 * mapped so we have to be sure we can fall back to I/O.
700 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
702 unsigned long bar5 = pci_resource_start(dev, 5);
703 unsigned long barsize = pci_resource_len(dev, 5);
705 void __iomem *ioaddr;
708 * Drop back to PIO if we can't map the mmio. Some
709 * systems seem to get terminally confused in the PCI
713 if(!request_mem_region(bar5, barsize, name))
715 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
719 ioaddr = ioremap(bar5, barsize);
723 release_mem_region(bar5, barsize);
728 pci_set_drvdata(dev, (void *) ioaddr);
730 if (pdev_is_sata(dev)) {
731 writel(0, ioaddr + 0x148);
732 writel(0, ioaddr + 0x1C8);
735 writeb(0, ioaddr + 0xB4);
736 writeb(0, ioaddr + 0xF4);
737 tmpbyte = readb(ioaddr + 0x4A);
739 switch(tmpbyte & 0x30) {
741 /* In 100 MHz clocking, try and switch to 133 */
742 writeb(tmpbyte|0x10, ioaddr + 0x4A);
745 /* On 133Mhz clocking */
748 /* On PCIx2 clocking */
751 /* Clocking is disabled */
752 /* 133 clock attempt to force it on */
753 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
757 writeb( 0x72, ioaddr + 0xA1);
758 writew( 0x328A, ioaddr + 0xA2);
759 writel(0x62DD62DD, ioaddr + 0xA4);
760 writel(0x43924392, ioaddr + 0xA8);
761 writel(0x40094009, ioaddr + 0xAC);
762 writeb( 0x72, ioaddr + 0xE1);
763 writew( 0x328A, ioaddr + 0xE2);
764 writel(0x62DD62DD, ioaddr + 0xE4);
765 writel(0x43924392, ioaddr + 0xE8);
766 writel(0x40094009, ioaddr + 0xEC);
768 if (pdev_is_sata(dev)) {
769 writel(0xFFFF0000, ioaddr + 0x108);
770 writel(0xFFFF0000, ioaddr + 0x188);
771 writel(0x00680000, ioaddr + 0x148);
772 writel(0x00680000, ioaddr + 0x1C8);
775 tmpbyte = readb(ioaddr + 0x4A);
777 proc_reports_siimage(dev, (tmpbyte>>4), name);
782 * init_chipset_siimage - set up an SI device
786 * Perform the initial PCI set up for this device. Attempt to switch
787 * to 133MHz clocking if the system isn't already set up to do it.
790 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
796 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
798 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
800 pci_read_config_byte(dev, 0x8A, &BA5_EN);
801 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
802 if (setup_mmio_siimage(dev, name)) {
807 pci_write_config_byte(dev, 0x80, 0x00);
808 pci_write_config_byte(dev, 0x84, 0x00);
809 pci_read_config_byte(dev, 0x8A, &tmpbyte);
810 switch(tmpbyte & 0x30) {
812 /* 133 clock attempt to force it on */
813 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
815 /* if clocking is disabled */
816 /* 133 clock attempt to force it on */
817 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
822 /* BIOS set PCI x2 clocking */
826 pci_read_config_byte(dev, 0x8A, &tmpbyte);
828 pci_write_config_byte(dev, 0xA1, 0x72);
829 pci_write_config_word(dev, 0xA2, 0x328A);
830 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
831 pci_write_config_dword(dev, 0xA8, 0x43924392);
832 pci_write_config_dword(dev, 0xAC, 0x40094009);
833 pci_write_config_byte(dev, 0xB1, 0x72);
834 pci_write_config_word(dev, 0xB2, 0x328A);
835 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
836 pci_write_config_dword(dev, 0xB8, 0x43924392);
837 pci_write_config_dword(dev, 0xBC, 0x40094009);
839 proc_reports_siimage(dev, (tmpbyte>>4), name);
844 * init_mmio_iops_siimage - set up the iops for MMIO
845 * @hwif: interface to set up
847 * The basic setup here is fairly simple, we can use standard MMIO
848 * operations. However we do have to set the taskfile register offsets
849 * by hand as there isnt a standard defined layout for them this
852 * The hardware supports buffered taskfiles and also some rather nice
853 * extended PRD tables. Unfortunately right now we don't.
856 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
858 struct pci_dev *dev = hwif->pci_dev;
859 void *addr = pci_get_drvdata(dev);
860 u8 ch = hwif->channel;
865 * Fill in the basic HWIF bits
868 default_hwif_mmiops(hwif);
869 hwif->hwif_data = addr;
872 * Now set up the hw. We have to do this ourselves as
873 * the MMIO layout isnt the same as the the standard port
877 memset(&hw, 0, sizeof(hw_regs_t));
879 base = (unsigned long)addr;
886 * The buffered task file doesn't have status/control
887 * so we can't currently use it sanely since we want to
891 // hwif->no_lba48 = 1;
893 hw.io_ports[IDE_DATA_OFFSET] = base;
894 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
895 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
896 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
897 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
898 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
899 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
900 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
901 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
903 hw.io_ports[IDE_IRQ_OFFSET] = 0;
905 if (pdev_is_sata(dev)) {
906 base = (unsigned long)addr;
909 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
910 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
911 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
912 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
913 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
914 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
917 hw.irq = hwif->pci_dev->irq;
919 memcpy(&hwif->hw, &hw, sizeof(hw));
920 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
924 base = (unsigned long) addr;
926 #ifdef SIIMAGE_LARGE_DMA
927 /* Watch the brackets - even Ken and Dennis get some language design wrong */
928 hwif->dma_base = base + (ch ? 0x18 : 0x10);
929 hwif->dma_base2 = base + (ch ? 0x08 : 0x00);
930 hwif->dma_prdtable = hwif->dma_base2 + 4;
931 #else /* ! SIIMAGE_LARGE_DMA */
932 hwif->dma_base = base + (ch ? 0x08 : 0x00);
933 hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
934 #endif /* SIIMAGE_LARGE_DMA */
938 static int is_dev_seagate_sata(ide_drive_t *drive)
940 const char *s = &drive->id->model[0];
946 len = strnlen(s, sizeof(drive->id->model));
948 if ((len > 4) && (!memcmp(s, "ST", 2))) {
949 if ((!memcmp(s + len - 2, "AS", 2)) ||
950 (!memcmp(s + len - 3, "ASL", 3))) {
951 printk(KERN_INFO "%s: applying pessimistic Seagate "
952 "errata fix\n", drive->name);
960 * siimage_fixup - post probe fixups
961 * @hwif: interface to fix up
963 * Called after drive probe we use this to decide whether the
964 * Seagate fixup must be applied. This used to be in init_iops but
965 * that can occur before we know what drives are present.
968 static void __devinit siimage_fixup(ide_hwif_t *hwif)
970 /* Try and raise the rqsize */
971 if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
976 * init_iops_siimage - set up iops
977 * @hwif: interface to set up
979 * Do the basic setup for the SIIMAGE hardware interface
980 * and then do the MMIO setup if we can. This is the first
981 * look in we get for setting up the hwif so that we
982 * can get the iops right before using them.
985 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
987 struct pci_dev *dev = hwif->pci_dev;
990 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
993 hwif->hwif_data = NULL;
995 /* Pessimal until we finish probing */
998 if (pci_get_drvdata(dev) == NULL)
1000 init_mmio_iops_siimage(hwif);
1004 * ata66_siimage - check for 80 pin cable
1005 * @hwif: interface to check
1007 * Check for the presence of an ATA66 capable cable on the
1011 static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
1013 unsigned long addr = siimage_selreg(hwif, 0);
1014 if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1016 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1017 return (ata66 & 0x01) ? 1 : 0;
1020 return (hwif->INB(addr) & 0x01) ? 1 : 0;
1024 * init_hwif_siimage - set up hwif structs
1025 * @hwif: interface to set up
1027 * We do the basic set up of the interface structure. The SIIMAGE
1028 * requires several custom handlers so we override the default
1029 * ide DMA handlers appropriately
1032 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
1036 hwif->resetproc = &siimage_reset;
1037 hwif->speedproc = &siimage_tune_chipset;
1038 hwif->tuneproc = &siimage_tuneproc;
1039 hwif->reset_poll = &siimage_reset_poll;
1040 hwif->pre_reset = &siimage_pre_reset;
1043 hwif->busproc = &siimage_busproc;
1045 if (!hwif->dma_base) {
1046 hwif->drives[0].autotune = 1;
1047 hwif->drives[1].autotune = 1;
1051 hwif->ultra_mask = 0x7f;
1052 hwif->mwdma_mask = 0x07;
1053 hwif->swdma_mask = 0x07;
1056 hwif->atapi_dma = 1;
1058 hwif->ide_dma_check = &siimage_config_drive_for_dma;
1059 if (!(hwif->udma_four))
1060 hwif->udma_four = ata66_siimage(hwif);
1063 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1065 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1069 * The BIOS often doesn't set up DMA on this controller
1070 * so we always do it.
1074 hwif->drives[0].autodma = hwif->autodma;
1075 hwif->drives[1].autodma = hwif->autodma;
1078 #define DECLARE_SII_DEV(name_str) \
1081 .init_chipset = init_chipset_siimage, \
1082 .init_iops = init_iops_siimage, \
1083 .init_hwif = init_hwif_siimage, \
1084 .fixup = siimage_fixup, \
1086 .autodma = AUTODMA, \
1087 .bootable = ON_BOARD, \
1090 static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1091 /* 0 */ DECLARE_SII_DEV("SiI680"),
1092 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1093 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA"),
1094 /* 3 */ DECLARE_SII_DEV("ATI IXP300"),
1095 /* 4 */ DECLARE_SII_DEV("ATI IXP400")
1099 * siimage_init_one - pci layer discovery entry
1101 * @id: ident table entry
1103 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1104 * We then use the IDE PCI generic helper to do most of the work.
1107 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1109 return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1112 static struct pci_device_id siimage_pci_tbl[] = {
1113 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1114 #ifdef CONFIG_BLK_DEV_IDE_SATA
1115 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1116 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1117 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1118 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1122 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1124 static struct pci_driver driver = {
1126 .id_table = siimage_pci_tbl,
1127 .probe = siimage_init_one,
1130 static int siimage_ide_init(void)
1132 return ide_pci_register_driver(&driver);
1135 module_init(siimage_ide_init);
1137 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1138 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1139 MODULE_LICENSE("GPL");