2 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation available under NDA only
13 * If you are using Marvell SATA-IDE adapters with Maxtor drives
14 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
16 * If you are using WD drives with SATA bridges you must set the
17 * drive to "Single". "Master" will hang
19 * If you have strange problems with nVidia chipset systems please
20 * see the SI support documentation and update your system BIOS
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/delay.h>
28 #include <linux/hdreg.h>
29 #include <linux/ide.h>
30 #include <linux/init.h>
34 #undef SIIMAGE_VIRTUAL_DMAPIO
35 #undef SIIMAGE_LARGE_DMA
38 * pdev_is_sata - check if device is SATA
39 * @pdev: PCI device to check
41 * Returns true if this is a SATA controller
44 static int pdev_is_sata(struct pci_dev *pdev)
48 case PCI_DEVICE_ID_SII_3112:
49 case PCI_DEVICE_ID_SII_1210SA:
51 case PCI_DEVICE_ID_SII_680:
59 * is_sata - check if hwif is SATA
60 * @hwif: interface to check
62 * Returns true if this is a SATA controller
65 static inline int is_sata(ide_hwif_t *hwif)
67 return pdev_is_sata(hwif->pci_dev);
71 * siimage_selreg - return register base
75 * Turn a config register offset into the right address in either
76 * PCI space or MMIO space to access the control register in question
77 * Thankfully this is a configuration operation so isnt performance
81 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
83 unsigned long base = (unsigned long)hwif->hwif_data;
86 base += (hwif->channel << 6);
88 base += (hwif->channel << 4);
93 * siimage_seldev - return register base
97 * Turn a config register offset into the right address in either
98 * PCI space or MMIO space to access the control register in question
99 * including accounting for the unit shift.
102 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
104 ide_hwif_t *hwif = HWIF(drive);
105 unsigned long base = (unsigned long)hwif->hwif_data;
108 base += (hwif->channel << 6);
110 base += (hwif->channel << 4);
111 base |= drive->select.b.unit << drive->select.b.unit;
116 * siimage_ratemask - Compute available modes
119 * Compute the available speeds for the devices on the interface.
120 * For the CMD680 this depends on the clocking mode (scsc), for the
121 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
122 * as a limit if there is no 80pin cable present.
125 static byte siimage_ratemask (ide_drive_t *drive)
127 ide_hwif_t *hwif = HWIF(drive);
128 u8 mode = 0, scsc = 0;
129 unsigned long base = (unsigned long) hwif->hwif_data;
132 scsc = hwif->INB(base + 0x4A);
134 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
138 if(strstr(drive->id->model, "Maxtor"))
143 if ((scsc & 0x30) == 0x10) /* 133 */
145 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
147 else if ((scsc & 0x30) == 0x00) /* 100 */
149 else /* Disabled ? */
152 if (!eighty_ninty_three(drive))
153 mode = min(mode, (u8)1);
158 * siimage_taskfile_timing - turn timing data to a mode
159 * @hwif: interface to query
161 * Read the timing data for the interface and return the
162 * mode that is being used.
165 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
168 unsigned long addr = siimage_selreg(hwif, 2);
171 timing = hwif->INW(addr);
173 pci_read_config_word(hwif->pci_dev, addr, &timing);
176 case 0x10c1: return 4;
177 case 0x10c3: return 3;
179 case 0x1281: return 2;
180 case 0x2283: return 1;
187 * simmage_tuneproc - tune a drive
188 * @drive: drive to tune
189 * @mode_wanted: the target operating mode
191 * Load the timing settings for this device mode into the
192 * controller. If we are in PIO mode 3 or 4 turn on IORDY
193 * monitoring (bit 9). The TF timing is bits 31:16
196 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
198 ide_hwif_t *hwif = HWIF(drive);
201 unsigned long addr = siimage_seldev(drive, 0x04);
202 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
204 /* cheat for now and use the docs */
205 switch(mode_wanted) {
230 hwif->OUTW(speedt, addr);
231 hwif->OUTW(speedp, tfaddr);
232 /* Now set up IORDY */
233 if(mode_wanted == 3 || mode_wanted == 4)
234 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
236 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
240 pci_write_config_word(hwif->pci_dev, addr, speedp);
241 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
242 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
244 /* Set IORDY for mode 3 or 4 */
245 if(mode_wanted == 3 || mode_wanted == 4)
247 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
252 * config_siimage_chipset_for_pio - set drive timings
253 * @drive: drive to tune
256 * Compute the best pio mode we can for a given device. Also honour
257 * the timings for the driver when dealing with mixed devices. Some
258 * of this is ugly but its all wrapped up here
260 * The SI680 can also do VDMA - we need to start using that
262 * FIXME: we use the BIOS channel timings to avoid driving the task
263 * files too fast at the disk. We need to compute the master/slave
264 * drive PIO mode properly so that we can up the speed on a hotplug
268 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
270 u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
271 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
273 /* WARNING PIO timing mess is going to happen b/w devices, argh */
274 if ((channel_timings != set_pio) && (set_pio > channel_timings))
275 set_pio = channel_timings;
277 siimage_tuneproc(drive, set_pio);
278 speed = XFER_PIO_0 + set_pio;
280 (void) ide_config_drive_speed(drive, speed);
283 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
285 config_siimage_chipset_for_pio(drive, set_speed);
289 * siimage_tune_chipset - set controller timings
290 * @drive: Drive to set up
291 * @xferspeed: speed we want to achieve
293 * Tune the SII chipset for the desired mode. If we can't achieve
294 * the desired mode then tune for a lower one, but ultimately
295 * make the thing work.
298 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
300 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
301 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
302 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
304 ide_hwif_t *hwif = HWIF(drive);
305 u16 ultra = 0, multi = 0;
306 u8 mode = 0, unit = drive->select.b.unit;
307 u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed);
308 unsigned long base = (unsigned long)hwif->hwif_data;
309 u8 scsc = 0, addr_mask = ((hwif->channel) ?
310 ((hwif->mmio) ? 0xF4 : 0x84) :
311 ((hwif->mmio) ? 0xB4 : 0x80));
313 unsigned long ma = siimage_seldev(drive, 0x08);
314 unsigned long ua = siimage_seldev(drive, 0x0C);
317 scsc = hwif->INB(base + 0x4A);
318 mode = hwif->INB(base + addr_mask);
319 multi = hwif->INW(ma);
320 ultra = hwif->INW(ua);
322 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
323 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
324 pci_read_config_word(hwif->pci_dev, ma, &multi);
325 pci_read_config_word(hwif->pci_dev, ua, &ultra);
328 mode &= ~((unit) ? 0x30 : 0x03);
330 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
332 scsc = is_sata(hwif) ? 1 : scsc;
340 siimage_tuneproc(drive, (speed - XFER_PIO_0));
341 mode |= ((unit) ? 0x10 : 0x01);
346 multi = dma[speed - XFER_MW_DMA_0];
347 mode |= ((unit) ? 0x20 : 0x02);
348 config_siimage_chipset_for_pio(drive, 0);
358 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
359 (ultra5[speed - XFER_UDMA_0]));
360 mode |= ((unit) ? 0x30 : 0x03);
361 config_siimage_chipset_for_pio(drive, 0);
368 hwif->OUTB(mode, base + addr_mask);
369 hwif->OUTW(multi, ma);
370 hwif->OUTW(ultra, ua);
372 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
373 pci_write_config_word(hwif->pci_dev, ma, multi);
374 pci_write_config_word(hwif->pci_dev, ua, ultra);
376 return (ide_config_drive_speed(drive, speed));
380 * config_chipset_for_dma - configure for DMA
381 * @drive: drive to configure
383 * Called by the IDE layer when it wants the timings set up.
384 * For the CMD680 we also need to set up the PIO timings and
388 static int config_chipset_for_dma (ide_drive_t *drive)
390 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
392 config_chipset_for_pio(drive, !speed);
397 if (ide_set_xfer_rate(drive, speed))
400 if (!drive->init_speed)
401 drive->init_speed = speed;
403 return ide_dma_enable(drive);
407 * siimage_configure_drive_for_dma - set up for DMA transfers
408 * @drive: drive we are going to set up
410 * Set up the drive for DMA, tune the controller and drive as
411 * required. If the drive isn't suitable for DMA or we hit
412 * other problems then we will drop down to PIO and set up
416 static int siimage_config_drive_for_dma (ide_drive_t *drive)
418 ide_hwif_t *hwif = HWIF(drive);
419 struct hd_driveid *id = drive->id;
421 if ((id->capability & 1) != 0 && drive->autodma) {
422 /* Consult the list of known "bad" drives */
423 if (__ide_dma_bad_drive(drive))
426 if ((id->field_valid & 4) && siimage_ratemask(drive)) {
427 if (id->dma_ultra & hwif->ultra_mask) {
428 /* Force if Capable UltraDMA */
429 int dma = config_chipset_for_dma(drive);
430 if ((id->field_valid & 2) && !dma)
433 } else if (id->field_valid & 2) {
435 if ((id->dma_mword & hwif->mwdma_mask) ||
436 (id->dma_1word & hwif->swdma_mask)) {
437 /* Force if Capable regular DMA modes */
438 if (!config_chipset_for_dma(drive))
441 } else if (__ide_dma_good_drive(drive) &&
442 (id->eide_dma_time < 150)) {
443 /* Consult the list of known "good" drives */
444 if (!config_chipset_for_dma(drive))
449 return hwif->ide_dma_on(drive);
450 } else if ((id->capability & 8) || (id->field_valid & 2)) {
453 config_chipset_for_pio(drive, 1);
454 return hwif->ide_dma_off_quietly(drive);
456 /* IORDY not supported */
460 /* returns 1 if dma irq issued, 0 otherwise */
461 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
463 ide_hwif_t *hwif = HWIF(drive);
465 unsigned long addr = siimage_selreg(hwif, 1);
467 /* return 1 if INTR asserted */
468 if ((hwif->INB(hwif->dma_status) & 4) == 4)
471 /* return 1 if Device INTR asserted */
472 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
474 return 0; //return 1;
480 * siimage_mmio_ide_dma_count - DMA bytes done
483 * If we are doing VDMA the CMD680 requires a little bit
484 * of more careful handling and we have to read the counts
485 * off ourselves. For non VDMA life is normal.
488 static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
490 #ifdef SIIMAGE_VIRTUAL_DMAPIO
491 struct request *rq = HWGROUP(drive)->rq;
492 ide_hwif_t *hwif = HWIF(drive);
493 u32 count = (rq->nr_sectors * SECTOR_SIZE);
495 unsigned long addr = siimage_selreg(hwif, 0x1C);
497 hwif->OUTL(count, addr);
498 rcount = hwif->INL(addr);
500 printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
501 drive->name, count, rcount, rq->nr_sectors);
503 #endif /* SIIMAGE_VIRTUAL_DMAPIO */
504 return __ide_dma_count(drive);
509 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
510 * @drive: drive we are testing
512 * Check if we caused an IDE DMA interrupt. We may also have caused
513 * SATA status interrupts, if so we clean them up and continue.
516 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
518 ide_hwif_t *hwif = HWIF(drive);
519 unsigned long base = (unsigned long)hwif->hwif_data;
520 unsigned long addr = siimage_selreg(hwif, 0x1);
522 if (SATA_ERROR_REG) {
523 u32 ext_stat = hwif->INL(base + 0x10);
525 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
526 u32 sata_error = hwif->INL(SATA_ERROR_REG);
527 hwif->OUTL(sata_error, SATA_ERROR_REG);
528 watchdog = (sata_error & 0x00680000) ? 1 : 0;
530 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
531 "watchdog = %d, %s\n",
532 drive->name, sata_error, watchdog,
537 watchdog = (ext_stat & 0x8000) ? 1 : 0;
541 if (!(ext_stat & 0x0404) && !watchdog)
545 /* return 1 if INTR asserted */
546 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
549 /* return 1 if Device INTR asserted */
550 if ((hwif->INB(addr) & 8) == 8)
551 return 0; //return 1;
556 static int siimage_mmio_ide_dma_verbose (ide_drive_t *drive)
558 int temp = __ide_dma_verbose(drive);
563 * siimage_busproc - bus isolation ioctl
564 * @drive: drive to isolate/restore
565 * @state: bus state to set
567 * Used by the SII3112 to handle bus isolation. As this is a
568 * SATA controller the work required is quite limited, we
569 * just have to clean up the statistics
572 static int siimage_busproc (ide_drive_t * drive, int state)
574 ide_hwif_t *hwif = HWIF(drive);
576 unsigned long addr = siimage_selreg(hwif, 0);
579 stat_config = hwif->INL(addr);
581 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
585 hwif->drives[0].failures = 0;
586 hwif->drives[1].failures = 0;
589 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
590 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
592 case BUSSTATE_TRISTATE:
593 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
594 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
599 hwif->bus_state = state;
604 * siimage_reset_poll - wait for sata reset
605 * @drive: drive we are resetting
607 * Poll the SATA phy and see whether it has come back from the dead
611 static int siimage_reset_poll (ide_drive_t *drive)
613 if (SATA_STATUS_REG) {
614 ide_hwif_t *hwif = HWIF(drive);
616 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
617 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
618 hwif->name, hwif->INL(SATA_STATUS_REG));
619 HWGROUP(drive)->poll_timeout = 0;
629 * siimage_pre_reset - reset hook
630 * @drive: IDE device being reset
632 * For the SATA devices we need to handle recalibration/geometry
636 static void siimage_pre_reset (ide_drive_t *drive)
638 if (drive->media != ide_disk)
641 if (is_sata(HWIF(drive)))
643 drive->special.b.set_geometry = 0;
644 drive->special.b.recalibrate = 0;
649 * siimage_reset - reset a device on an siimage controller
650 * @drive: drive to reset
652 * Perform a controller level reset fo the device. For
653 * SATA we must also check the PHY.
656 static void siimage_reset (ide_drive_t *drive)
658 ide_hwif_t *hwif = HWIF(drive);
660 unsigned long addr = siimage_selreg(hwif, 0);
663 reset = hwif->INB(addr);
664 hwif->OUTB((reset|0x03), addr);
667 hwif->OUTB(reset, addr);
668 (void) hwif->INB(addr);
670 pci_read_config_byte(hwif->pci_dev, addr, &reset);
671 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
673 pci_write_config_byte(hwif->pci_dev, addr, reset);
674 pci_read_config_byte(hwif->pci_dev, addr, &reset);
677 if (SATA_STATUS_REG) {
678 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
679 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
680 hwif->name, sata_stat, __FUNCTION__);
682 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
683 hwif->name, sata_stat);
691 * proc_reports_siimage - add siimage controller to proc
693 * @clocking: SCSC value
694 * @name: controller name
696 * Report the clocking mode of the controller and add it to
697 * the /proc interface layer
700 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
702 if (!pdev_is_sata(dev)) {
703 printk(KERN_INFO "%s: BASE CLOCK ", name);
706 case 0x03: printk("DISABLED!\n"); break;
707 case 0x02: printk("== 2X PCI\n"); break;
708 case 0x01: printk("== 133\n"); break;
709 case 0x00: printk("== 100\n"); break;
715 * setup_mmio_siimage - switch an SI controller into MMIO
716 * @dev: PCI device we are configuring
719 * Attempt to put the device into mmio mode. There are some slight
720 * complications here with certain systems where the mmio bar isnt
721 * mapped so we have to be sure we can fall back to I/O.
724 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
726 unsigned long bar5 = pci_resource_start(dev, 5);
727 unsigned long barsize = pci_resource_len(dev, 5);
733 * Drop back to PIO if we can't map the mmio. Some
734 * systems seem to get terminally confused in the PCI
738 if(!request_mem_region(bar5, barsize, name))
740 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
744 ioaddr = ioremap(bar5, barsize);
748 release_mem_region(bar5, barsize);
753 pci_set_drvdata(dev, ioaddr);
754 addr = (unsigned long) ioaddr;
756 if (pdev_is_sata(dev)) {
757 writel(0, addr + 0x148);
758 writel(0, addr + 0x1C8);
761 writeb(0, addr + 0xB4);
762 writeb(0, addr + 0xF4);
763 tmpbyte = readb(addr + 0x4A);
765 switch(tmpbyte & 0x30) {
767 /* In 100 MHz clocking, try and switch to 133 */
768 writeb(tmpbyte|0x10, addr + 0x4A);
771 /* On 133Mhz clocking */
774 /* On PCIx2 clocking */
777 /* Clocking is disabled */
778 /* 133 clock attempt to force it on */
779 writeb(tmpbyte & ~0x20, addr + 0x4A);
783 writeb( 0x72, addr + 0xA1);
784 writew( 0x328A, addr + 0xA2);
785 writel(0x62DD62DD, addr + 0xA4);
786 writel(0x43924392, addr + 0xA8);
787 writel(0x40094009, addr + 0xAC);
788 writeb( 0x72, addr + 0xE1);
789 writew( 0x328A, addr + 0xE2);
790 writel(0x62DD62DD, addr + 0xE4);
791 writel(0x43924392, addr + 0xE8);
792 writel(0x40094009, addr + 0xEC);
794 if (pdev_is_sata(dev)) {
795 writel(0xFFFF0000, addr + 0x108);
796 writel(0xFFFF0000, addr + 0x188);
797 writel(0x00680000, addr + 0x148);
798 writel(0x00680000, addr + 0x1C8);
801 tmpbyte = readb(addr + 0x4A);
803 proc_reports_siimage(dev, (tmpbyte>>4), name);
808 * init_chipset_siimage - set up an SI device
812 * Perform the initial PCI set up for this device. Attempt to switch
813 * to 133MHz clocking if the system isn't already set up to do it.
816 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
822 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
824 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
826 pci_read_config_byte(dev, 0x8A, &BA5_EN);
827 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
828 if (setup_mmio_siimage(dev, name)) {
833 pci_write_config_byte(dev, 0x80, 0x00);
834 pci_write_config_byte(dev, 0x84, 0x00);
835 pci_read_config_byte(dev, 0x8A, &tmpbyte);
836 switch(tmpbyte & 0x30) {
838 /* 133 clock attempt to force it on */
839 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
841 /* if clocking is disabled */
842 /* 133 clock attempt to force it on */
843 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
848 /* BIOS set PCI x2 clocking */
852 pci_read_config_byte(dev, 0x8A, &tmpbyte);
854 pci_write_config_byte(dev, 0xA1, 0x72);
855 pci_write_config_word(dev, 0xA2, 0x328A);
856 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
857 pci_write_config_dword(dev, 0xA8, 0x43924392);
858 pci_write_config_dword(dev, 0xAC, 0x40094009);
859 pci_write_config_byte(dev, 0xB1, 0x72);
860 pci_write_config_word(dev, 0xB2, 0x328A);
861 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
862 pci_write_config_dword(dev, 0xB8, 0x43924392);
863 pci_write_config_dword(dev, 0xBC, 0x40094009);
865 proc_reports_siimage(dev, (tmpbyte>>4), name);
870 * init_mmio_iops_siimage - set up the iops for MMIO
871 * @hwif: interface to set up
873 * The basic setup here is fairly simple, we can use standard MMIO
874 * operations. However we do have to set the taskfile register offsets
875 * by hand as there isnt a standard defined layout for them this
878 * The hardware supports buffered taskfiles and also some rather nice
879 * extended PRD tables. Unfortunately right now we don't.
882 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
884 struct pci_dev *dev = hwif->pci_dev;
885 void *addr = pci_get_drvdata(dev);
886 u8 ch = hwif->channel;
891 * Fill in the basic HWIF bits
894 default_hwif_mmiops(hwif);
895 hwif->hwif_data = addr;
898 * Now set up the hw. We have to do this ourselves as
899 * the MMIO layout isnt the same as the the standard port
903 memset(&hw, 0, sizeof(hw_regs_t));
906 base = (unsigned long)addr;
913 * The buffered task file doesn't have status/control
914 * so we can't currently use it sanely since we want to
918 // hwif->no_lba48 = 1;
920 hw.io_ports[IDE_DATA_OFFSET] = base;
921 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
922 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
923 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
924 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
925 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
926 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
927 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
928 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
930 hw.io_ports[IDE_IRQ_OFFSET] = 0;
932 if (pdev_is_sata(dev)) {
933 base = (unsigned long) addr;
936 hw.sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
937 hw.sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
938 hw.sata_scr[SATA_CONTROL_OFFSET]= base + 0x100;
939 hw.sata_misc[SATA_MISC_OFFSET] = base + 0x140;
940 hw.sata_misc[SATA_PHY_OFFSET] = base + 0x144;
941 hw.sata_misc[SATA_IEN_OFFSET] = base + 0x148;
944 hw.irq = hwif->pci_dev->irq;
946 memcpy(&hwif->hw, &hw, sizeof(hw));
947 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
950 memcpy(hwif->sata_scr, hwif->hw.sata_scr, sizeof(hwif->hw.sata_scr));
951 memcpy(hwif->sata_misc, hwif->hw.sata_misc, sizeof(hwif->hw.sata_misc));
956 base = (unsigned long) addr;
958 #ifdef SIIMAGE_LARGE_DMA
959 /* Watch the brackets - even Ken and Dennis get some language design wrong */
960 hwif->dma_base = base + (ch ? 0x18 : 0x10);
961 hwif->dma_base2 = base + (ch ? 0x08 : 0x00);
962 hwif->dma_prdtable = hwif->dma_base2 + 4;
963 #else /* ! SIIMAGE_LARGE_DMA */
964 hwif->dma_base = base + (ch ? 0x08 : 0x00);
965 hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
966 #endif /* SIIMAGE_LARGE_DMA */
970 static int is_dev_seagate_sata(ide_drive_t *drive)
972 const char *s = &drive->id->model[0];
978 len = strnlen(s, sizeof(drive->id->model));
980 if ((len > 4) && (!memcmp(s, "ST", 2))) {
981 if ((!memcmp(s + len - 2, "AS", 2)) ||
982 (!memcmp(s + len - 3, "ASL", 3))) {
983 printk(KERN_INFO "%s: applying pessimistic Seagate "
984 "errata fix\n", drive->name);
992 * init_iops_siimage - set up iops
993 * @hwif: interface to set up
995 * Do the basic setup for the SIIMAGE hardware interface
996 * and then do the MMIO setup if we can. This is the first
997 * look in we get for setting up the hwif so that we
998 * can get the iops right before using them.
1001 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
1003 struct pci_dev *dev = hwif->pci_dev;
1006 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1009 hwif->hwif_data = 0;
1012 if (is_sata(hwif) && is_dev_seagate_sata(&hwif->drives[0]))
1015 if (pci_get_drvdata(dev) == NULL)
1017 init_mmio_iops_siimage(hwif);
1021 * ata66_siimage - check for 80 pin cable
1022 * @hwif: interface to check
1024 * Check for the presence of an ATA66 capable cable on the
1028 static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
1030 unsigned long addr = siimage_selreg(hwif, 0);
1031 if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1033 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1034 return (ata66 & 0x01) ? 1 : 0;
1037 return (hwif->INB(addr) & 0x01) ? 1 : 0;
1041 * init_hwif_siimage - set up hwif structs
1042 * @hwif: interface to set up
1044 * We do the basic set up of the interface structure. The SIIMAGE
1045 * requires several custom handlers so we override the default
1046 * ide DMA handlers appropriately
1049 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
1053 hwif->resetproc = &siimage_reset;
1054 hwif->speedproc = &siimage_tune_chipset;
1055 hwif->tuneproc = &siimage_tuneproc;
1056 hwif->reset_poll = &siimage_reset_poll;
1057 hwif->pre_reset = &siimage_pre_reset;
1060 hwif->busproc = &siimage_busproc;
1062 if (!hwif->dma_base) {
1063 hwif->drives[0].autotune = 1;
1064 hwif->drives[1].autotune = 1;
1068 hwif->ultra_mask = 0x7f;
1069 hwif->mwdma_mask = 0x07;
1070 hwif->swdma_mask = 0x07;
1073 hwif->atapi_dma = 1;
1075 hwif->ide_dma_check = &siimage_config_drive_for_dma;
1076 if (!(hwif->udma_four))
1077 hwif->udma_four = ata66_siimage(hwif);
1080 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1081 hwif->ide_dma_verbose = &siimage_mmio_ide_dma_verbose;
1083 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1087 * The BIOS often doesn't set up DMA on this controller
1088 * so we always do it.
1092 hwif->drives[0].autodma = hwif->autodma;
1093 hwif->drives[1].autodma = hwif->autodma;
1096 #define DECLARE_SII_DEV(name_str) \
1099 .init_chipset = init_chipset_siimage, \
1100 .init_iops = init_iops_siimage, \
1101 .init_hwif = init_hwif_siimage, \
1103 .autodma = AUTODMA, \
1104 .bootable = ON_BOARD, \
1107 static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1108 /* 0 */ DECLARE_SII_DEV("SiI680"),
1109 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1110 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1114 * siimage_init_one - pci layer discovery entry
1116 * @id: ident table entry
1118 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1119 * We then use the IDE PCI generic helper to do most of the work.
1122 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1124 ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1128 static struct pci_device_id siimage_pci_tbl[] = {
1129 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1130 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1131 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1134 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1136 static struct pci_driver driver = {
1138 .id_table = siimage_pci_tbl,
1139 .probe = siimage_init_one,
1142 static int siimage_ide_init(void)
1144 return ide_pci_register_driver(&driver);
1147 module_init(siimage_ide_init);
1149 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1150 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1151 MODULE_LICENSE("GPL");