2 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation available under NDA only
13 * If you are using Marvell SATA-IDE adapters with Maxtor drives
14 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
16 * If you are using WD drives with SATA bridges you must set the
17 * drive to "Single". "Master" will hang
19 * If you have strange problems with nVidia chipset systems please
20 * see the SI support documentation and update your system BIOS
24 #include <linux/config.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
37 #if defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS)
38 #include <linux/proc_fs.h>
40 static u8 siimage_proc = 0;
41 #define SIIMAGE_MAX_DEVS 16
42 static struct pci_dev *siimage_devs[SIIMAGE_MAX_DEVS];
43 static int n_siimage_devs;
44 #endif /* defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS) */
47 * pdev_is_sata - check if device is SATA
48 * @pdev: PCI device to check
50 * Returns true if this is a SATA controller
53 static int pdev_is_sata(struct pci_dev *pdev)
57 case PCI_DEVICE_ID_SII_3112:
58 case PCI_DEVICE_ID_SII_1210SA:
60 case PCI_DEVICE_ID_SII_680:
68 * is_sata - check if hwif is SATA
69 * @hwif: interface to check
71 * Returns true if this is a SATA controller
74 static inline int is_sata(ide_hwif_t *hwif)
76 return pdev_is_sata(hwif->pci_dev);
80 * siimage_selreg - return register base
84 * Turn a config register offset into the right address in either
85 * PCI space or MMIO space to access the control register in question
86 * Thankfully this is a configuration operation so isnt performance
90 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
92 unsigned long base = (unsigned long)hwif->hwif_data;
95 base += (hwif->channel << 6);
97 base += (hwif->channel << 4);
102 * siimage_seldev - return register base
106 * Turn a config register offset into the right address in either
107 * PCI space or MMIO space to access the control register in question
108 * including accounting for the unit shift.
111 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
113 ide_hwif_t *hwif = HWIF(drive);
114 unsigned long base = (unsigned long)hwif->hwif_data;
117 base += (hwif->channel << 6);
119 base += (hwif->channel << 4);
120 base |= drive->select.b.unit << drive->select.b.unit;
124 #if defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS)
126 * print_siimage_get_info - print minimal proc information
127 * @buf: buffer to write into (kernel space)
128 * @dev: PCI device we are describing
129 * @index: Controller number
131 * Print the basic information for the state of the CMD680/SI3112
132 * channel. We don't actually dump a lot of information out for
133 * this controller although we could expand it if we needed.
136 static char *print_siimage_get_info (char *buf, struct pci_dev *dev, int index)
139 u8 mmio = (pci_get_drvdata(dev) != NULL) ? 1 : 0;
140 unsigned long bmdma = pci_resource_start(dev, 4);
143 bmdma = pci_resource_start(dev, 5);
145 p += sprintf(p, "\nController: %d\n", index);
146 p += sprintf(p, "SiI%x Chipset.\n", dev->device);
148 p += sprintf(p, "MMIO Base 0x%lx\n", bmdma);
149 p += sprintf(p, "%s-DMA Base 0x%lx\n", (mmio)?"MMIO":"BM", bmdma);
150 p += sprintf(p, "%s-DMA Base 0x%lx\n", (mmio)?"MMIO":"BM", bmdma+8);
155 * siimage_get_info - proc callback
156 * @buffer: kernel buffer to complete
157 * @addr: written with base of data to return
158 * offset: seek offset
159 * count: bytes to fill in
161 * Called when the user reads data from the virtual file for this
162 * controller from /proc
165 static int siimage_get_info (char *buffer, char **addr, off_t offset, int count)
171 p += sprintf(p, "\n");
172 for (i = 0; i < n_siimage_devs; i++) {
173 struct pci_dev *dev = siimage_devs[i];
174 p = print_siimage_get_info(p, dev, i);
176 /* p - buffer must be less than 4k! */
177 len = (p - buffer) - offset;
178 *addr = buffer + offset;
180 return len > count ? count : len;
183 #endif /* defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS) */
186 * siimage_ratemask - Compute available modes
189 * Compute the available speeds for the devices on the interface.
190 * For the CMD680 this depends on the clocking mode (scsc), for the
191 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
192 * as a limit if there is no 80pin cable present.
195 static byte siimage_ratemask (ide_drive_t *drive)
197 ide_hwif_t *hwif = HWIF(drive);
198 u8 mode = 0, scsc = 0;
199 unsigned long base = (unsigned long) hwif->hwif_data;
202 scsc = hwif->INB(base + 0x4A);
204 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
208 if(strstr(drive->id->model, "Maxtor"))
213 if ((scsc & 0x30) == 0x10) /* 133 */
215 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
217 else if ((scsc & 0x30) == 0x00) /* 100 */
219 else /* Disabled ? */
222 if (!eighty_ninty_three(drive))
223 mode = min(mode, (u8)1);
228 * siimage_taskfile_timing - turn timing data to a mode
229 * @hwif: interface to query
231 * Read the timing data for the interface and return the
232 * mode that is being used.
235 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
238 unsigned long addr = siimage_selreg(hwif, 2);
241 timing = hwif->INW(addr);
243 pci_read_config_word(hwif->pci_dev, addr, &timing);
246 case 0x10c1: return 4;
247 case 0x10c3: return 3;
249 case 0x1281: return 2;
250 case 0x2283: return 1;
257 * simmage_tuneproc - tune a drive
258 * @drive: drive to tune
259 * @mode_wanted: the target operating mode
261 * Load the timing settings for this device mode into the
262 * controller. If we are in PIO mode 3 or 4 turn on IORDY
263 * monitoring (bit 9). The TF timing is bits 31:16
266 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
268 ide_hwif_t *hwif = HWIF(drive);
271 unsigned long addr = siimage_seldev(drive, 0x04);
272 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
274 /* cheat for now and use the docs */
275 switch(mode_wanted) {
300 hwif->OUTW(speedt, addr);
301 hwif->OUTW(speedp, tfaddr);
302 /* Now set up IORDY */
303 if(mode_wanted == 3 || mode_wanted == 4)
304 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
306 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
310 pci_write_config_word(hwif->pci_dev, addr, speedp);
311 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
312 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
314 /* Set IORDY for mode 3 or 4 */
315 if(mode_wanted == 3 || mode_wanted == 4)
317 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
322 * config_siimage_chipset_for_pio - set drive timings
323 * @drive: drive to tune
326 * Compute the best pio mode we can for a given device. Also honour
327 * the timings for the driver when dealing with mixed devices. Some
328 * of this is ugly but its all wrapped up here
330 * The SI680 can also do VDMA - we need to start using that
332 * FIXME: we use the BIOS channel timings to avoid driving the task
333 * files too fast at the disk. We need to compute the master/slave
334 * drive PIO mode properly so that we can up the speed on a hotplug
338 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
340 u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
341 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
343 /* WARNING PIO timing mess is going to happen b/w devices, argh */
344 if ((channel_timings != set_pio) && (set_pio > channel_timings))
345 set_pio = channel_timings;
347 siimage_tuneproc(drive, set_pio);
348 speed = XFER_PIO_0 + set_pio;
350 (void) ide_config_drive_speed(drive, speed);
353 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
355 config_siimage_chipset_for_pio(drive, set_speed);
359 * siimage_tune_chipset - set controller timings
360 * @drive: Drive to set up
361 * @xferspeed: speed we want to achieve
363 * Tune the SII chipset for the desired mode. If we can't achieve
364 * the desired mode then tune for a lower one, but ultimately
365 * make the thing work.
368 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
370 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
371 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
372 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
374 ide_hwif_t *hwif = HWIF(drive);
375 u16 ultra = 0, multi = 0;
376 u8 mode = 0, unit = drive->select.b.unit;
377 u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed);
378 unsigned long base = (unsigned long)hwif->hwif_data;
379 u8 scsc = 0, addr_mask = ((hwif->channel) ?
380 ((hwif->mmio) ? 0xF4 : 0x84) :
381 ((hwif->mmio) ? 0xB4 : 0x80));
383 unsigned long ma = siimage_seldev(drive, 0x08);
384 unsigned long ua = siimage_seldev(drive, 0x0C);
387 scsc = hwif->INB(base + 0x4A);
388 mode = hwif->INB(base + addr_mask);
389 multi = hwif->INW(ma);
390 ultra = hwif->INW(ua);
392 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
393 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
394 pci_read_config_word(hwif->pci_dev, ma, &multi);
395 pci_read_config_word(hwif->pci_dev, ua, &ultra);
398 mode &= ~((unit) ? 0x30 : 0x03);
400 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
402 scsc = is_sata(hwif) ? 1 : scsc;
410 siimage_tuneproc(drive, (speed - XFER_PIO_0));
411 mode |= ((unit) ? 0x10 : 0x01);
416 multi = dma[speed - XFER_MW_DMA_0];
417 mode |= ((unit) ? 0x20 : 0x02);
418 config_siimage_chipset_for_pio(drive, 0);
428 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
429 (ultra5[speed - XFER_UDMA_0]));
430 mode |= ((unit) ? 0x30 : 0x03);
431 config_siimage_chipset_for_pio(drive, 0);
438 hwif->OUTB(mode, base + addr_mask);
439 hwif->OUTW(multi, ma);
440 hwif->OUTW(ultra, ua);
442 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
443 pci_write_config_word(hwif->pci_dev, ma, multi);
444 pci_write_config_word(hwif->pci_dev, ua, ultra);
446 return (ide_config_drive_speed(drive, speed));
450 * config_chipset_for_dma - configure for DMA
451 * @drive: drive to configure
453 * Called by the IDE layer when it wants the timings set up.
454 * For the CMD680 we also need to set up the PIO timings and
458 static int config_chipset_for_dma (ide_drive_t *drive)
460 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
462 config_chipset_for_pio(drive, !speed);
467 if (ide_set_xfer_rate(drive, speed))
470 if (!drive->init_speed)
471 drive->init_speed = speed;
473 return ide_dma_enable(drive);
477 * siimage_configure_drive_for_dma - set up for DMA transfers
478 * @drive: drive we are going to set up
480 * Set up the drive for DMA, tune the controller and drive as
481 * required. If the drive isn't suitable for DMA or we hit
482 * other problems then we will drop down to PIO and set up
486 static int siimage_config_drive_for_dma (ide_drive_t *drive)
488 ide_hwif_t *hwif = HWIF(drive);
489 struct hd_driveid *id = drive->id;
491 if ((id->capability & 1) != 0 && drive->autodma) {
492 /* Consult the list of known "bad" drives */
493 if (__ide_dma_bad_drive(drive))
496 if ((id->field_valid & 4) && siimage_ratemask(drive)) {
497 if (id->dma_ultra & hwif->ultra_mask) {
498 /* Force if Capable UltraDMA */
499 int dma = config_chipset_for_dma(drive);
500 if ((id->field_valid & 2) && !dma)
503 } else if (id->field_valid & 2) {
505 if ((id->dma_mword & hwif->mwdma_mask) ||
506 (id->dma_1word & hwif->swdma_mask)) {
507 /* Force if Capable regular DMA modes */
508 if (!config_chipset_for_dma(drive))
511 } else if (__ide_dma_good_drive(drive) &&
512 (id->eide_dma_time < 150)) {
513 /* Consult the list of known "good" drives */
514 if (!config_chipset_for_dma(drive))
519 return hwif->ide_dma_on(drive);
520 } else if ((id->capability & 8) || (id->field_valid & 2)) {
523 config_chipset_for_pio(drive, 1);
524 return hwif->ide_dma_off_quietly(drive);
526 /* IORDY not supported */
530 /* returns 1 if dma irq issued, 0 otherwise */
531 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
533 ide_hwif_t *hwif = HWIF(drive);
535 unsigned long addr = siimage_selreg(hwif, 1);
537 /* return 1 if INTR asserted */
538 if ((hwif->INB(hwif->dma_status) & 4) == 4)
541 /* return 1 if Device INTR asserted */
542 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
544 return 0; //return 1;
550 * siimage_mmio_ide_dma_count - DMA bytes done
553 * If we are doing VDMA the CMD680 requires a little bit
554 * of more careful handling and we have to read the counts
555 * off ourselves. For non VDMA life is normal.
558 static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
560 #ifdef SIIMAGE_VIRTUAL_DMAPIO
561 struct request *rq = HWGROUP(drive)->rq;
562 ide_hwif_t *hwif = HWIF(drive);
563 u32 count = (rq->nr_sectors * SECTOR_SIZE);
565 unsigned long addr = siimage_selreg(hwif, 0x1C);
567 hwif->OUTL(count, addr);
568 rcount = hwif->INL(addr);
570 printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
571 drive->name, count, rcount, rq->nr_sectors);
573 #endif /* SIIMAGE_VIRTUAL_DMAPIO */
574 return __ide_dma_count(drive);
579 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
580 * @drive: drive we are testing
582 * Check if we caused an IDE DMA interrupt. We may also have caused
583 * SATA status interrupts, if so we clean them up and continue.
586 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
588 ide_hwif_t *hwif = HWIF(drive);
589 unsigned long base = (unsigned long)hwif->hwif_data;
590 unsigned long addr = siimage_selreg(hwif, 0x1);
592 if (SATA_ERROR_REG) {
593 u32 ext_stat = hwif->INL(base + 0x10);
595 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
596 u32 sata_error = hwif->INL(SATA_ERROR_REG);
597 hwif->OUTL(sata_error, SATA_ERROR_REG);
598 watchdog = (sata_error & 0x00680000) ? 1 : 0;
600 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
601 "watchdog = %d, %s\n",
602 drive->name, sata_error, watchdog,
607 watchdog = (ext_stat & 0x8000) ? 1 : 0;
611 if (!(ext_stat & 0x0404) && !watchdog)
615 /* return 1 if INTR asserted */
616 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
619 /* return 1 if Device INTR asserted */
620 if ((hwif->INB(addr) & 8) == 8)
621 return 0; //return 1;
626 static int siimage_mmio_ide_dma_verbose (ide_drive_t *drive)
628 int temp = __ide_dma_verbose(drive);
633 * siimage_busproc - bus isolation ioctl
634 * @drive: drive to isolate/restore
635 * @state: bus state to set
637 * Used by the SII3112 to handle bus isolation. As this is a
638 * SATA controller the work required is quite limited, we
639 * just have to clean up the statistics
642 static int siimage_busproc (ide_drive_t * drive, int state)
644 ide_hwif_t *hwif = HWIF(drive);
646 unsigned long addr = siimage_selreg(hwif, 0);
649 stat_config = hwif->INL(addr);
651 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
655 hwif->drives[0].failures = 0;
656 hwif->drives[1].failures = 0;
659 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
660 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
662 case BUSSTATE_TRISTATE:
663 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
664 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
669 hwif->bus_state = state;
674 * siimage_reset_poll - wait for sata reset
675 * @drive: drive we are resetting
677 * Poll the SATA phy and see whether it has come back from the dead
681 static int siimage_reset_poll (ide_drive_t *drive)
683 if (SATA_STATUS_REG) {
684 ide_hwif_t *hwif = HWIF(drive);
686 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
687 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
688 hwif->name, hwif->INL(SATA_STATUS_REG));
689 HWGROUP(drive)->poll_timeout = 0;
699 * siimage_pre_reset - reset hook
700 * @drive: IDE device being reset
702 * For the SATA devices we need to handle recalibration/geometry
706 static void siimage_pre_reset (ide_drive_t *drive)
708 if (drive->media != ide_disk)
711 if (is_sata(HWIF(drive)))
713 drive->special.b.set_geometry = 0;
714 drive->special.b.recalibrate = 0;
719 * siimage_reset - reset a device on an siimage controller
720 * @drive: drive to reset
722 * Perform a controller level reset fo the device. For
723 * SATA we must also check the PHY.
726 static void siimage_reset (ide_drive_t *drive)
728 ide_hwif_t *hwif = HWIF(drive);
730 unsigned long addr = siimage_selreg(hwif, 0);
733 reset = hwif->INB(addr);
734 hwif->OUTB((reset|0x03), addr);
737 hwif->OUTB(reset, addr);
738 (void) hwif->INB(addr);
740 pci_read_config_byte(hwif->pci_dev, addr, &reset);
741 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
743 pci_write_config_byte(hwif->pci_dev, addr, reset);
744 pci_read_config_byte(hwif->pci_dev, addr, &reset);
747 if (SATA_STATUS_REG) {
748 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
749 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
750 hwif->name, sata_stat, __FUNCTION__);
752 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
753 hwif->name, sata_stat);
761 * proc_reports_siimage - add siimage controller to proc
763 * @clocking: SCSC value
764 * @name: controller name
766 * Report the clocking mode of the controller and add it to
767 * the /proc interface layer
770 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
772 if (!pdev_is_sata(dev)) {
773 printk(KERN_INFO "%s: BASE CLOCK ", name);
776 case 0x03: printk("DISABLED!\n"); break;
777 case 0x02: printk("== 2X PCI\n"); break;
778 case 0x01: printk("== 133\n"); break;
779 case 0x00: printk("== 100\n"); break;
783 #if defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS)
784 siimage_devs[n_siimage_devs++] = dev;
788 ide_pci_create_host_proc("siimage", siimage_get_info);
790 #endif /* DISPLAY_SIIMAGE_TIMINGS && CONFIG_PROC_FS */
794 * setup_mmio_siimage - switch an SI controller into MMIO
795 * @dev: PCI device we are configuring
798 * Attempt to put the device into mmio mode. There are some slight
799 * complications here with certain systems where the mmio bar isnt
800 * mapped so we have to be sure we can fall back to I/O.
803 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
805 unsigned long bar5 = pci_resource_start(dev, 5);
806 unsigned long barsize = pci_resource_len(dev, 5);
812 * Drop back to PIO if we can't map the mmio. Some
813 * systems seem to get terminally confused in the PCI
817 if(!request_mem_region(bar5, barsize, name))
819 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
823 ioaddr = ioremap(bar5, barsize);
827 release_mem_region(bar5, barsize);
832 pci_set_drvdata(dev, ioaddr);
833 addr = (unsigned long) ioaddr;
835 if (pdev_is_sata(dev)) {
836 writel(0, addr + 0x148);
837 writel(0, addr + 0x1C8);
840 writeb(0, addr + 0xB4);
841 writeb(0, addr + 0xF4);
842 tmpbyte = readb(addr + 0x4A);
844 switch(tmpbyte & 0x30) {
846 /* In 100 MHz clocking, try and switch to 133 */
847 writeb(tmpbyte|0x10, addr + 0x4A);
850 /* On 133Mhz clocking */
853 /* On PCIx2 clocking */
856 /* Clocking is disabled */
857 /* 133 clock attempt to force it on */
858 writeb(tmpbyte & ~0x20, addr + 0x4A);
862 writeb( 0x72, addr + 0xA1);
863 writew( 0x328A, addr + 0xA2);
864 writel(0x62DD62DD, addr + 0xA4);
865 writel(0x43924392, addr + 0xA8);
866 writel(0x40094009, addr + 0xAC);
867 writeb( 0x72, addr + 0xE1);
868 writew( 0x328A, addr + 0xE2);
869 writel(0x62DD62DD, addr + 0xE4);
870 writel(0x43924392, addr + 0xE8);
871 writel(0x40094009, addr + 0xEC);
873 if (pdev_is_sata(dev)) {
874 writel(0xFFFF0000, addr + 0x108);
875 writel(0xFFFF0000, addr + 0x188);
876 writel(0x00680000, addr + 0x148);
877 writel(0x00680000, addr + 0x1C8);
880 tmpbyte = readb(addr + 0x4A);
882 proc_reports_siimage(dev, (tmpbyte>>4), name);
887 * init_chipset_siimage - set up an SI device
891 * Perform the initial PCI set up for this device. Attempt to switch
892 * to 133MHz clocking if the system isn't already set up to do it.
895 static unsigned int __init init_chipset_siimage (struct pci_dev *dev, const char *name)
901 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
903 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
905 pci_read_config_byte(dev, 0x8A, &BA5_EN);
906 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
907 if (setup_mmio_siimage(dev, name)) {
912 pci_write_config_byte(dev, 0x80, 0x00);
913 pci_write_config_byte(dev, 0x84, 0x00);
914 pci_read_config_byte(dev, 0x8A, &tmpbyte);
915 switch(tmpbyte & 0x30) {
917 /* 133 clock attempt to force it on */
918 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
920 /* if clocking is disabled */
921 /* 133 clock attempt to force it on */
922 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
927 /* BIOS set PCI x2 clocking */
931 pci_read_config_byte(dev, 0x8A, &tmpbyte);
933 pci_write_config_byte(dev, 0xA1, 0x72);
934 pci_write_config_word(dev, 0xA2, 0x328A);
935 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
936 pci_write_config_dword(dev, 0xA8, 0x43924392);
937 pci_write_config_dword(dev, 0xAC, 0x40094009);
938 pci_write_config_byte(dev, 0xB1, 0x72);
939 pci_write_config_word(dev, 0xB2, 0x328A);
940 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
941 pci_write_config_dword(dev, 0xB8, 0x43924392);
942 pci_write_config_dword(dev, 0xBC, 0x40094009);
944 proc_reports_siimage(dev, (tmpbyte>>4), name);
949 * init_mmio_iops_siimage - set up the iops for MMIO
950 * @hwif: interface to set up
952 * The basic setup here is fairly simple, we can use standard MMIO
953 * operations. However we do have to set the taskfile register offsets
954 * by hand as there isnt a standard defined layout for them this
957 * The hardware supports buffered taskfiles and also some rather nice
958 * extended PRD tables. Unfortunately right now we don't.
961 static void __init init_mmio_iops_siimage (ide_hwif_t *hwif)
963 struct pci_dev *dev = hwif->pci_dev;
964 void *addr = pci_get_drvdata(dev);
965 u8 ch = hwif->channel;
970 * Fill in the basic HWIF bits
973 default_hwif_mmiops(hwif);
974 hwif->hwif_data = addr;
977 * Now set up the hw. We have to do this ourselves as
978 * the MMIO layout isnt the same as the the standard port
982 memset(&hw, 0, sizeof(hw_regs_t));
985 base = (unsigned long)addr;
992 * The buffered task file doesn't have status/control
993 * so we can't currently use it sanely since we want to
997 // hwif->no_lba48 = 1;
999 hw.io_ports[IDE_DATA_OFFSET] = base;
1000 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
1001 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
1002 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
1003 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
1004 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
1005 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
1006 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
1007 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
1009 hw.io_ports[IDE_IRQ_OFFSET] = 0;
1011 if (pdev_is_sata(dev)) {
1012 base = (unsigned long) addr;
1015 hw.sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
1016 hw.sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
1017 hw.sata_scr[SATA_CONTROL_OFFSET]= base + 0x100;
1018 hw.sata_misc[SATA_MISC_OFFSET] = base + 0x140;
1019 hw.sata_misc[SATA_PHY_OFFSET] = base + 0x144;
1020 hw.sata_misc[SATA_IEN_OFFSET] = base + 0x148;
1023 hw.irq = hwif->pci_dev->irq;
1025 memcpy(&hwif->hw, &hw, sizeof(hw));
1026 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
1028 if (is_sata(hwif)) {
1029 memcpy(hwif->sata_scr, hwif->hw.sata_scr, sizeof(hwif->hw.sata_scr));
1030 memcpy(hwif->sata_misc, hwif->hw.sata_misc, sizeof(hwif->hw.sata_misc));
1035 base = (unsigned long) addr;
1037 #ifdef SIIMAGE_LARGE_DMA
1038 /* Watch the brackets - even Ken and Dennis get some language design wrong */
1039 hwif->dma_base = base + (ch ? 0x18 : 0x10);
1040 hwif->dma_base2 = base + (ch ? 0x08 : 0x00);
1041 hwif->dma_prdtable = hwif->dma_base2 + 4;
1042 #else /* ! SIIMAGE_LARGE_DMA */
1043 hwif->dma_base = base + (ch ? 0x08 : 0x00);
1044 hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
1045 #endif /* SIIMAGE_LARGE_DMA */
1049 static int is_dev_seagate_sata(ide_drive_t *drive)
1051 const char *s = &drive->id->model[0];
1054 if (!drive->present)
1057 len = strnlen(s, sizeof(drive->id->model));
1059 if ((len > 4) && (!memcmp(s, "ST", 2))) {
1060 if ((!memcmp(s + len - 2, "AS", 2)) ||
1061 (!memcmp(s + len - 3, "ASL", 3))) {
1062 printk(KERN_INFO "%s: applying pessimistic Seagate "
1063 "errata fix\n", drive->name);
1071 * init_iops_siimage - set up iops
1072 * @hwif: interface to set up
1074 * Do the basic setup for the SIIMAGE hardware interface
1075 * and then do the MMIO setup if we can. This is the first
1076 * look in we get for setting up the hwif so that we
1077 * can get the iops right before using them.
1080 static void __init init_iops_siimage (ide_hwif_t *hwif)
1082 struct pci_dev *dev = hwif->pci_dev;
1085 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1088 hwif->hwif_data = 0;
1091 if (is_sata(hwif) && is_dev_seagate_sata(&hwif->drives[0]))
1094 if (pci_get_drvdata(dev) == NULL)
1096 init_mmio_iops_siimage(hwif);
1100 * ata66_siimage - check for 80 pin cable
1101 * @hwif: interface to check
1103 * Check for the presence of an ATA66 capable cable on the
1107 static unsigned int __init ata66_siimage (ide_hwif_t *hwif)
1109 unsigned long addr = siimage_selreg(hwif, 0);
1110 if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1112 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1113 return (ata66 & 0x01) ? 1 : 0;
1116 return (hwif->INB(addr) & 0x01) ? 1 : 0;
1120 * init_hwif_siimage - set up hwif structs
1121 * @hwif: interface to set up
1123 * We do the basic set up of the interface structure. The SIIMAGE
1124 * requires several custom handlers so we override the default
1125 * ide DMA handlers appropriately
1128 static void __init init_hwif_siimage (ide_hwif_t *hwif)
1132 hwif->resetproc = &siimage_reset;
1133 hwif->speedproc = &siimage_tune_chipset;
1134 hwif->tuneproc = &siimage_tuneproc;
1135 hwif->reset_poll = &siimage_reset_poll;
1136 hwif->pre_reset = &siimage_pre_reset;
1139 hwif->busproc = &siimage_busproc;
1141 if (!hwif->dma_base) {
1142 hwif->drives[0].autotune = 1;
1143 hwif->drives[1].autotune = 1;
1147 hwif->ultra_mask = 0x7f;
1148 hwif->mwdma_mask = 0x07;
1149 hwif->swdma_mask = 0x07;
1152 hwif->atapi_dma = 1;
1154 hwif->ide_dma_check = &siimage_config_drive_for_dma;
1155 if (!(hwif->udma_four))
1156 hwif->udma_four = ata66_siimage(hwif);
1159 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1160 hwif->ide_dma_verbose = &siimage_mmio_ide_dma_verbose;
1162 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1166 * The BIOS often doesn't set up DMA on this controller
1167 * so we always do it.
1171 hwif->drives[0].autodma = hwif->autodma;
1172 hwif->drives[1].autodma = hwif->autodma;
1176 * siimage_init_one - pci layer discovery entry
1178 * @id: ident table entry
1180 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1181 * We then use the IDE PCI generic helper to do most of the work.
1184 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1186 ide_pci_device_t *d = &siimage_chipsets[id->driver_data];
1187 if (dev->device != d->device)
1189 ide_setup_pci_device(dev, d);
1193 static struct pci_device_id siimage_pci_tbl[] = {
1194 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1195 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1196 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1199 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1201 static struct pci_driver driver = {
1203 .id_table = siimage_pci_tbl,
1204 .probe = siimage_init_one,
1207 static int siimage_ide_init(void)
1209 return ide_pci_register_driver(&driver);
1212 module_init(siimage_ide_init);
1214 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1215 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1216 MODULE_LICENSE("GPL");