2 * linux/drivers/ide/pci/sis5513.c Version 0.16ac+vp Jun 18, 2003
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
6 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
7 * May be copied or modified under the terms of the GNU General Public License
12 * SiS Taiwan : for direct support and hardware.
13 * Daniela Engert : for initial ATA100 advices and numerous others.
14 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
15 * for checking code correctness, providing patches.
18 * Original tests and design on the SiS620 chipset.
19 * ATA100 tests and design on the SiS735 chipset.
20 * ATA16/33 support from specs
21 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
22 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
25 * SiS chipset documentation available under NDA to companies only
26 * (not to individuals).
30 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
31 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
32 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
34 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
35 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
36 * can figure out that we have a more modern and more capable 5513 by looking
37 * for the respective NorthBridge IDs.
39 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
40 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
41 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
42 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
43 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
47 #include <linux/config.h>
48 #include <linux/types.h>
49 #include <linux/module.h>
50 #include <linux/kernel.h>
51 #include <linux/delay.h>
52 #include <linux/timer.h>
54 #include <linux/ioport.h>
55 #include <linux/blkdev.h>
56 #include <linux/hdreg.h>
58 #include <linux/interrupt.h>
59 #include <linux/pci.h>
60 #include <linux/init.h>
61 #include <linux/ide.h>
65 #include "ide-timing.h"
68 /* registers layout and init values are chipset family dependant */
73 #define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
75 #define ATA_133a 0x06 // SiS961b with 133 support
76 #define ATA_133 0x07 // SiS962/963
78 static u8 chipset_family;
88 } SiSHostChipInfo[] = {
89 { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
90 { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
91 { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
92 { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
93 { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
95 { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
96 { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
98 { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
99 { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
100 { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
101 { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
102 { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
104 { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
105 { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
106 { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
107 { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
108 { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
109 { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
111 { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
112 { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
113 { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
116 /* Cycle time bits and values vary across chip dma capabilities
117 These three arrays hold the register layout and the values to set.
118 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
120 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
121 static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
122 static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
123 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
124 {0,0,0,0,0,0,0}, /* no udma */
125 {0,0,0,0,0,0,0}, /* no udma */
126 {3,2,1,0,0,0,0}, /* ATA_33 */
127 {7,5,3,2,1,0,0}, /* ATA_66 */
128 {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
129 {11,7,5,4,2,1,0}, /* ATA_100 */
130 {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
131 {15,10,7,5,3,2,1}, /* ATA_133 */
133 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
134 See SiS962 data sheet for more detail */
135 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
136 {0,0,0,0,0,0,0}, /* no udma */
137 {0,0,0,0,0,0,0}, /* no udma */
145 /* Initialize time, Active time, Recovery time vary across
146 IDE clock settings. These 3 arrays hold the register value
147 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
148 static u8 ini_time_value[][8] = {
158 static u8 act_time_value[][8] = {
162 {19,19,19,5,4,14,5,4},
163 {19,19,19,5,4,14,5,4},
164 {28,28,28,7,6,21,7,6},
165 {38,38,38,10,9,28,10,9},
166 {38,38,38,10,9,28,10,9},
168 static u8 rco_time_value[][8] = {
175 {40,12,4,12,5,34,12,5},
176 {40,12,4,12,5,34,12,5},
180 * Printing configuration
182 /* Used for chipset type printing at boot time */
183 static char* chipset_capability[] = {
186 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
187 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
190 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
191 #include <linux/stat.h>
192 #include <linux/proc_fs.h>
194 static u8 sis_proc = 0;
196 static struct pci_dev *bmide_dev;
198 static char* cable_type[] = {
203 static char* recovery_time[] ={
204 "12 PCICLK", "1 PCICLK",
205 "2 PCICLK", "3 PCICLK",
206 "4 PCICLK", "5 PCICLCK",
207 "6 PCICLK", "7 PCICLCK",
208 "8 PCICLK", "9 PCICLCK",
209 "10 PCICLK", "11 PCICLK",
210 "13 PCICLK", "14 PCICLK",
211 "15 PCICLK", "15 PCICLK"
214 static char* active_time[] = {
215 "8 PCICLK", "1 PCICLCK",
216 "2 PCICLK", "3 PCICLK",
217 "4 PCICLK", "5 PCICLK",
218 "6 PCICLK", "12 PCICLK"
221 static char* cycle_time[] = {
232 /* Generic add master or slave info function */
233 static char* get_drives_info (char *buffer, u8 pos)
235 u8 reg00, reg01, reg10, reg11; /* timing registers */
239 /* Postwrite/Prefetch */
240 if (chipset_family < ATA_133) {
241 pci_read_config_byte(bmide_dev, 0x4b, ®00);
242 p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
243 pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
244 (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
245 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
246 (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
247 (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
248 pci_read_config_byte(bmide_dev, 0x40+2*pos, ®00);
249 pci_read_config_byte(bmide_dev, 0x41+2*pos, ®01);
250 pci_read_config_byte(bmide_dev, 0x44+2*pos, ®10);
251 pci_read_config_byte(bmide_dev, 0x45+2*pos, ®11);
255 pci_read_config_dword(bmide_dev, 0x54, ®54h);
256 if (reg54h & 0x40000000) {
257 // Configuration space remapped to 0x70
260 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, ®dw0);
261 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, ®dw1);
263 p += sprintf(p, "Drive %d:\n", pos);
268 if (chipset_family >= ATA_133) {
269 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
270 (regdw0 & 0x04) ? "Enabled" : "Disabled",
271 (regdw1 & 0x04) ? "Enabled" : "Disabled");
272 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
273 cycle_time[(regdw0 & 0xF0) >> 4],
274 cycle_time[(regdw1 & 0xF0) >> 4]);
275 } else if (chipset_family >= ATA_33) {
276 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
277 (reg01 & 0x80) ? "Enabled" : "Disabled",
278 (reg11 & 0x80) ? "Enabled" : "Disabled");
280 p += sprintf(p, " UDMA Cycle Time ");
281 switch(chipset_family) {
282 case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
284 case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
286 case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
287 default: p += sprintf(p, "?"); break;
289 p += sprintf(p, " \t UDMA Cycle Time ");
290 switch(chipset_family) {
291 case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
293 case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
295 case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
296 default: p += sprintf(p, "?"); break;
298 p += sprintf(p, "\n");
302 if (chipset_family < ATA_133) { /* else case TODO */
305 p += sprintf(p, " Data Active Time ");
306 switch(chipset_family) {
307 case ATA_16: /* confirmed */
310 case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
312 case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
313 default: p += sprintf(p, "?"); break;
315 p += sprintf(p, " \t Data Active Time ");
316 switch(chipset_family) {
320 case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
322 case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
323 default: p += sprintf(p, "?"); break;
325 p += sprintf(p, "\n");
328 /* warning: may need (reg&0x07) for pre ATA66 chips */
329 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
330 recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
336 static char* get_masters_info(char* buffer)
338 return get_drives_info(buffer, 0);
341 static char* get_slaves_info(char* buffer)
343 return get_drives_info(buffer, 1);
346 /* Main get_info, called on /proc/ide/sis reads */
347 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
354 p += sprintf(p, "\nSiS 5513 ");
355 switch(chipset_family) {
356 case ATA_16: p += sprintf(p, "DMA 16"); break;
357 case ATA_33: p += sprintf(p, "Ultra 33"); break;
358 case ATA_66: p += sprintf(p, "Ultra 66"); break;
360 case ATA_100: p += sprintf(p, "Ultra 100"); break;
362 case ATA_133: p += sprintf(p, "Ultra 133"); break;
363 default: p+= sprintf(p, "Unknown???"); break;
365 p += sprintf(p, " chipset\n");
366 p += sprintf(p, "--------------- Primary Channel "
367 "---------------- Secondary Channel "
371 pci_read_config_byte(bmide_dev, 0x4a, ®);
372 if (chipset_family == ATA_133) {
373 pci_read_config_word(bmide_dev, 0x50, ®2);
374 pci_read_config_word(bmide_dev, 0x52, ®3);
376 p += sprintf(p, "Channel Status: ");
377 if (chipset_family < ATA_66) {
378 p += sprintf(p, "%s \t \t \t \t %s\n",
379 (reg & 0x04) ? "On" : "Off",
380 (reg & 0x02) ? "On" : "Off");
381 } else if (chipset_family < ATA_133) {
382 p += sprintf(p, "%s \t \t \t \t %s \n",
383 (reg & 0x02) ? "On" : "Off",
384 (reg & 0x04) ? "On" : "Off");
385 } else { /* ATA_133 */
386 p += sprintf(p, "%s \t \t \t \t %s \n",
387 (reg2 & 0x02) ? "On" : "Off",
388 (reg3 & 0x02) ? "On" : "Off");
392 pci_read_config_byte(bmide_dev, 0x09, ®);
393 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
394 (reg & 0x01) ? "Native" : "Compatible",
395 (reg & 0x04) ? "Native" : "Compatible");
398 if (chipset_family >= ATA_133) {
399 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
400 (reg2 & 0x01) ? cable_type[1] : cable_type[0],
401 (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
402 } else if (chipset_family > ATA_33) {
403 pci_read_config_byte(bmide_dev, 0x48, ®);
404 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
405 (reg & 0x10) ? cable_type[1] : cable_type[0],
406 (reg & 0x20) ? cable_type[1] : cable_type[0]);
410 if (chipset_family < ATA_133) {
411 pci_read_config_word(bmide_dev, 0x4c, ®2);
412 pci_read_config_word(bmide_dev, 0x4e, ®3);
413 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
417 p = get_masters_info(p);
418 p = get_slaves_info(p);
420 len = (p - buffer) - offset;
421 *addr = buffer + offset;
423 return len > count ? count : len;
425 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
427 static u8 sis5513_ratemask (ide_drive_t *drive)
429 u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 };
430 u8 mode = rates[chipset_family];
432 if (!eighty_ninty_three(drive))
433 mode = min(mode, (u8)1);
438 * Configuration functions
440 /* Enables per-drive prefetch and postwrite */
441 static void config_drive_art_rwp (ide_drive_t *drive)
443 ide_hwif_t *hwif = HWIF(drive);
444 struct pci_dev *dev = hwif->pci_dev;
447 u8 rw_prefetch = (0x11 << drive->dn);
449 if (drive->media != ide_disk)
451 pci_read_config_byte(dev, 0x4b, ®4bh);
453 if ((reg4bh & rw_prefetch) != rw_prefetch)
454 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
458 /* Set per-drive active and recovery time */
459 static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
461 ide_hwif_t *hwif = HWIF(drive);
462 struct pci_dev *dev = hwif->pci_dev;
464 u8 timing, drive_pci, test1, test2;
466 u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
467 u16 xfer_pio = drive->id->eide_pio_modes;
469 config_drive_art_rwp(drive);
470 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
475 if (drive->id->eide_pio_iordy > 0) {
478 (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
481 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
482 (drive->id->eide_pio_modes & 2) ? 0x04 :
483 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
486 timing = (xfer_pio >= pio) ? xfer_pio : pio;
488 /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
490 /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
491 if (chipset_family >= ATA_133) {
493 pci_read_config_dword(dev, 0x54, ®54h);
494 if (reg54h & 0x40000000) drive_pci = 0x70;
495 drive_pci += ((drive->dn)*0x4);
497 drive_pci += ((drive->dn)*0x2);
500 /* register layout changed with newer ATA100 chips */
501 if (chipset_family < ATA_100) {
502 pci_read_config_byte(dev, drive_pci, &test1);
503 pci_read_config_byte(dev, drive_pci+1, &test2);
505 /* Clear active and recovery timings */
510 case 4: test1 |= 0x01; test2 |= 0x03; break;
511 case 3: test1 |= 0x03; test2 |= 0x03; break;
512 case 2: test1 |= 0x04; test2 |= 0x04; break;
513 case 1: test1 |= 0x07; test2 |= 0x06; break;
516 pci_write_config_byte(dev, drive_pci, test1);
517 pci_write_config_byte(dev, drive_pci+1, test2);
518 } else if (chipset_family < ATA_133) {
519 switch(timing) { /* active recovery
521 case 4: test1 = 0x30|0x01; break;
522 case 3: test1 = 0x30|0x03; break;
523 case 2: test1 = 0x40|0x04; break;
524 case 1: test1 = 0x60|0x07; break;
527 pci_write_config_byte(dev, drive_pci, test1);
528 } else { /* ATA_133 */
530 pci_read_config_dword(dev, drive_pci, &test3);
533 test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
534 test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
535 test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
537 test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
538 test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
539 test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
541 pci_write_config_dword(dev, drive_pci, test3);
545 static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
548 pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
549 config_art_rwp_pio(drive, pio);
550 return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
553 static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
555 ide_hwif_t *hwif = HWIF(drive);
556 struct pci_dev *dev = hwif->pci_dev;
558 u8 drive_pci, reg, speed;
561 speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed);
563 /* See config_art_rwp_pio for drive pci config registers */
565 if (chipset_family >= ATA_133) {
567 pci_read_config_dword(dev, 0x54, ®54h);
568 if (reg54h & 0x40000000) drive_pci = 0x70;
569 drive_pci += ((drive->dn)*0x4);
570 pci_read_config_dword(dev, (unsigned long)drive_pci, ®dw);
571 /* Disable UDMA bit for non UDMA modes on UDMA chips */
572 if (speed < XFER_UDMA_0) {
574 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
578 drive_pci += ((drive->dn)*0x2);
579 pci_read_config_byte(dev, drive_pci+1, ®);
580 /* Disable UDMA bit for non UDMA modes on UDMA chips */
581 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
583 pci_write_config_byte(dev, drive_pci+1, reg);
587 /* Config chip for mode */
596 if (chipset_family >= ATA_133) {
599 /* check if ATA133 enable */
601 regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
602 regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
604 /* if ATA133 disable, we should not set speed above UDMA5 */
605 if (speed > XFER_UDMA_5)
607 regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
608 regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
610 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
612 /* Force the UDMA bit on if we want to use UDMA */
614 /* clean reg cycle time bits */
615 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
616 << cycle_time_offset[chipset_family]);
617 /* set reg cycle time bits */
618 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
619 << cycle_time_offset[chipset_family];
620 pci_write_config_byte(dev, drive_pci+1, reg);
630 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
631 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
632 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
633 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
635 default: return((int) config_chipset_for_pio(drive, 0));
638 return ((int) ide_config_drive_speed(drive, speed));
641 static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
643 (void) config_chipset_for_pio(drive, pio);
647 * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
649 static int config_chipset_for_dma (ide_drive_t *drive)
651 u8 speed = ide_dma_speed(drive, sis5513_ratemask(drive));
654 printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n",
655 drive->dn, drive->id->dma_ultra);
661 sis5513_tune_chipset(drive, speed);
662 return ide_dma_enable(drive);
665 static int sis5513_config_drive_xfer_rate (ide_drive_t *drive)
667 ide_hwif_t *hwif = HWIF(drive);
668 struct hd_driveid *id = drive->id;
670 drive->init_speed = 0;
672 if (id && (id->capability & 1) && drive->autodma) {
673 /* Consult the list of known "bad" drives */
674 if (__ide_dma_bad_drive(drive))
676 if (id->field_valid & 4) {
677 if (id->dma_ultra & hwif->ultra_mask) {
678 /* Force if Capable UltraDMA */
679 int dma = config_chipset_for_dma(drive);
680 if ((id->field_valid & 2) && !dma)
683 } else if (id->field_valid & 2) {
685 if ((id->dma_mword & hwif->mwdma_mask) ||
686 (id->dma_1word & hwif->swdma_mask)) {
687 /* Force if Capable regular DMA modes */
688 if (!config_chipset_for_dma(drive))
691 } else if (__ide_dma_good_drive(drive) &&
692 (id->eide_dma_time < 150)) {
693 /* Consult the list of known "good" drives */
694 if (!config_chipset_for_dma(drive))
699 return hwif->ide_dma_on(drive);
700 } else if ((id->capability & 8) || (id->field_valid & 2)) {
703 sis5513_tune_drive(drive, 5);
704 return hwif->ide_dma_off_quietly(drive);
706 /* IORDY not supported */
710 /* initiates/aborts (U)DMA read/write operations on a drive. */
711 static int sis5513_config_xfer_rate (ide_drive_t *drive)
713 config_drive_art_rwp(drive);
714 config_art_rwp_pio(drive, 5);
715 return sis5513_config_drive_xfer_rate(drive);
719 Future simpler config_xfer_rate :
720 When ide_find_best_mode is made bad-drive aware
721 - remove config_drive_xfer_rate and config_chipset_for_dma,
722 - replace config_xfer_rate with the following
724 static int sis5513_config_xfer_rate (ide_drive_t *drive)
726 u16 w80 = HWIF(drive)->udma_four;
729 config_drive_art_rwp(drive);
730 config_art_rwp_pio(drive, 5);
732 speed = ide_find_best_mode(drive,
733 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
734 (chipset_family >= ATA_33 ? XFER_UDMA : 0) |
735 (w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) |
736 (w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) |
737 (w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0));
739 sis5513_tune_chipset(drive, speed);
741 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
742 return HWIF(drive)->ide_dma_on(drive);
743 return HWIF(drive)->ide_dma_off_quietly(drive);
747 /* Chip detection and general config */
748 static unsigned int __init init_chipset_sis5513 (struct pci_dev *dev, const char *name)
750 struct pci_dev *host;
755 for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
757 host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
762 chipset_family = SiSHostChipInfo[i].chipset_family;
764 /* Special case for SiS630 : 630S/ET is ATA_100a */
765 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
767 pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
769 chipset_family = ATA_100a;
772 printk(KERN_INFO "SIS5513: %s %s controller\n",
773 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
776 if (!chipset_family) { /* Belongs to pci-quirks */
781 /* Disable ID masking and register remapping */
782 pci_read_config_dword(dev, 0x54, &idemisc);
783 pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
784 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
785 pci_write_config_dword(dev, 0x54, idemisc);
787 if (trueid == 0x5518) {
788 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
789 chipset_family = ATA_133;
793 if (!chipset_family) { /* Belongs to pci-quirks */
795 struct pci_dev *lpc_bridge;
801 pci_read_config_byte(dev, 0x4a, &idecfg);
802 pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
803 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
804 pci_write_config_byte(dev, 0x4a, idecfg);
806 if (trueid == 0x5517) { /* SiS 961/961B */
808 lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */
809 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
810 pci_read_config_byte(dev, 0x49, &prefctl);
812 if (sbrev == 0x10 && (prefctl & 0x80)) {
813 printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
814 chipset_family = ATA_133a;
816 printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
817 chipset_family = ATA_100;
825 /* Make general config ops here
826 1/ tell IDE channels to operate in Compatibility mode only
827 2/ tell old chips to allow per drive IDE timings */
833 switch(chipset_family) {
835 /* SiS962 operation mode */
836 pci_read_config_word(dev, 0x50, ®w);
838 pci_write_config_word(dev, 0x50, regw&0xfff7);
839 pci_read_config_word(dev, 0x52, ®w);
841 pci_write_config_word(dev, 0x52, regw&0xfff7);
846 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
847 /* Set compatibility bit */
848 pci_read_config_byte(dev, 0x49, ®);
850 pci_write_config_byte(dev, 0x49, reg|0x01);
856 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
858 /* On ATA_66 chips the bit was elsewhere */
859 pci_read_config_byte(dev, 0x52, ®);
861 pci_write_config_byte(dev, 0x52, reg|0x04);
865 /* On ATA_33 we didn't have a single bit to set */
866 pci_read_config_byte(dev, 0x09, ®);
867 if ((reg & 0x0f) != 0x00) {
868 pci_write_config_byte(dev, 0x09, reg&0xf0);
871 /* force per drive recovery and active timings
872 needed on ATA_33 and below chips */
873 pci_read_config_byte(dev, 0x52, ®);
875 pci_write_config_byte(dev, 0x52, reg|0x08);
880 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
884 ide_pci_create_host_proc("sis", sis_get_info);
892 static unsigned int __init ata66_sis5513 (ide_hwif_t *hwif)
896 if (chipset_family >= ATA_133) {
898 u16 reg_addr = hwif->channel ? 0x52: 0x50;
899 pci_read_config_word(hwif->pci_dev, reg_addr, ®w);
900 ata66 = (regw & 0x8000) ? 0 : 1;
901 } else if (chipset_family >= ATA_66) {
903 u8 mask = hwif->channel ? 0x20 : 0x10;
904 pci_read_config_byte(hwif->pci_dev, 0x48, ®48h);
905 ata66 = (reg48h & mask) ? 0 : 1;
910 static void __init init_hwif_sis5513 (ide_hwif_t *hwif)
915 hwif->irq = hwif->channel ? 15 : 14;
917 hwif->tuneproc = &sis5513_tune_drive;
918 hwif->speedproc = &sis5513_tune_chipset;
920 if (!(hwif->dma_base)) {
921 hwif->drives[0].autotune = 1;
922 hwif->drives[1].autotune = 1;
927 hwif->ultra_mask = 0x7f;
928 hwif->mwdma_mask = 0x07;
929 hwif->swdma_mask = 0x07;
934 if (!(hwif->udma_four))
935 hwif->udma_four = ata66_sis5513(hwif);
937 if (chipset_family > ATA_16) {
938 hwif->ide_dma_check = &sis5513_config_xfer_rate;
942 hwif->drives[0].autodma = hwif->autodma;
943 hwif->drives[1].autodma = hwif->autodma;
947 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
949 ide_setup_pci_device(dev, &sis5513_chipsets[id->driver_data]);
953 static struct pci_device_id sis5513_pci_tbl[] = {
954 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
957 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
959 static struct pci_driver driver = {
961 .id_table = sis5513_pci_tbl,
962 .probe = sis5513_init_one,
965 static int sis5513_ide_init(void)
967 return ide_pci_register_driver(&driver);
970 module_init(sis5513_ide_init);
972 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
973 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
974 MODULE_LICENSE("GPL");
979 * - Use drivers/ide/ide-timing.h !
980 * - More checks in the config registers (force values instead of
981 * relying on the BIOS setting them correctly).
982 * - Further optimisations ?
983 * . for example ATA66+ regs 0x48 & 0x4A