2 * linux/drivers/ide/pci/sl82c105.c
4 * SL82C105/Winbond 553 IDE driver
8 * Drive tuning added from Rebel.com's kernel sources
9 * -- Russell King (15/11/98) linux@arm.linux.org.uk
11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
16 #include <linux/config.h>
17 #include <linux/types.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/timer.h>
22 #include <linux/ioport.h>
23 #include <linux/interrupt.h>
24 #include <linux/blkdev.h>
25 #include <linux/hdreg.h>
26 #include <linux/pci.h>
27 #include <linux/ide.h>
37 #define DBG(arg) printk arg
42 * SL82C105 PCI config register 0x40 bits.
44 #define CTRL_IDE_IRQB (1 << 30)
45 #define CTRL_IDE_IRQA (1 << 28)
46 #define CTRL_LEGIRQ (1 << 11)
47 #define CTRL_P1F16 (1 << 5)
48 #define CTRL_P1EN (1 << 4)
49 #define CTRL_P0F16 (1 << 1)
50 #define CTRL_P0EN (1 << 0)
53 * Convert a PIO mode and cycle time to the required on/off
54 * times for the interface. This has protection against run-away
57 static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
62 cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
63 cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
75 return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
79 * Configure the drive and chipset for PIO
81 static void config_for_pio(ide_drive_t *drive, int pio, int report, int chipset_only)
83 ide_hwif_t *hwif = HWIF(drive);
84 struct pci_dev *dev = hwif->pci_dev;
87 unsigned int xfer_mode, reg;
89 DBG(("config_for_pio(drive:%s, pio:%d, report:%d, chipset_only:%d)\n",
90 drive->name, pio, report, chipset_only));
92 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
94 pio = ide_get_best_pio_mode(drive, pio, 5, &p);
96 xfer_mode = XFER_PIO_0 + pio;
98 if (chipset_only || ide_config_drive_speed(drive, xfer_mode) == 0) {
99 drv_ctrl = get_timing_sl82c105(&p);
100 drive->pio_speed = xfer_mode;
102 drive->pio_speed = XFER_PIO_0;
104 if (drive->using_dma == 0) {
106 * If we are actually using MW DMA, then we can not
107 * reprogram the interface drive control register.
109 pci_write_config_word(dev, reg, drv_ctrl);
110 pci_read_config_word(dev, reg, &drv_ctrl);
113 printk("%s: selected %s (%dns) (%04X)\n", drive->name,
114 ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
120 * Configure the drive and the chipset for DMA
122 static int config_for_dma (ide_drive_t *drive)
124 ide_hwif_t *hwif = HWIF(drive);
125 struct pci_dev *dev = hwif->pci_dev;
128 DBG(("config_for_dma(drive:%s)\n", drive->name));
130 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
132 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0)
135 pci_write_config_word(dev, reg, 0x0240);
141 * Check to see if the drive and
142 * chipset is capable of DMA mode
145 static int sl82c105_check_drive (ide_drive_t *drive)
147 ide_hwif_t *hwif = HWIF(drive);
149 DBG(("sl82c105_check_drive(drive:%s)\n", drive->name));
152 struct hd_driveid *id = drive->id;
157 if (!id || !(id->capability & 1))
160 /* Consult the list of known "bad" drives */
161 if (__ide_dma_bad_drive(drive))
164 if (id->field_valid & 2) {
165 if ((id->dma_mword & hwif->mwdma_mask) ||
166 (id->dma_1word & hwif->swdma_mask))
167 return hwif->ide_dma_on(drive);
170 if (__ide_dma_good_drive(drive))
171 return hwif->ide_dma_on(drive);
174 return hwif->ide_dma_off_quietly(drive);
178 * The SL82C105 holds off all IDE interrupts while in DMA mode until
179 * all DMA activity is completed. Sometimes this causes problems (eg,
180 * when the drive wants to report an error condition).
182 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
183 * state machine. We need to kick this to work around various bugs.
185 static inline void sl82c105_reset_host(struct pci_dev *dev)
189 pci_read_config_word(dev, 0x7e, &val);
190 pci_write_config_word(dev, 0x7e, val | (1 << 2));
191 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
195 * If we get an IRQ timeout, it might be that the DMA state machine
196 * got confused. Fix from Todd Inglett. Details from Winbond.
198 * This function is called when the IDE timer expires, the drive
199 * indicates that it is READY, and we were waiting for DMA to complete.
201 static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
203 ide_hwif_t *hwif = HWIF(drive);
204 struct pci_dev *dev = hwif->pci_dev;
205 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
206 unsigned long dma_base = hwif->dma_base;
208 printk("sl82c105: lost IRQ: resetting host\n");
211 * Check the raw interrupt from the drive.
213 pci_read_config_dword(dev, 0x40, &val);
215 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
218 * Was DMA enabled? If so, disable it - we're resetting the
219 * host. The IDE layer will be handling the drive for us.
221 val = hwif->INB(dma_base);
223 outb(val & ~1, dma_base);
224 printk("sl82c105: DMA was enabled\n");
227 sl82c105_reset_host(dev);
229 /* ide_dmaproc would return 1, so we do as well */
234 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
235 * Winbond recommend that the DMA state machine is reset prior to
236 * setting the bus master DMA enable bit.
238 * The generic IDE core will have disabled the BMEN bit before this
239 * function is called.
241 static int sl82c105_ide_dma_begin(ide_drive_t *drive)
243 ide_hwif_t *hwif = HWIF(drive);
244 struct pci_dev *dev = hwif->pci_dev;
246 // DBG(("sl82c105_ide_dma_begin(drive:%s)\n", drive->name));
248 sl82c105_reset_host(dev);
249 return __ide_dma_begin(drive);
252 static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
254 ide_hwif_t *hwif = HWIF(drive);
255 struct pci_dev *dev = hwif->pci_dev;
257 DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));
259 sl82c105_reset_host(dev);
260 return __ide_dma_timeout(drive);
263 static int sl82c105_ide_dma_on (ide_drive_t *drive)
265 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
267 if (config_for_dma(drive)) {
268 config_for_pio(drive, 4, 0, 0);
269 return HWIF(drive)->ide_dma_off_quietly(drive);
271 printk(KERN_INFO "%s: DMA enabled\n", drive->name);
272 return __ide_dma_on(drive);
275 static int sl82c105_ide_dma_off_quietly (ide_drive_t *drive)
277 u8 speed = XFER_PIO_0;
280 DBG(("sl82c105_ide_dma_off_quietly(drive:%s)\n", drive->name));
282 rc = __ide_dma_off_quietly(drive);
283 if (drive->pio_speed)
284 speed = drive->pio_speed - XFER_PIO_0;
285 config_for_pio(drive, speed, 0, 1);
286 drive->current_speed = drive->pio_speed;
292 * Ok, that is nasty, but we must make sure the DMA timings
293 * won't be used for a PIO access. The solution here is
294 * to make sure the 16 bits mode is diabled on the channel
295 * when DMA is enabled, thus causing the chip to use PIO0
296 * timings for those operations.
298 static void sl82c105_selectproc(ide_drive_t *drive)
300 ide_hwif_t *hwif = HWIF(drive);
301 struct pci_dev *dev = hwif->pci_dev;
304 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
306 mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
307 old = val = *((u32 *)&hwif->hwif_data);
308 if (drive->using_dma)
313 pci_write_config_dword(dev, 0x40, val);
314 *((u32 *)&hwif->hwif_data) = val;
319 * ATA reset will clear the 16 bits mode in the control
320 * register, we need to update our cache
322 static void sl82c105_resetproc(ide_drive_t *drive)
324 ide_hwif_t *hwif = HWIF(drive);
325 struct pci_dev *dev = hwif->pci_dev;
328 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
330 pci_read_config_dword(dev, 0x40, &val);
331 *((u32 *)&hwif->hwif_data) = val;
335 * We only deal with PIO mode here - DMA mode 'using_dma' is not
336 * initialised at the point that this function is called.
338 static void tune_sl82c105(ide_drive_t *drive, u8 pio)
340 DBG(("tune_sl82c105(drive:%s)\n", drive->name));
342 config_for_pio(drive, pio, 1, 0);
345 * We support 32-bit I/O on this interface, and it
346 * doesn't have problems with interrupts.
353 * Return the revision of the Winbond bridge
354 * which this function is part of.
356 static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
358 struct pci_dev *bridge;
362 * The bridge should be part of the same device, but function 0.
364 bridge = pci_find_slot(dev->bus->number,
365 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
370 * Make sure it is a Winbond 553 and is an ISA bridge.
372 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
373 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
374 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA)
378 * We need to find function 0's revision, not function 1
380 pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
386 * Enable the PCI device
388 * --BenH: It's arch fixup code that should enable channels that
389 * have not been enabled by firmware. I decided we can still enable
390 * channel 0 here at least, but channel 1 has to be enabled by
391 * firmware or arch code. We still set both to 16 bits mode.
393 static unsigned int __init init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
397 DBG(("init_chipset_sl82c105()\n"));
399 pci_read_config_dword(dev, 0x40, &val);
400 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
401 pci_write_config_dword(dev, 0x40, val);
406 static void __init init_dma_sl82c105(ide_hwif_t *hwif, unsigned long dma_base)
411 DBG(("init_dma_sl82c105(hwif: ide%d, dma_base: 0x%08x)\n", hwif->index, dma_base));
418 dma_state = hwif->INB(dma_base + 2);
419 rev = sl82c105_bridge_revision(hwif->pci_dev);
421 printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
429 hwif->OUTB(dma_state, dma_base + 2);
431 ide_setup_dma(hwif, dma_base, 8);
435 * Initialise the chip
438 static void __init init_hwif_sl82c105(ide_hwif_t *hwif)
440 struct pci_dev *dev = hwif->pci_dev;
443 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
445 hwif->tuneproc = tune_sl82c105;
446 hwif->selectproc = sl82c105_selectproc;
447 hwif->resetproc = sl82c105_resetproc;
449 /* Default to PIO 0 for fallback unless tuned otherwise,
450 * we always autotune PIO, this is done before DMA is
451 * checked, so there is no risk of accidentally disabling
454 hwif->drives[0].pio_speed = XFER_PIO_0;
455 hwif->drives[0].autotune = 1;
456 hwif->drives[1].pio_speed = XFER_PIO_1;
457 hwif->drives[1].autotune = 1;
459 pci_read_config_dword(dev, 0x40, &val);
460 *((u32 *)&hwif->hwif_data) = val;
466 hwif->mwdma_mask = 0x07;
467 hwif->swdma_mask = 0x07;
469 #ifdef CONFIG_BLK_DEV_IDEDMA
470 hwif->ide_dma_check = &sl82c105_check_drive;
471 hwif->ide_dma_on = &sl82c105_ide_dma_on;
472 hwif->ide_dma_off_quietly = &sl82c105_ide_dma_off_quietly;
473 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
474 hwif->ide_dma_begin = &sl82c105_ide_dma_begin;
475 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
479 hwif->drives[0].autodma = hwif->autodma;
480 hwif->drives[1].autodma = hwif->autodma;
481 #endif /* CONFIG_BLK_DEV_IDEDMA */
484 static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
486 ide_setup_pci_device(dev, &sl82c105_chipsets[id->driver_data]);
490 static struct pci_device_id sl82c105_pci_tbl[] = {
491 { PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
494 MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
496 static struct pci_driver driver = {
497 .name = "W82C105 IDE",
498 .id_table = sl82c105_pci_tbl,
499 .probe = sl82c105_init_one,
502 static int sl82c105_ide_init(void)
504 return ide_pci_register_driver(&driver);
507 module_init(sl82c105_ide_init);
509 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
510 MODULE_LICENSE("GPL");