5 * VIA IDE driver for Linux. Supported southbridges:
7 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
8 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
11 * Copyright (c) 2000-2002 Vojtech Pavlik
13 * Based on the work of:
19 * Obsolete device documentation publically available from via.com.tw
20 * Current device documentation available under NDA only
24 * This program is free software; you can redistribute it and/or modify it
25 * under the terms of the GNU General Public License version 2 as published by
26 * the Free Software Foundation.
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
33 #include <linux/blkdev.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
39 #include "ide-timing.h"
41 #define DISPLAY_VIA_TIMINGS
43 #define VIA_IDE_ENABLE 0x40
44 #define VIA_IDE_CONFIG 0x41
45 #define VIA_FIFO_CONFIG 0x43
46 #define VIA_MISC_1 0x44
47 #define VIA_MISC_2 0x45
48 #define VIA_MISC_3 0x46
49 #define VIA_DRIVE_TIMING 0x48
50 #define VIA_8BIT_TIMING 0x4e
51 #define VIA_ADDRESS_SETUP 0x4c
52 #define VIA_UDMA_TIMING 0x50
54 #define VIA_UDMA 0x007
55 #define VIA_UDMA_NONE 0x000
56 #define VIA_UDMA_33 0x001
57 #define VIA_UDMA_66 0x002
58 #define VIA_UDMA_100 0x003
59 #define VIA_UDMA_133 0x004
60 #define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */
61 #define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */
62 #define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */
63 #define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */
64 #define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */
65 #define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */
68 * VIA SouthBridge chips.
71 static struct via_isa_bridge {
77 } via_isa_bridges[] = {
78 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
79 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
80 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
81 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
82 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
83 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
84 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
85 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
86 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
87 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
88 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
89 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
90 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
91 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
92 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
93 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
94 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
95 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
99 static struct via_isa_bridge *via_config;
100 static unsigned int via_80w;
101 static unsigned int via_clock;
102 static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
108 #if defined(DISPLAY_VIA_TIMINGS) && defined(CONFIG_PROC_FS)
110 #include <linux/stat.h>
111 #include <linux/proc_fs.h>
113 static u8 via_proc = 0;
114 static unsigned long via_base;
115 static struct pci_dev *bmide_dev, *isa_dev;
117 static char *via_control3[] = { "No limit", "64", "128", "192" };
119 #define via_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
120 #define via_print_drive(name, format, arg...)\
121 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
125 * via_get_info - generate via /proc file
126 * @buffer: buffer for data
127 * @addr: set to start of data to use
128 * @offset: current file offset
129 * @count: size of read
131 * Fills in buffer with the debugging/configuration information for
132 * the VIA chipset tuning and attached drives
135 static int via_get_info(char *buffer, char **addr, off_t offset, int count)
137 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
138 uen[4], udma[4], umul[4], active8b[4], recover8b[4];
139 struct pci_dev *dev = bmide_dev;
140 unsigned int v, u, i;
146 via_print("----------VIA BusMastering IDE Configuration"
149 via_print("Driver Version: 3.38");
150 via_print("South Bridge: VIA %s",
153 pci_read_config_byte(isa_dev, PCI_REVISION_ID, &t);
154 pci_read_config_byte(dev, PCI_REVISION_ID, &x);
155 via_print("Revision: ISA %#x IDE %#x", t, x);
156 via_print("Highest DMA rate: %s",
157 via_dma[via_config->flags & VIA_UDMA]);
159 via_print("BM-DMA base: %#lx", via_base);
160 via_print("PCI clock: %d.%dMHz",
161 via_clock / 1000, via_clock / 100 % 10);
163 pci_read_config_byte(dev, VIA_MISC_1, &t);
164 via_print("Master Read Cycle IRDY: %dws",
166 via_print("Master Write Cycle IRDY: %dws",
168 via_print("BM IDE Status Register Read Retry: %s",
169 (t & 8) ? "yes" : "no");
171 pci_read_config_byte(dev, VIA_MISC_3, &t);
172 via_print("Max DRDY Pulse Width: %s%s",
173 via_control3[(t & 0x03)], (t & 0x03) ? " PCI clocks" : "");
175 via_print("-----------------------Primary IDE"
176 "-------Secondary IDE------");
177 via_print("Read DMA FIFO flush: %10s%20s",
178 (t & 0x80) ? "yes" : "no", (t & 0x40) ? "yes" : "no");
179 via_print("End Sector FIFO flush: %10s%20s",
180 (t & 0x20) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
182 pci_read_config_byte(dev, VIA_IDE_CONFIG, &t);
183 via_print("Prefetch Buffer: %10s%20s",
184 (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
185 via_print("Post Write Buffer: %10s%20s",
186 (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
188 pci_read_config_byte(dev, VIA_IDE_ENABLE, &t);
189 via_print("Enabled: %10s%20s",
190 (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
192 c = inb(via_base + 0x02) | (inb(via_base + 0x0a) << 8);
193 via_print("Simplex only: %10s%20s",
194 (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
196 via_print("Cable Type: %10s%20s",
197 (via_80w & 1) ? "80w" : "40w", (via_80w & 2) ? "80w" : "40w");
199 via_print("-------------------drive0----drive1"
200 "----drive2----drive3-----");
202 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
203 pci_read_config_dword(dev, VIA_DRIVE_TIMING, &v);
204 pci_read_config_word(dev, VIA_8BIT_TIMING, &w);
206 if (via_config->flags & VIA_UDMA)
207 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
210 for (i = 0; i < 4; i++) {
212 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
213 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
214 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
215 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
216 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
217 udma[i] = ((u >> ((3 - i) << 3)) & 0x7) + 2;
218 umul[i] = ((u >> (((3 - i) & 2) << 3)) & 0x8) ? 1 : 2;
219 uen[i] = ((u >> ((3 - i) << 3)) & 0x20);
220 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
222 speed[i] = 2 * via_clock / (active[i] + recover[i]);
223 cycle[i] = 1000000 * (active[i] + recover[i]) / via_clock;
225 if (!uen[i] || !den[i])
228 switch (via_config->flags & VIA_UDMA) {
231 speed[i] = 2 * via_clock / udma[i];
232 cycle[i] = 1000000 * udma[i] / via_clock;
236 speed[i] = 4 * via_clock / (udma[i] * umul[i]);
237 cycle[i] = 500000 * (udma[i] * umul[i]) / via_clock;
241 speed[i] = 6 * via_clock / udma[i];
242 cycle[i] = 333333 * udma[i] / via_clock;
246 speed[i] = 8 * via_clock / udma[i];
247 cycle[i] = 250000 * udma[i] / via_clock;
252 via_print_drive("Transfer Mode: ", "%10s",
253 den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
255 via_print_drive("Address Setup: ", "%8dns",
256 1000000 * setup[i] / via_clock);
257 via_print_drive("Cmd Active: ", "%8dns",
258 1000000 * active8b[i] / via_clock);
259 via_print_drive("Cmd Recovery: ", "%8dns",
260 1000000 * recover8b[i] / via_clock);
261 via_print_drive("Data Active: ", "%8dns",
262 1000000 * active[i] / via_clock);
263 via_print_drive("Data Recovery: ", "%8dns",
264 1000000 * recover[i] / via_clock);
265 via_print_drive("Cycle Time: ", "%8dns",
267 via_print_drive("Transfer Rate: ", "%4d.%dMB/s",
268 speed[i] / 1000, speed[i] / 100 % 10);
270 /* hoping it is less than 4K... */
271 len = (p - buffer) - offset;
272 *addr = buffer + offset;
274 return len > count ? count : len;
277 #endif /* DISPLAY_VIA_TIMINGS && CONFIG_PROC_FS */
280 * via_set_speed - write timing registers
283 * @timing: IDE timing data to use
285 * via_set_speed writes timing values to the chipset registers
288 static void via_set_speed(struct pci_dev *dev, u8 dn, struct ide_timing *timing)
292 if (~via_config->flags & VIA_BAD_AST) {
293 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
294 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
295 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
298 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
299 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
301 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
302 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
304 switch (via_config->flags & VIA_UDMA) {
305 case VIA_UDMA_33: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
306 case VIA_UDMA_66: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
307 case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
308 case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
312 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
316 * via_set_drive - configure transfer mode
317 * @drive: Drive to set up
318 * @speed: desired speed
320 * via_set_drive() computes timing values configures the drive and
321 * the chipset to a desired transfer mode. It also can be called
325 static int via_set_drive(ide_drive_t *drive, u8 speed)
327 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
328 struct ide_timing t, p;
331 if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
332 if (ide_config_drive_speed(drive, speed))
333 printk(KERN_WARNING "ide%d: Drive %d didn't "
334 "accept speed setting. Oh, well.\n",
335 drive->dn >> 1, drive->dn & 1);
337 T = 1000000000 / via_clock;
339 switch (via_config->flags & VIA_UDMA) {
340 case VIA_UDMA_33: UT = T; break;
341 case VIA_UDMA_66: UT = T/2; break;
342 case VIA_UDMA_100: UT = T/3; break;
343 case VIA_UDMA_133: UT = T/4; break;
347 ide_timing_compute(drive, speed, &t, T, UT);
350 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
351 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
354 via_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
356 if (!drive->init_speed)
357 drive->init_speed = speed;
358 drive->current_speed = speed;
364 * via82cxxx_tune_drive - PIO setup
365 * @drive: drive to set up
366 * @pio: mode to use (255 for 'best possible')
368 * A callback from the upper layers for PIO-only tuning.
371 static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
375 ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
379 via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
383 * via82cxxx_ide_dma_check - set up for DMA if possible
384 * @drive: IDE drive to set up
386 * Set up the drive for the highest supported speed considering the
387 * driver, controller and cable
390 static int via82cxxx_ide_dma_check (ide_drive_t *drive)
392 u16 w80 = HWIF(drive)->udma_four;
394 u16 speed = ide_find_best_mode(drive,
395 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
396 (via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
397 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
398 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) |
399 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));
401 via_set_drive(drive, speed);
403 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
404 return HWIF(drive)->ide_dma_on(drive);
405 return HWIF(drive)->ide_dma_off_quietly(drive);
409 * init_chipset_via82cxxx - initialization handler
411 * @name: Name of interface
413 * The initialization callback. Here we determine the IDE chip type
414 * and initialize its drive independent registers.
417 static unsigned int __init init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
419 struct pci_dev *isa = NULL;
425 * Find the ISA bridge to see how good the IDE is.
428 for (via_config = via_isa_bridges; via_config->id; via_config++)
429 if ((isa = pci_find_device(PCI_VENDOR_ID_VIA +
430 !!(via_config->flags & VIA_BAD_ID),
431 via_config->id, NULL))) {
433 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
434 if (t >= via_config->rev_min &&
435 t <= via_config->rev_max)
439 if (!via_config->id) {
440 printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
445 * Check 80-wire cable presence and setup Clk66.
448 switch (via_config->flags & VIA_UDMA) {
452 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
453 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
454 for (i = 24; i >= 0; i -= 8)
455 if (((u >> (i & 16)) & 8) &&
457 (((u >> i) & 7) < 2)) {
462 via_80w |= (1 << (1 - (i >> 4)));
467 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
468 for (i = 24; i >= 0; i -= 8)
469 if (((u >> i) & 0x10) ||
470 (((u >> i) & 0x20) &&
471 (((u >> i) & 7) < 4))) {
472 /* BIOS 80-wire bit or
473 * UDMA w/ < 60ns/cycle
475 via_80w |= (1 << (1 - (i >> 4)));
480 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
481 for (i = 24; i >= 0; i -= 8)
482 if (((u >> i) & 0x10) ||
483 (((u >> i) & 0x20) &&
484 (((u >> i) & 7) < 6))) {
485 /* BIOS 80-wire bit or
486 * UDMA w/ < 60ns/cycle
488 via_80w |= (1 << (1 - (i >> 4)));
495 if (via_config->flags & VIA_BAD_CLK66) {
496 /* Would cause trouble on 596a and 686 */
497 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
498 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
502 * Check whether interfaces are enabled.
505 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
508 * Set up FIFO sizes and thresholds.
511 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
513 /* Disable PREQ# till DDACK# */
514 if (via_config->flags & VIA_BAD_PREQ) {
515 /* Would crash on 586b rev 41 */
519 /* Fix FIFO split between channels */
520 if (via_config->flags & VIA_SET_FIFO) {
523 case 2: t |= 0x00; break; /* 16 on primary */
524 case 1: t |= 0x60; break; /* 16 on secondary */
525 case 3: t |= 0x20; break; /* 8 pri 8 sec */
529 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
532 * Determine system bus clock.
535 via_clock = system_bus_clock() * 1000;
538 case 33000: via_clock = 33333; break;
539 case 37000: via_clock = 37500; break;
540 case 41000: via_clock = 41666; break;
543 if (via_clock < 20000 || via_clock > 50000) {
544 printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
545 "impossible (%d), using 33 MHz instead.\n", via_clock);
546 printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
547 "to assume 80-wire cable.\n");
552 * Print the boot message.
555 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
556 printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
557 "controller on pci%s\n",
559 via_dma[via_config->flags & VIA_UDMA],
563 * Setup /proc/ide/via entry.
566 #if defined(DISPLAY_VIA_TIMINGS) && defined(CONFIG_PROC_FS)
568 via_base = pci_resource_start(dev, 4);
571 ide_pci_create_host_proc("via", via_get_info);
574 #endif /* DISPLAY_VIA_TIMINGS && CONFIG_PROC_FS */
578 static void __init init_hwif_via82cxxx(ide_hwif_t *hwif)
584 hwif->tuneproc = &via82cxxx_tune_drive;
585 hwif->speedproc = &via_set_drive;
587 for (i = 0; i < 2; i++) {
588 hwif->drives[i].io_32bit = 1;
589 hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
590 hwif->drives[i].autotune = 1;
591 hwif->drives[i].dn = hwif->channel * 2 + i;
598 hwif->ultra_mask = 0x7f;
599 hwif->mwdma_mask = 0x07;
600 hwif->swdma_mask = 0x07;
602 if (!hwif->udma_four)
603 hwif->udma_four = (via_80w >> hwif->channel) & 1;
604 hwif->ide_dma_check = &via82cxxx_ide_dma_check;
607 hwif->drives[0].autodma = hwif->autodma;
608 hwif->drives[1].autodma = hwif->autodma;
611 static ide_pci_device_t via82cxxx_chipset __devinitdata = {
613 .init_chipset = init_chipset_via82cxxx,
614 .init_hwif = init_hwif_via82cxxx,
616 .autodma = NOAUTODMA,
617 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
618 .bootable = ON_BOARD,
621 static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
623 ide_setup_pci_device(dev, &via82cxxx_chipset);
627 static struct pci_device_id via_pci_tbl[] = {
628 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
629 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
632 MODULE_DEVICE_TABLE(pci, via_pci_tbl);
634 static struct pci_driver driver = {
636 .id_table = via_pci_tbl,
637 .probe = via_init_one,
640 static int via_ide_init(void)
642 return ide_pci_register_driver(&driver);
645 module_init(via_ide_init);
647 MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
648 MODULE_DESCRIPTION("PCI driver module for VIA IDE");
649 MODULE_LICENSE("GPL");