4 * CSR implementation, iso/bus manager implementation.
6 * Copyright (C) 1999 Andreas E. Bombe
7 * 2002 Manfred Weihs <weihs@ict.tuwien.ac.at>
9 * This code is licensed under the GPL. See the file COPYING in the root
10 * directory of the kernel sources for details.
15 * Manfred Weihs <weihs@ict.tuwien.ac.at>
16 * configuration ROM manipulation
20 #include <linux/string.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/param.h>
24 #include <linux/spinlock.h>
27 #include "ieee1394_types.h"
30 #include "highlevel.h"
32 /* Module Parameters */
33 /* this module parameter can be used to disable mapping of the FCP registers */
36 module_param(fcp, int, 0444);
37 MODULE_PARM_DESC(fcp, "Map FCP registers (default = 1, disable = 0).");
39 static struct csr1212_keyval *node_cap = NULL;
41 static void add_host(struct hpsb_host *host);
42 static void remove_host(struct hpsb_host *host);
43 static void host_reset(struct hpsb_host *host);
44 static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
45 u64 addr, size_t length, u16 fl);
46 static int write_fcp(struct hpsb_host *host, int nodeid, int dest,
47 quadlet_t *data, u64 addr, size_t length, u16 flags);
48 static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf,
49 u64 addr, size_t length, u16 flags);
50 static int write_regs(struct hpsb_host *host, int nodeid, int destid,
51 quadlet_t *data, u64 addr, size_t length, u16 flags);
52 static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,
53 u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl);
54 static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,
55 u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl);
56 static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
57 u64 addr, size_t length, u16 fl);
58 static u64 allocate_addr_range(u64 size, u32 alignment, void *__host);
59 static void release_addr_range(u64 addr, void *__host);
61 static struct hpsb_highlevel csr_highlevel = {
62 .name = "standard registers",
64 .remove_host = remove_host,
65 .host_reset = host_reset,
68 static struct hpsb_address_ops map_ops = {
72 static struct hpsb_address_ops fcp_ops = {
76 static struct hpsb_address_ops reg_ops = {
80 .lock64 = lock64_regs,
83 static struct hpsb_address_ops config_rom_ops = {
84 .read = read_config_rom,
87 struct csr1212_bus_ops csr_bus_ops = {
88 .allocate_addr_range = allocate_addr_range,
89 .release_addr = release_addr_range,
93 static u16 csr_crc16(unsigned *data, int length)
96 int shift, sum, next=0;
98 for (i = length; i; i--) {
99 for (next = check, shift = 28; shift >= 0; shift -= 4 ) {
100 sum = ((next >> 12) ^ (be32_to_cpu(*data) >> shift)) & 0xf;
101 next = (next << 4) ^ (sum << 12) ^ (sum << 5) ^ (sum);
103 check = next & 0xffff;
110 static void host_reset(struct hpsb_host *host)
112 host->csr.state &= 0x300;
114 host->csr.bus_manager_id = 0x3f;
115 host->csr.bandwidth_available = 4915;
116 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */
117 host->csr.channels_available_lo = ~0;
118 host->csr.broadcast_channel = 0x80000000 | 31;
121 if (host->driver->hw_csr_reg) {
122 host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0);
126 host->csr.node_ids = host->node_id << 16;
128 if (!host->is_root) {
129 /* clear cmstr bit */
130 host->csr.state &= ~0x100;
133 host->csr.topology_map[1] =
134 cpu_to_be32(be32_to_cpu(host->csr.topology_map[1]) + 1);
135 host->csr.topology_map[2] = cpu_to_be32(host->node_count << 16
136 | host->selfid_count);
137 host->csr.topology_map[0] =
138 cpu_to_be32((host->selfid_count + 2) << 16
139 | csr_crc16(host->csr.topology_map + 1,
140 host->selfid_count + 2));
142 host->csr.speed_map[1] =
143 cpu_to_be32(be32_to_cpu(host->csr.speed_map[1]) + 1);
144 host->csr.speed_map[0] = cpu_to_be32(0x3f1 << 16
145 | csr_crc16(host->csr.speed_map+1,
150 * HI == seconds (bits 0:2)
151 * LO == fraction units of 1/8000 of a second, as per 1394 (bits 19:31)
153 * Convert to units and then to HZ, for comparison to jiffies.
155 * By default this will end up being 800 units, or 100ms (125usec per
158 * NOTE: The spec says 1/8000, but also says we can compute based on 1/8192
159 * like CSR specifies. Should make our math less complex.
161 static inline void calculate_expire(struct csr_control *csr)
165 /* Take the seconds, and convert to units */
166 units = (unsigned long)(csr->split_timeout_hi & 0x07) << 13;
168 /* Add in the fractional units */
169 units += (unsigned long)(csr->split_timeout_lo >> 19);
171 /* Convert to jiffies */
172 csr->expire = (unsigned long)(units * HZ) >> 13UL;
174 /* Just to keep from rounding low */
177 HPSB_VERBOSE("CSR: setting expire to %lu, HZ=%u", csr->expire, HZ);
181 static void add_host(struct hpsb_host *host)
183 struct csr1212_keyval *root;
184 quadlet_t bus_info[CSR_BUS_INFO_SIZE];
186 hpsb_register_addrspace(&csr_highlevel, host, ®_ops,
188 CSR_REGISTER_BASE + CSR_CONFIG_ROM);
189 hpsb_register_addrspace(&csr_highlevel, host, &config_rom_ops,
190 CSR_REGISTER_BASE + CSR_CONFIG_ROM,
191 CSR_REGISTER_BASE + CSR_CONFIG_ROM_END);
193 hpsb_register_addrspace(&csr_highlevel, host, &fcp_ops,
194 CSR_REGISTER_BASE + CSR_FCP_COMMAND,
195 CSR_REGISTER_BASE + CSR_FCP_END);
197 hpsb_register_addrspace(&csr_highlevel, host, &map_ops,
198 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP,
199 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP_END);
200 hpsb_register_addrspace(&csr_highlevel, host, &map_ops,
201 CSR_REGISTER_BASE + CSR_SPEED_MAP,
202 CSR_REGISTER_BASE + CSR_SPEED_MAP_END);
204 host->csr.lock = SPIN_LOCK_UNLOCKED;
207 host->csr.node_ids = 0;
208 host->csr.split_timeout_hi = 0;
209 host->csr.split_timeout_lo = 800 << 19;
210 calculate_expire(&host->csr);
211 host->csr.cycle_time = 0;
212 host->csr.bus_time = 0;
213 host->csr.bus_manager_id = 0x3f;
214 host->csr.bandwidth_available = 4915;
215 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */
216 host->csr.channels_available_lo = ~0;
217 host->csr.broadcast_channel = 0x80000000 | 31;
220 if (host->driver->hw_csr_reg) {
221 host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0);
225 if (host->csr.max_rec >= 9)
226 host->csr.max_rom = 2;
227 else if (host->csr.max_rec >= 5)
228 host->csr.max_rom = 1;
230 host->csr.max_rom = 0;
232 host->csr.generation = 2;
234 bus_info[1] = __constant_cpu_to_be32(0x31333934);
235 bus_info[2] = cpu_to_be32((1 << CSR_IRMC_SHIFT) |
236 (1 << CSR_CMC_SHIFT) |
237 (1 << CSR_ISC_SHIFT) |
238 (0 << CSR_BMC_SHIFT) |
239 (0 << CSR_PMC_SHIFT) |
240 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
241 (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
242 (host->csr.max_rom << CSR_MAX_ROM_SHIFT) |
243 (host->csr.generation << CSR_GENERATION_SHIFT) |
246 bus_info[3] = cpu_to_be32(host->csr.guid_hi);
247 bus_info[4] = cpu_to_be32(host->csr.guid_lo);
249 /* The hardware copy of the bus info block will be set later when a
250 * bus reset is issued. */
252 csr1212_init_local_csr(host->csr.rom, bus_info, host->csr.max_rom);
254 host->csr.rom->max_rom = host->csr.max_rom;
256 root = host->csr.rom->root_kv;
258 if(csr1212_attach_keyval_to_directory(root, node_cap) != CSR1212_SUCCESS) {
259 HPSB_ERR("Failed to attach Node Capabilities to root directory");
262 host->update_config_rom = 1;
265 static void remove_host(struct hpsb_host *host)
267 quadlet_t bus_info[CSR_BUS_INFO_SIZE];
269 bus_info[1] = __constant_cpu_to_be32(0x31333934);
270 bus_info[2] = cpu_to_be32((0 << CSR_IRMC_SHIFT) |
271 (0 << CSR_CMC_SHIFT) |
272 (0 << CSR_ISC_SHIFT) |
273 (0 << CSR_BMC_SHIFT) |
274 (0 << CSR_PMC_SHIFT) |
275 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
276 (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
277 (0 << CSR_MAX_ROM_SHIFT) |
278 (0 << CSR_GENERATION_SHIFT) |
281 bus_info[3] = cpu_to_be32(host->csr.guid_hi);
282 bus_info[4] = cpu_to_be32(host->csr.guid_lo);
284 csr1212_detach_keyval_from_directory(host->csr.rom->root_kv, node_cap);
286 csr1212_init_local_csr(host->csr.rom, bus_info, 0);
287 host->update_config_rom = 1;
291 int hpsb_update_config_rom(struct hpsb_host *host, const quadlet_t *new_rom,
292 size_t buffersize, unsigned char rom_version)
297 HPSB_NOTICE("hpsb_update_config_rom() is deprecated");
299 spin_lock_irqsave(&host->csr.lock, flags);
300 if (rom_version != host->csr.generation)
302 else if (buffersize > host->csr.rom->cache_head->size)
305 /* Just overwrite the generated ConfigROM image with new data,
306 * it can be regenerated later. */
307 memcpy(host->csr.rom->cache_head->data, new_rom, buffersize);
308 host->csr.rom->cache_head->len = buffersize;
310 if (host->driver->set_hw_config_rom)
311 host->driver->set_hw_config_rom(host, host->csr.rom->bus_info_data);
312 /* Increment the generation number to keep some sort of sync
313 * with the newer ConfigROM manipulation method. */
314 host->csr.generation++;
315 if (host->csr.generation > 0xf || host->csr.generation < 2)
316 host->csr.generation = 2;
319 spin_unlock_irqrestore(&host->csr.lock, flags);
324 /* Read topology / speed maps and configuration ROM */
325 static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
326 u64 addr, size_t length, u16 fl)
329 int csraddr = addr - CSR_REGISTER_BASE;
332 spin_lock_irqsave(&host->csr.lock, flags);
334 if (csraddr < CSR_SPEED_MAP) {
335 src = ((char *)host->csr.topology_map) + csraddr
338 src = ((char *)host->csr.speed_map) + csraddr - CSR_SPEED_MAP;
341 memcpy(buffer, src, length);
342 spin_unlock_irqrestore(&host->csr.lock, flags);
343 return RCODE_COMPLETE;
347 #define out if (--length == 0) break
349 static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf,
350 u64 addr, size_t length, u16 flags)
352 int csraddr = addr - CSR_REGISTER_BASE;
356 if ((csraddr | length) & 0x3)
357 return RCODE_TYPE_ERROR;
362 case CSR_STATE_CLEAR:
363 *(buf++) = cpu_to_be32(host->csr.state);
366 *(buf++) = cpu_to_be32(host->csr.state);
369 *(buf++) = cpu_to_be32(host->csr.node_ids);
372 case CSR_RESET_START:
373 return RCODE_TYPE_ERROR;
375 /* address gap - handled by default below */
377 case CSR_SPLIT_TIMEOUT_HI:
378 *(buf++) = cpu_to_be32(host->csr.split_timeout_hi);
380 case CSR_SPLIT_TIMEOUT_LO:
381 *(buf++) = cpu_to_be32(host->csr.split_timeout_lo);
385 return RCODE_ADDRESS_ERROR;
388 oldcycle = host->csr.cycle_time;
389 host->csr.cycle_time =
390 host->driver->devctl(host, GET_CYCLE_COUNTER, 0);
392 if (oldcycle > host->csr.cycle_time) {
393 /* cycle time wrapped around */
394 host->csr.bus_time += 1 << 7;
396 *(buf++) = cpu_to_be32(host->csr.cycle_time);
399 oldcycle = host->csr.cycle_time;
400 host->csr.cycle_time =
401 host->driver->devctl(host, GET_CYCLE_COUNTER, 0);
403 if (oldcycle > host->csr.cycle_time) {
404 /* cycle time wrapped around */
405 host->csr.bus_time += (1 << 7);
407 *(buf++) = cpu_to_be32(host->csr.bus_time
408 | (host->csr.cycle_time >> 25));
412 return RCODE_ADDRESS_ERROR;
414 case CSR_BUSY_TIMEOUT:
415 /* not yet implemented */
416 return RCODE_ADDRESS_ERROR;
418 case CSR_BUS_MANAGER_ID:
419 if (host->driver->hw_csr_reg)
420 ret = host->driver->hw_csr_reg(host, 0, 0, 0);
422 ret = host->csr.bus_manager_id;
424 *(buf++) = cpu_to_be32(ret);
426 case CSR_BANDWIDTH_AVAILABLE:
427 if (host->driver->hw_csr_reg)
428 ret = host->driver->hw_csr_reg(host, 1, 0, 0);
430 ret = host->csr.bandwidth_available;
432 *(buf++) = cpu_to_be32(ret);
434 case CSR_CHANNELS_AVAILABLE_HI:
435 if (host->driver->hw_csr_reg)
436 ret = host->driver->hw_csr_reg(host, 2, 0, 0);
438 ret = host->csr.channels_available_hi;
440 *(buf++) = cpu_to_be32(ret);
442 case CSR_CHANNELS_AVAILABLE_LO:
443 if (host->driver->hw_csr_reg)
444 ret = host->driver->hw_csr_reg(host, 3, 0, 0);
446 ret = host->csr.channels_available_lo;
448 *(buf++) = cpu_to_be32(ret);
451 case CSR_BROADCAST_CHANNEL:
452 *(buf++) = cpu_to_be32(host->csr.broadcast_channel);
455 /* address gap to end - fall through to default */
457 return RCODE_ADDRESS_ERROR;
460 return RCODE_COMPLETE;
463 static int write_regs(struct hpsb_host *host, int nodeid, int destid,
464 quadlet_t *data, u64 addr, size_t length, u16 flags)
466 int csraddr = addr - CSR_REGISTER_BASE;
468 if ((csraddr | length) & 0x3)
469 return RCODE_TYPE_ERROR;
474 case CSR_STATE_CLEAR:
475 /* FIXME FIXME FIXME */
476 printk("doh, someone wants to mess with state clear\n");
479 printk("doh, someone wants to mess with state set\n");
483 host->csr.node_ids &= NODE_MASK << 16;
484 host->csr.node_ids |= be32_to_cpu(*(data++)) & (BUS_MASK << 16);
485 host->node_id = host->csr.node_ids >> 16;
486 host->driver->devctl(host, SET_BUS_ID, host->node_id >> 6);
489 case CSR_RESET_START:
490 /* FIXME - perform command reset */
494 return RCODE_ADDRESS_ERROR;
496 case CSR_SPLIT_TIMEOUT_HI:
497 host->csr.split_timeout_hi =
498 be32_to_cpu(*(data++)) & 0x00000007;
499 calculate_expire(&host->csr);
501 case CSR_SPLIT_TIMEOUT_LO:
502 host->csr.split_timeout_lo =
503 be32_to_cpu(*(data++)) & 0xfff80000;
504 calculate_expire(&host->csr);
508 return RCODE_ADDRESS_ERROR;
511 /* should only be set by cycle start packet, automatically */
512 host->csr.cycle_time = be32_to_cpu(*data);
513 host->driver->devctl(host, SET_CYCLE_COUNTER,
514 be32_to_cpu(*(data++)));
517 host->csr.bus_time = be32_to_cpu(*(data++)) & 0xffffff80;
521 return RCODE_ADDRESS_ERROR;
523 case CSR_BUSY_TIMEOUT:
524 /* not yet implemented */
525 return RCODE_ADDRESS_ERROR;
527 case CSR_BUS_MANAGER_ID:
528 case CSR_BANDWIDTH_AVAILABLE:
529 case CSR_CHANNELS_AVAILABLE_HI:
530 case CSR_CHANNELS_AVAILABLE_LO:
531 /* these are not writable, only lockable */
532 return RCODE_TYPE_ERROR;
534 case CSR_BROADCAST_CHANNEL:
535 /* only the valid bit can be written */
536 host->csr.broadcast_channel = (host->csr.broadcast_channel & ~0x40000000)
537 | (be32_to_cpu(*data) & 0x40000000);
540 /* address gap to end - fall through */
542 return RCODE_ADDRESS_ERROR;
545 return RCODE_COMPLETE;
551 static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,
552 u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl)
554 int csraddr = addr - CSR_REGISTER_BASE;
556 quadlet_t *regptr = NULL;
559 return RCODE_TYPE_ERROR;
561 if (csraddr < CSR_BUS_MANAGER_ID || csraddr > CSR_CHANNELS_AVAILABLE_LO
562 || extcode != EXTCODE_COMPARE_SWAP)
563 goto unsupported_lockreq;
565 data = be32_to_cpu(data);
566 arg = be32_to_cpu(arg);
568 /* Is somebody releasing the broadcast_channel on us? */
569 if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x1)) {
570 /* Note: this is may not be the right way to handle
571 * the problem, so we should look into the proper way
573 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "
574 "broadcast channel 31. Ignoring.",
575 NODE_BUS_ARGS(host, nodeid));
577 data &= ~0x1; /* keep broadcast channel allocated */
580 if (host->driver->hw_csr_reg) {
584 hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,
587 *store = cpu_to_be32(old);
588 return RCODE_COMPLETE;
591 spin_lock_irqsave(&host->csr.lock, flags);
594 case CSR_BUS_MANAGER_ID:
595 regptr = &host->csr.bus_manager_id;
596 *store = cpu_to_be32(*regptr);
601 case CSR_BANDWIDTH_AVAILABLE:
607 regptr = &host->csr.bandwidth_available;
610 /* bandwidth available algorithm adapted from IEEE 1394a-2000 spec */
612 *store = cpu_to_be32(old); /* change nothing */
617 /* allocate bandwidth */
618 bandwidth = arg - data;
619 if (old >= bandwidth) {
620 new = old - bandwidth;
621 *store = cpu_to_be32(arg);
624 *store = cpu_to_be32(old);
627 /* deallocate bandwidth */
628 bandwidth = data - arg;
629 if (old + bandwidth < 0x2000) {
630 new = old + bandwidth;
631 *store = cpu_to_be32(arg);
634 *store = cpu_to_be32(old);
640 case CSR_CHANNELS_AVAILABLE_HI:
642 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */
643 quadlet_t affected_channels = arg ^ data;
645 regptr = &host->csr.channels_available_hi;
647 if ((arg & affected_channels) == (*regptr & affected_channels)) {
648 *regptr ^= affected_channels;
649 *store = cpu_to_be32(arg);
651 *store = cpu_to_be32(*regptr);
657 case CSR_CHANNELS_AVAILABLE_LO:
659 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */
660 quadlet_t affected_channels = arg ^ data;
662 regptr = &host->csr.channels_available_lo;
664 if ((arg & affected_channels) == (*regptr & affected_channels)) {
665 *regptr ^= affected_channels;
666 *store = cpu_to_be32(arg);
668 *store = cpu_to_be32(*regptr);
674 spin_unlock_irqrestore(&host->csr.lock, flags);
676 return RCODE_COMPLETE;
680 case CSR_STATE_CLEAR:
682 case CSR_RESET_START:
684 case CSR_SPLIT_TIMEOUT_HI:
685 case CSR_SPLIT_TIMEOUT_LO:
688 case CSR_BROADCAST_CHANNEL:
689 return RCODE_TYPE_ERROR;
691 case CSR_BUSY_TIMEOUT:
692 /* not yet implemented - fall through */
694 return RCODE_ADDRESS_ERROR;
698 static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,
699 u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl)
701 int csraddr = addr - CSR_REGISTER_BASE;
704 data = be64_to_cpu(data);
705 arg = be64_to_cpu(arg);
708 return RCODE_TYPE_ERROR;
710 if (csraddr != CSR_CHANNELS_AVAILABLE
711 || extcode != EXTCODE_COMPARE_SWAP)
712 goto unsupported_lock64req;
714 /* Is somebody releasing the broadcast_channel on us? */
715 if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x100000000ULL)) {
716 /* Note: this is may not be the right way to handle
717 * the problem, so we should look into the proper way
719 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "
720 "broadcast channel 31. Ignoring.",
721 NODE_BUS_ARGS(host, nodeid));
723 data &= ~0x100000000ULL; /* keep broadcast channel allocated */
726 if (host->driver->hw_csr_reg) {
727 quadlet_t data_hi, data_lo;
728 quadlet_t arg_hi, arg_lo;
729 quadlet_t old_hi, old_lo;
731 data_hi = data >> 32;
732 data_lo = data & 0xFFFFFFFF;
734 arg_lo = arg & 0xFFFFFFFF;
736 old_hi = host->driver->hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,
739 old_lo = host->driver->hw_csr_reg(host, ((csraddr + 4) - CSR_BUS_MANAGER_ID) >> 2,
742 *store = cpu_to_be64(((octlet_t)old_hi << 32) | old_lo);
745 octlet_t affected_channels = arg ^ data;
747 spin_lock_irqsave(&host->csr.lock, flags);
749 old = ((octlet_t)host->csr.channels_available_hi << 32) | host->csr.channels_available_lo;
751 if ((arg & affected_channels) == (old & affected_channels)) {
752 host->csr.channels_available_hi ^= (affected_channels >> 32);
753 host->csr.channels_available_lo ^= (affected_channels & 0xffffffff);
754 *store = cpu_to_be64(arg);
756 *store = cpu_to_be64(old);
759 spin_unlock_irqrestore(&host->csr.lock, flags);
762 /* Is somebody erroneously releasing the broadcast_channel on us? */
763 if (host->csr.channels_available_hi & 0x1)
764 host->csr.channels_available_hi &= ~0x1;
766 return RCODE_COMPLETE;
768 unsupported_lock64req:
770 case CSR_STATE_CLEAR:
772 case CSR_RESET_START:
774 case CSR_SPLIT_TIMEOUT_HI:
775 case CSR_SPLIT_TIMEOUT_LO:
778 case CSR_BUS_MANAGER_ID:
779 case CSR_BROADCAST_CHANNEL:
780 case CSR_BUSY_TIMEOUT:
781 case CSR_BANDWIDTH_AVAILABLE:
782 return RCODE_TYPE_ERROR;
785 return RCODE_ADDRESS_ERROR;
789 static int write_fcp(struct hpsb_host *host, int nodeid, int dest,
790 quadlet_t *data, u64 addr, size_t length, u16 flags)
792 int csraddr = addr - CSR_REGISTER_BASE;
795 return RCODE_TYPE_ERROR;
798 case CSR_FCP_COMMAND:
799 highlevel_fcp_request(host, nodeid, 0, (u8 *)data, length);
801 case CSR_FCP_RESPONSE:
802 highlevel_fcp_request(host, nodeid, 1, (u8 *)data, length);
805 return RCODE_TYPE_ERROR;
808 return RCODE_COMPLETE;
811 static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
812 u64 addr, size_t length, u16 fl)
814 u32 offset = addr - CSR1212_REGISTER_SPACE_BASE;
816 if (csr1212_read(host->csr.rom, offset, buffer, length) == CSR1212_SUCCESS)
817 return RCODE_COMPLETE;
819 return RCODE_ADDRESS_ERROR;
822 static u64 allocate_addr_range(u64 size, u32 alignment, void *__host)
824 struct hpsb_host *host = (struct hpsb_host*)__host;
826 return hpsb_allocate_and_register_addrspace(&csr_highlevel,
830 CSR1212_UNITS_SPACE_BASE,
831 CSR1212_UNITS_SPACE_END);
834 static void release_addr_range(u64 addr, void *__host)
836 struct hpsb_host *host = (struct hpsb_host*)__host;
837 hpsb_unregister_addrspace(&csr_highlevel, host, addr);
843 node_cap = csr1212_new_immediate(CSR1212_KV_ID_NODE_CAPABILITIES, 0x0083c0);
845 HPSB_ERR("Failed to allocate memory for Node Capabilties ConfigROM entry!");
849 hpsb_register_highlevel(&csr_highlevel);
854 void cleanup_csr(void)
857 csr1212_release_keyval(node_cap);
858 hpsb_unregister_highlevel(&csr_highlevel);