2 * i8042 keyboard and mouse controller driver for Linux
4 * Copyright (c) 1999-2002 Vojtech Pavlik
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/config.h>
19 #include <linux/reboot.h>
20 #include <linux/init.h>
21 #include <linux/sysdev.h>
23 #include <linux/serio.h>
24 #include <linux/pci.h>
28 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
29 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
30 MODULE_LICENSE("GPL");
32 static unsigned int i8042_noaux;
33 module_param_named(noaux, i8042_noaux, bool, 0);
34 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
36 static unsigned int i8042_nomux;
37 module_param_named(nomux, i8042_nomux, bool, 0);
38 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present.");
40 static unsigned int i8042_unlock;
41 module_param_named(unlock, i8042_unlock, bool, 0);
42 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
44 static unsigned int i8042_reset;
45 module_param_named(reset, i8042_reset, bool, 0);
46 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
48 static unsigned int i8042_direct;
49 module_param_named(direct, i8042_direct, bool, 0);
50 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
52 static unsigned int i8042_dumbkbd;
53 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
54 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
56 __obsolete_setup("i8042_noaux");
57 __obsolete_setup("i8042_nomux");
58 __obsolete_setup("i8042_unlock");
59 __obsolete_setup("i8042_reset");
60 __obsolete_setup("i8042_direct");
61 __obsolete_setup("i8042_dumbkbd");
66 spinlock_t i8042_lock = SPIN_LOCK_UNLOCKED;
70 unsigned char disable;
78 static struct serio i8042_kbd_port;
79 static struct serio i8042_aux_port;
80 static unsigned char i8042_initial_ctr;
81 static unsigned char i8042_ctr;
82 static unsigned char i8042_mux_open;
83 static unsigned char i8042_mux_present;
84 static unsigned char i8042_sysdev_initialized;
85 static struct pm_dev *i8042_pm_dev;
86 struct timer_list i8042_timer;
89 * Shared IRQ's require a device pointer, but this driver doesn't support
92 #define i8042_request_irq_cookie (&i8042_timer)
94 static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs);
97 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
98 * be ready for reading values from it / writing values to it.
101 static int i8042_wait_read(void)
104 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
108 return -(i == I8042_CTL_TIMEOUT);
111 static int i8042_wait_write(void)
114 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
118 return -(i == I8042_CTL_TIMEOUT);
122 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
123 * of the i8042 down the toilet.
126 static int i8042_flush(void)
132 spin_lock_irqsave(&i8042_lock, flags);
134 while ((i8042_read_status() & I8042_STR_OBF) && (i++ < I8042_BUFFER_SIZE)) {
136 data = i8042_read_data();
137 dbg("%02x <- i8042 (flush, %s)", data,
138 i8042_read_status() & I8042_STR_AUXDATA ? "aux" : "kbd");
141 spin_unlock_irqrestore(&i8042_lock, flags);
147 * i8042_command() executes a command on the i8042. It also sends the input
148 * parameter(s) of the commands to it, and receives the output value(s). The
149 * parameters are to be stored in the param array, and the output is placed
150 * into the same array. The number of the parameters and output values is
151 * encoded in bits 8-11 of the command number.
154 static int i8042_command(unsigned char *param, int command)
157 int retval = 0, i = 0;
159 spin_lock_irqsave(&i8042_lock, flags);
161 retval = i8042_wait_write();
163 dbg("%02x -> i8042 (command)", command & 0xff);
164 i8042_write_command(command & 0xff);
168 for (i = 0; i < ((command >> 12) & 0xf); i++) {
169 if ((retval = i8042_wait_write())) break;
170 dbg("%02x -> i8042 (parameter)", param[i]);
171 i8042_write_data(param[i]);
175 for (i = 0; i < ((command >> 8) & 0xf); i++) {
176 if ((retval = i8042_wait_read())) break;
177 if (i8042_read_status() & I8042_STR_AUXDATA)
178 param[i] = ~i8042_read_data();
180 param[i] = i8042_read_data();
181 dbg("%02x <- i8042 (return)", param[i]);
184 spin_unlock_irqrestore(&i8042_lock, flags);
187 dbg(" -- i8042 (timeout)");
193 * i8042_kbd_write() sends a byte out through the keyboard interface.
196 static int i8042_kbd_write(struct serio *port, unsigned char c)
201 spin_lock_irqsave(&i8042_lock, flags);
203 if(!(retval = i8042_wait_write())) {
204 dbg("%02x -> i8042 (kbd-data)", c);
208 spin_unlock_irqrestore(&i8042_lock, flags);
214 * i8042_aux_write() sends a byte out through the aux interface.
217 static int i8042_aux_write(struct serio *port, unsigned char c)
219 struct i8042_values *values = port->driver;
226 if (values->mux == -1)
227 retval = i8042_command(&c, I8042_CMD_AUX_SEND);
229 retval = i8042_command(&c, I8042_CMD_MUX_SEND + values->mux);
232 * Make sure the interrupt happens and the character is received even
233 * in the case the IRQ isn't wired, so that we can receive further
237 i8042_interrupt(0, NULL, NULL);
242 * i8042_activate_port() enables port on a chip.
245 static int i8042_activate_port(struct serio *port)
247 struct i8042_values *values = port->driver;
252 * Enable port again here because it is disabled if we are
253 * resuming (normally it is enabled already).
255 i8042_ctr &= ~values->disable;
257 i8042_ctr |= values->irqen;
259 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
260 i8042_ctr &= ~values->irqen;
269 * i8042_open() is called when a port is open by the higher layer.
270 * It allocates the interrupt and calls i8042_enable_port.
273 static int i8042_open(struct serio *port)
275 struct i8042_values *values = port->driver;
277 if (values->mux != -1)
278 if (i8042_mux_open++)
281 if (request_irq(values->irq, i8042_interrupt,
282 SA_SHIRQ, "i8042", i8042_request_irq_cookie)) {
283 printk(KERN_ERR "i8042.c: Can't get irq %d for %s, unregistering the port.\n", values->irq, values->name);
287 if (i8042_activate_port(port)) {
288 printk(KERN_ERR "i8042.c: Can't activate %s, unregistering the port\n", values->name);
292 i8042_interrupt(0, NULL, NULL);
297 free_irq(values->irq, i8042_request_irq_cookie);
301 serio_unregister_port_delayed(port);
307 * i8042_close() frees the interrupt, so that it can possibly be used
308 * by another driver. We never know - if the user doesn't have a mouse,
309 * the BIOS could have used the AUX interrupt for PCI.
312 static void i8042_close(struct serio *port)
314 struct i8042_values *values = port->driver;
316 if (values->mux != -1)
317 if (--i8042_mux_open)
320 i8042_ctr &= ~values->irqen;
322 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
323 printk(KERN_ERR "i8042.c: Can't write CTR while closing %s.\n", values->name);
327 free_irq(values->irq, i8042_request_irq_cookie);
333 * Structures for registering the devices in the serio.c module.
336 static struct i8042_values i8042_kbd_values = {
337 .irqen = I8042_CTR_KBDINT,
338 .disable = I8042_CTR_KBDDIS,
343 static struct serio i8042_kbd_port =
345 .type = SERIO_8042_XL,
346 .write = i8042_kbd_write,
348 .close = i8042_close,
349 .driver = &i8042_kbd_values,
350 .name = "i8042 Kbd Port",
351 .phys = I8042_KBD_PHYS_DESC,
354 static struct i8042_values i8042_aux_values = {
355 .irqen = I8042_CTR_AUXINT,
356 .disable = I8042_CTR_AUXDIS,
361 static struct serio i8042_aux_port =
364 .write = i8042_aux_write,
366 .close = i8042_close,
367 .driver = &i8042_aux_values,
368 .name = "i8042 Aux Port",
369 .phys = I8042_AUX_PHYS_DESC,
372 static struct i8042_values i8042_mux_values[4];
373 static struct serio i8042_mux_port[4];
374 static char i8042_mux_names[4][32];
375 static char i8042_mux_short[4][16];
376 static char i8042_mux_phys[4][32];
379 * i8042_interrupt() is the most important function in this driver -
380 * it handles the interrupts from the i8042, and sends incoming bytes
381 * to the upper layers.
384 static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs)
387 unsigned char str, data = 0;
391 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
393 spin_lock_irqsave(&i8042_lock, flags);
394 str = i8042_read_status();
395 if (str & I8042_STR_OBF)
396 data = i8042_read_data();
397 spin_unlock_irqrestore(&i8042_lock, flags);
399 if (~str & I8042_STR_OBF) {
400 if (irq) dbg("Interrupt %d, without any data", irq);
405 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
406 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
408 if (i8042_mux_values[0].exists && (str & I8042_STR_AUXDATA)) {
410 if (str & I8042_STR_MUXERR) {
413 case 0xfe: dfl = SERIO_TIMEOUT; break;
414 case 0xff: dfl = SERIO_PARITY; break;
419 dbg("%02x <- i8042 (interrupt, aux%d, %d%s%s)",
420 data, (str >> 6), irq,
421 dfl & SERIO_PARITY ? ", bad parity" : "",
422 dfl & SERIO_TIMEOUT ? ", timeout" : "");
424 serio_interrupt(i8042_mux_port + ((str >> 6) & 3), data, dfl, regs);
429 dbg("%02x <- i8042 (interrupt, %s, %d%s%s)",
430 data, (str & I8042_STR_AUXDATA) ? "aux" : "kbd", irq,
431 dfl & SERIO_PARITY ? ", bad parity" : "",
432 dfl & SERIO_TIMEOUT ? ", timeout" : "");
434 if (i8042_aux_values.exists && (str & I8042_STR_AUXDATA)) {
435 serio_interrupt(&i8042_aux_port, data, dfl, regs);
439 if (!i8042_kbd_values.exists)
442 serio_interrupt(&i8042_kbd_port, data, dfl, regs);
447 return IRQ_RETVAL(ret);
451 * i8042_enable_mux_mode checks whether the controller has an active
452 * multiplexor and puts the chip into Multiplexed (as opposed to
456 static int i8042_enable_mux_mode(struct i8042_values *values, unsigned char *mux_version)
461 * Get rid of bytes in the queue.
467 * Internal loopback test - send three bytes, they should come back from the
468 * mouse interface, the last should be version. Note that we negate mouseport
469 * command responses for the i8042_check_aux() routine.
473 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0x0f)
476 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xa9)
479 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == 0x5b) {
482 * Do another loop test with the 0x5a value. Doing anything else upsets
483 * Profusion/ServerWorks OSB4 chipsets.
487 i8042_command(¶m, I8042_CMD_AUX_LOOP);
492 *mux_version = ~param;
499 * i8042_enable_mux_ports enables 4 individual AUX ports after
500 * the controller has been switched into Multiplexed mode
503 static int i8042_enable_mux_ports(struct i8042_values *values)
508 * Disable all muxed ports by disabling AUX.
511 i8042_ctr |= I8042_CTR_AUXDIS;
512 i8042_ctr &= ~I8042_CTR_AUXINT;
514 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
515 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n");
520 * Enable all muxed ports.
523 for (i = 0; i < 4; i++) {
524 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
525 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
533 * i8042_check_mux() checks whether the controller supports the PS/2 Active
534 * Multiplexing specification by Synaptics, Phoenix, Insyde and
538 static int __init i8042_check_mux(struct i8042_values *values)
540 unsigned char mux_version;
542 if (i8042_enable_mux_mode(values, &mux_version))
545 /* Workaround for broken chips which seem to support MUX, but in reality don't. */
546 /* They all report version 10.12 */
547 if (mux_version == 0xAC)
550 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
551 (mux_version >> 4) & 0xf, mux_version & 0xf);
553 if (i8042_enable_mux_ports(values))
556 i8042_mux_present = 1;
562 * i8042_check_aux() applies as much paranoia as it can at detecting
563 * the presence of an AUX interface.
566 static int __init i8042_check_aux(struct i8042_values *values)
569 static int i8042_check_aux_cookie;
572 * Check if AUX irq is available. If it isn't, then there is no point
573 * in trying to detect AUX presence.
576 if (request_irq(values->irq, i8042_interrupt, SA_SHIRQ,
577 "i8042", &i8042_check_aux_cookie))
579 free_irq(values->irq, &i8042_check_aux_cookie);
582 * Get rid of bytes in the queue.
588 * Internal loopback test - filters out AT-type i8042's. Unfortunately
589 * SiS screwed up and their 5597 doesn't support the LOOP command even
590 * though it has an AUX port.
594 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xa5) {
597 * External connection test - filters out AT-soldered PS/2 i8042's
598 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
599 * 0xfa - no error on some notebooks which ignore the spec
600 * Because it's common for chipsets to return error on perfectly functioning
601 * AUX ports, we test for this only when the LOOP command failed.
604 if (i8042_command(¶m, I8042_CMD_AUX_TEST)
605 || (param && param != 0xfa && param != 0xff))
610 * Bit assignment test - filters out PS/2 i8042's in AT mode
613 if (i8042_command(¶m, I8042_CMD_AUX_DISABLE))
615 if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS)) {
616 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
617 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n");
620 if (i8042_command(¶m, I8042_CMD_AUX_ENABLE))
622 if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS))
626 * Disable the interface.
629 i8042_ctr |= I8042_CTR_AUXDIS;
630 i8042_ctr &= ~I8042_CTR_AUXINT;
632 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
640 * i8042_port_register() marks the device as existing,
641 * registers it, and reports to the user.
644 static int __init i8042_port_register(struct i8042_values *values, struct serio *port)
648 i8042_ctr &= ~values->disable;
650 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
651 printk(KERN_WARNING "i8042.c: Can't write CTR while registering.\n");
656 printk(KERN_INFO "serio: i8042 %s port at %#lx,%#lx irq %d\n",
658 (unsigned long) I8042_DATA_REG,
659 (unsigned long) I8042_COMMAND_REG,
662 serio_register_port(port);
668 static void i8042_timer_func(unsigned long data)
670 i8042_interrupt(0, NULL, NULL);
674 static int i8042_spank_usb(void)
676 struct pci_dev *usb = NULL;
683 while((usb = pci_find_class((PCI_CLASS_SERIAL_USB << 8), usb)) != NULL)
685 /* UHCI controller not in legacy ? */
687 pci_read_config_word(usb, 0xC0, &word);
691 /* Check it is enabled. If the port is active in legacy mode
692 then this will be mapped already */
694 for(i = 0; i < PCI_ROM_RESOURCE; i++)
696 if (!(pci_resource_flags (usb, i) & IORESOURCE_IO))
699 if(i == PCI_ROM_RESOURCE)
706 addr = pci_resource_start(usb, i);
707 len = pci_resource_len (usb, i);
710 * Check its configured and not in use
714 if (request_region(addr, len, "usb whackamole"))
718 * Kick the problem controller out of legacy mode
719 * so things like the E750x don't break
722 outw(0, addr + 4); /* IRQ Mask */
723 outw(4, addr); /* Reset */
728 /* Now take if off the BIOS */
729 pci_write_config_word(usb, 0xC0, 0x2000);
730 release_region(addr, len);
738 * i8042_controller init initializes the i8042 controller, and,
739 * most importantly, sets it into non-xlated mode if that's
743 static int i8042_controller_init(void)
748 * Test the i8042. We need to know if it thinks it's working correctly
749 * before doing anything else.
758 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
759 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
763 if (param != I8042_RET_CTL_TEST) {
764 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
765 param, I8042_RET_CTL_TEST);
771 * Save the CTR for restoral on unload / reboot.
774 while(i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
775 if(tries > 3 || !i8042_spank_usb())
777 printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n");
780 printk(KERN_WARNING "i8042.c: Can't read CTR, disabling USB legacy and retrying.\n");
785 i8042_initial_ctr = i8042_ctr;
788 * Disable the keyboard interface and interrupt.
791 i8042_ctr |= I8042_CTR_KBDDIS;
792 i8042_ctr &= ~I8042_CTR_KBDINT;
798 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
800 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
802 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
806 * If the chip is configured into nontranslated mode by the BIOS, don't
807 * bother enabling translating and be happy.
810 if (~i8042_ctr & I8042_CTR_XLATE)
814 * Set nontranslated mode for the kbd interface if requested by an option.
815 * After this the kbd interface becomes a simple serial in/out, like the aux
816 * interface is. We don't do this by default, since it can confuse notebook
821 i8042_ctr &= ~I8042_CTR_XLATE;
822 i8042_kbd_port.type = SERIO_8042;
829 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
830 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
839 * Reset the controller.
841 void i8042_controller_reset(void)
846 if (i8042_command(¶m, I8042_CMD_CTL_TEST))
847 printk(KERN_ERR "i8042.c: i8042 controller reset timeout.\n");
851 * Restore the original control register setting.
854 i8042_ctr = i8042_initial_ctr;
856 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
857 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
862 * Here we try to reset everything back to a state in which the BIOS will be
863 * able to talk to the hardware when rebooting.
866 void i8042_controller_cleanup(void)
873 * Reset anything that is connected to the ports.
876 if (i8042_kbd_values.exists)
877 serio_cleanup(&i8042_kbd_port);
879 if (i8042_aux_values.exists)
880 serio_cleanup(&i8042_aux_port);
882 for (i = 0; i < 4; i++)
883 if (i8042_mux_values[i].exists)
884 serio_cleanup(i8042_mux_port + i);
886 i8042_controller_reset();
891 * Here we try to restore the original BIOS settings
894 static int i8042_controller_suspend(void)
896 del_timer_sync(&i8042_timer);
897 i8042_controller_reset();
904 * Here we try to reset everything back to a state in which suspended
907 static int i8042_controller_resume(void)
911 if (i8042_controller_init()) {
912 printk(KERN_ERR "i8042: resume failed\n");
916 if (i8042_mux_present)
917 if (i8042_enable_mux_mode(&i8042_aux_values, NULL) ||
918 i8042_enable_mux_ports(&i8042_aux_values)) {
919 printk(KERN_WARNING "i8042: failed to resume active multiplexor, mouse won't work.\n");
923 * Reconnect anything that was connected to the ports.
926 if (i8042_kbd_values.exists && i8042_activate_port(&i8042_kbd_port) == 0)
927 serio_reconnect(&i8042_kbd_port);
929 if (i8042_aux_values.exists && i8042_activate_port(&i8042_aux_port) == 0)
930 serio_reconnect(&i8042_aux_port);
932 for (i = 0; i < 4; i++)
933 if (i8042_mux_values[i].exists && i8042_activate_port(i8042_mux_port + i) == 0)
934 serio_reconnect(i8042_mux_port + i);
936 * Restart timer (for polling "stuck" data)
938 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
945 * We need to reset the 8042 back to original mode on system shutdown,
946 * because otherwise BIOSes will be confused.
949 static int i8042_notify_sys(struct notifier_block *this, unsigned long code,
952 if (code == SYS_DOWN || code == SYS_HALT)
953 i8042_controller_cleanup();
957 static struct notifier_block i8042_notifier=
965 * Suspend/resume handlers for the new PM scheme (driver model)
967 static int i8042_suspend(struct sys_device *dev, u32 state)
969 return i8042_controller_suspend();
972 static int i8042_resume(struct sys_device *dev)
974 return i8042_controller_resume();
977 static struct sysdev_class kbc_sysclass = {
978 set_kset_name("i8042"),
979 .suspend = i8042_suspend,
980 .resume = i8042_resume,
983 static struct sys_device device_i8042 = {
985 .cls = &kbc_sysclass,
989 * Suspend/resume handler for the old PM scheme (APM)
991 static int i8042_pm_callback(struct pm_dev *dev, pm_request_t request, void *dummy)
995 return i8042_controller_suspend();
998 return i8042_controller_resume();
1004 static void __init i8042_init_mux_values(struct i8042_values *values, struct serio *port, int index)
1006 memcpy(port, &i8042_aux_port, sizeof(struct serio));
1007 memcpy(values, &i8042_aux_values, sizeof(struct i8042_values));
1008 sprintf(i8042_mux_names[index], "i8042 Aux-%d Port", index);
1009 sprintf(i8042_mux_phys[index], I8042_MUX_PHYS_DESC, index + 1);
1010 sprintf(i8042_mux_short[index], "AUX%d", index);
1011 port->name = i8042_mux_names[index];
1012 port->phys = i8042_mux_phys[index];
1013 port->driver = values;
1014 values->name = i8042_mux_short[index];
1015 values->mux = index;
1018 int __init i8042_init(void)
1024 init_timer(&i8042_timer);
1025 i8042_timer.function = i8042_timer_func;
1027 if (i8042_platform_init())
1030 i8042_aux_values.irq = I8042_AUX_IRQ;
1031 i8042_kbd_values.irq = I8042_KBD_IRQ;
1033 if (i8042_controller_init())
1037 i8042_kbd_port.write = NULL;
1039 if (!i8042_noaux && !i8042_check_aux(&i8042_aux_values)) {
1040 if (!i8042_nomux && !i8042_check_mux(&i8042_aux_values))
1041 for (i = 0; i < 4; i++) {
1042 i8042_init_mux_values(i8042_mux_values + i, i8042_mux_port + i, i);
1043 i8042_port_register(i8042_mux_values + i, i8042_mux_port + i);
1046 i8042_port_register(&i8042_aux_values, &i8042_aux_port);
1049 i8042_port_register(&i8042_kbd_values, &i8042_kbd_port);
1051 mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD);
1053 if (sysdev_class_register(&kbc_sysclass) == 0) {
1054 if (sysdev_register(&device_i8042) == 0)
1055 i8042_sysdev_initialized = 1;
1057 sysdev_class_unregister(&kbc_sysclass);
1060 i8042_pm_dev = pm_register(PM_SYS_DEV, PM_SYS_UNKNOWN, i8042_pm_callback);
1062 register_reboot_notifier(&i8042_notifier);
1067 void __exit i8042_exit(void)
1071 unregister_reboot_notifier(&i8042_notifier);
1074 pm_unregister(i8042_pm_dev);
1076 if (i8042_sysdev_initialized) {
1077 sysdev_unregister(&device_i8042);
1078 sysdev_class_unregister(&kbc_sysclass);
1081 i8042_controller_cleanup();
1083 if (i8042_kbd_values.exists)
1084 serio_unregister_port(&i8042_kbd_port);
1086 if (i8042_aux_values.exists)
1087 serio_unregister_port(&i8042_aux_port);
1089 for (i = 0; i < 4; i++)
1090 if (i8042_mux_values[i].exists)
1091 serio_unregister_port(i8042_mux_port + i);
1092 del_timer_sync(&i8042_timer);
1094 i8042_platform_exit();
1097 module_init(i8042_init);
1098 module_exit(i8042_exit);