1 /* $Id: hfc_sx.c,v 1.12.2.5 2004/02/11 13:21:33 keil Exp $
3 * level driver for Cologne Chip Designs hfc-s+/sp based cards
5 * Author Werner Cornelius
6 * based on existing driver for CCD HFC PCI cards
7 * Copyright by Werner Cornelius <werner@isdn4linux.de>
9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference.
14 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/isapnp.h>
21 extern const char *CardType[];
23 static const char *hfcsx_revision = "$Revision: 1.12.2.5 $";
25 /***************************************/
26 /* IRQ-table for CCDs demo board */
27 /* IRQs 6,5,10,11,12,15 are supported */
28 /***************************************/
30 /* Teles 16.3c Vendor Id TAG2620, Version 1.0, Vendor version 2.1
32 * Thanks to Uwe Wisniewski
46 static u_char ccd_sp_irqtab[16] = {
47 0,0,0,0,0,2,1,0,0,0,3,4,5,0,0,6
49 #else /* Teles 16.3c */
50 static u_char ccd_sp_irqtab[16] = {
51 0,0,0,7,0,1,0,0,0,2,3,4,5,0,0,6
54 #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
56 #define byteout(addr,val) outb(val,addr)
57 #define bytein(addr) inb(addr)
59 /******************************/
60 /* In/Out access to registers */
61 /******************************/
63 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val)
65 byteout(cs->hw.hfcsx.base+1, regnum);
66 byteout(cs->hw.hfcsx.base, val);
70 Read_hfc(struct IsdnCardState *cs, u_char regnum)
74 byteout(cs->hw.hfcsx.base+1, regnum);
75 ret = bytein(cs->hw.hfcsx.base);
80 /**************************************************/
81 /* select a fifo and remember which one for reuse */
82 /**************************************************/
84 fifo_select(struct IsdnCardState *cs, u_char fifo)
86 if (fifo == cs->hw.hfcsx.last_fifo)
87 return; /* still valid */
89 byteout(cs->hw.hfcsx.base+1, HFCSX_FIF_SEL);
90 byteout(cs->hw.hfcsx.base, fifo);
91 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
93 byteout(cs->hw.hfcsx.base, fifo);
94 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
97 /******************************************/
98 /* reset the specified fifo to defaults. */
99 /* If its a send fifo init needed markers */
100 /******************************************/
102 reset_fifo(struct IsdnCardState *cs, u_char fifo)
104 fifo_select(cs, fifo); /* first select the fifo */
105 byteout(cs->hw.hfcsx.base+1, HFCSX_CIRM);
106 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
108 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
112 /*************************************************************/
113 /* write_fifo writes the skb contents to the desired fifo */
114 /* if no space is available or an error occurs 0 is returned */
115 /* the skb is not released in any way. */
116 /*************************************************************/
118 write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max)
121 int fifo_size, count, z1, z2;
122 u_char f_msk, f1, f2, *src;
124 if (skb->len <= 0) return(0);
125 if (fifo & 1) return(0); /* no write fifo */
127 fifo_select(cs, fifo);
129 fifo_size = D_FIFO_SIZE; /* D-channel */
130 f_msk = MAX_D_FRAMES;
131 if (trans_max) return(0); /* only HDLC */
134 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
135 f_msk = MAX_B_FRAMES;
138 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
139 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
141 /* Check for transparent mode */
143 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
144 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
147 count += fifo_size; /* free bytes */
148 if (count < skb->len+1) return(0); /* no room */
149 count = fifo_size - count; /* bytes still not send */
150 if (count > 2 * trans_max) return(0); /* delay to long */
154 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
155 return(1); /* success */
158 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker;
159 msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES+1));
160 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
161 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
163 count = f1 - f2; /* frame count actually buffered */
165 count += (f_msk + 1); /* if wrap around */
166 if (count > f_msk-1) {
167 if (cs->debug & L1_DEB_ISAC_FIFO)
168 debugl1(cs, "hfcsx_write_fifo %d more as %d frames",fifo,f_msk-1);
172 *(msp + f1) = z1; /* remember marker */
174 if (cs->debug & L1_DEB_ISAC_FIFO)
175 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)",
177 /* now determine free bytes in FIFO buffer */
178 count = *(msp + f2) - z1;
180 count += fifo_size; /* count now contains available bytes */
182 if (cs->debug & L1_DEB_ISAC_FIFO)
183 debugl1(cs, "hfcsx_write_fifo %d count(%ld/%d)",
184 fifo, skb->len, count);
185 if (count < skb->len) {
186 if (cs->debug & L1_DEB_ISAC_FIFO)
187 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo);
191 count = skb->len; /* get frame len */
192 src = skb->data; /* source pointer */
194 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
196 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */
198 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
202 /***************************************************************/
203 /* read_fifo reads data to an skb from the desired fifo */
204 /* if no data is available or an error occurs NULL is returned */
205 /* the skb is not released in any way. */
206 /***************************************************************/
207 static struct sk_buff *
208 read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max)
209 { int fifo_size, count, z1, z2;
210 u_char f_msk, f1, f2, *dst;
213 if (!(fifo & 1)) return(NULL); /* no read fifo */
214 fifo_select(cs, fifo);
216 fifo_size = D_FIFO_SIZE; /* D-channel */
217 f_msk = MAX_D_FRAMES;
218 if (trans_max) return(NULL); /* only hdlc */
221 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
222 f_msk = MAX_B_FRAMES;
225 /* transparent mode */
227 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
228 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
229 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
230 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
231 /* now determine bytes in actual FIFO buffer */
234 count += fifo_size; /* count now contains buffered bytes */
236 if (count > trans_max)
237 count = trans_max; /* limit length */
238 if ((skb = dev_alloc_skb(count))) {
239 dst = skb_put(skb, count);
241 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
244 else return(NULL); /* no memory */
248 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
249 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
251 if (f1 == f2) return(NULL); /* no frame available */
253 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
254 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
255 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
256 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
258 if (cs->debug & L1_DEB_ISAC_FIFO)
259 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)",
260 fifo, f1, f2, z1, z2);
261 /* now determine bytes in actual FIFO buffer */
264 count += fifo_size; /* count now contains buffered bytes */
267 if (cs->debug & L1_DEB_ISAC_FIFO)
268 debugl1(cs, "hfcsx_read_fifo %d count %ld)",
271 if ((count > fifo_size) || (count < 4)) {
272 if (cs->debug & L1_DEB_WARN)
273 debugl1(cs, "hfcsx_read_fifo %d paket inv. len %d ", fifo , count);
275 count--; /* empty fifo */
276 Read_hfc(cs, HFCSX_FIF_DRD);
280 if ((skb = dev_alloc_skb(count - 3))) {
282 dst = skb_put(skb, count);
285 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
287 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */
288 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */
289 if (Read_hfc(cs, HFCSX_FIF_DRD)) {
290 dev_kfree_skb_irq(skb);
291 if (cs->debug & L1_DEB_ISAC_FIFO)
292 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo);
296 printk(KERN_WARNING "HFC-SX: receive out of memory\n");
300 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */
302 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
304 } while (!skb); /* retry in case of crc error */
308 /******************************************/
309 /* free hardware resources used by driver */
310 /******************************************/
312 release_io_hfcsx(struct IsdnCardState *cs)
314 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */
315 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
316 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */
317 set_current_state(TASK_UNINTERRUPTIBLE);
318 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
319 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */
320 del_timer(&cs->hw.hfcsx.timer);
321 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */
322 kfree(cs->hw.hfcsx.extra);
323 cs->hw.hfcsx.extra = NULL;
326 /**********************************************************/
327 /* set_fifo_size determines the size of the RAM and FIFOs */
328 /* returning 0 -> need to reset the chip again. */
329 /**********************************************************/
330 static int set_fifo_size(struct IsdnCardState *cs)
333 if (cs->hw.hfcsx.b_fifo_size) return(1); /* already determined */
335 if ((cs->hw.hfcsx.chip >> 4) == 9) {
336 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K;
340 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K;
341 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */
346 /********************************************************************************/
347 /* function called to reset the HFC SX chip. A complete software reset of chip */
348 /* and fifos is done. */
349 /********************************************************************************/
351 reset_hfcsx(struct IsdnCardState *cs)
353 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */
354 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
356 printk(KERN_INFO "HFC_SX: resetting card\n");
358 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */
360 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */
362 if (Read_hfc(cs, HFCSX_STATUS) & 2)
363 printk(KERN_WARNING "HFC-SX init bit busy\n");
364 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */
365 if (!set_fifo_size(cs)) continue;
369 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */
370 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
372 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */
373 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE;
374 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */
375 cs->hw.hfcsx.bswapped = 0; /* no exchange */
376 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */
377 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER;
378 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
380 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC |
381 HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER;
382 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
384 /* Clear already pending ints */
385 if (Read_hfc(cs, HFCSX_INT_S1));
387 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */
389 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */
390 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */
392 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
393 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
394 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
395 cs->hw.hfcsx.sctrl_r = 0;
396 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
398 /* Init GCI/IOM2 in master mode */
399 /* Slots 0 and 1 are set for B-chan 1 and 2 */
400 /* D- and monitor/CI channel are not enabled */
401 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
402 /* STIO2 is used as data input, B1+B2 from IOM->ST */
403 /* ST B-channel send disabled -> continous 1s */
404 /* The IOM slots are always enabled */
405 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */
406 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
407 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
408 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
409 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
410 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
412 /* Finally enable IRQ output */
413 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE;
414 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
415 if (Read_hfc(cs, HFCSX_INT_S2));
418 /***************************************************/
419 /* Timer function called when kernel timer expires */
420 /***************************************************/
422 hfcsx_Timer(struct IsdnCardState *cs)
424 cs->hw.hfcsx.timer.expires = jiffies + 75;
426 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80);
427 add_timer(&cs->hw.hfcsx.timer);
431 /************************************************/
432 /* select a b-channel entry matching and active */
433 /************************************************/
436 Sel_BCS(struct IsdnCardState *cs, int channel)
438 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
439 return (&cs->bcs[0]);
440 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
441 return (&cs->bcs[1]);
446 /*******************************/
447 /* D-channel receive procedure */
448 /*******************************/
451 receive_dmsg(struct IsdnCardState *cs)
456 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
457 debugl1(cs, "rec_dmsg blocked");
462 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0);
464 skb_queue_tail(&cs->rq, skb);
465 schedule_event(cs, D_RCVBUFREADY);
467 } while (--count && skb);
469 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
473 /**********************************/
474 /* B-channel main receive routine */
475 /**********************************/
477 main_rec_hfcsx(struct BCState *bcs)
479 struct IsdnCardState *cs = bcs->cs;
485 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
486 debugl1(cs, "rec_data %d blocked", bcs->channel);
489 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
490 HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX,
491 (bcs->mode == L1_MODE_TRANS) ?
492 HFCSX_BTRANS_THRESHOLD : 0);
495 skb_queue_tail(&bcs->rqueue, skb);
496 schedule_event(bcs, B_RCVBUFREADY);
499 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
505 /**************************/
506 /* D-channel send routine */
507 /**************************/
509 hfcsx_fill_dfifo(struct IsdnCardState *cs)
513 if (cs->tx_skb->len <= 0)
516 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) {
517 dev_kfree_skb_any(cs->tx_skb);
523 /**************************/
524 /* B-channel send routine */
525 /**************************/
527 hfcsx_fill_fifo(struct BCState *bcs)
529 struct IsdnCardState *cs = bcs->cs;
533 if (bcs->tx_skb->len <= 0)
536 if (write_fifo(cs, bcs->tx_skb,
537 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
538 HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX,
539 (bcs->mode == L1_MODE_TRANS) ?
540 HFCSX_BTRANS_THRESHOLD : 0)) {
542 bcs->tx_cnt -= bcs->tx_skb->len;
543 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
544 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
546 spin_lock_irqsave(&bcs->aclock, flags);
547 bcs->ackcnt += bcs->tx_skb->len;
548 spin_unlock_irqrestore(&bcs->aclock, flags);
549 schedule_event(bcs, B_ACKPENDING);
551 dev_kfree_skb_any(bcs->tx_skb);
553 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
557 /**********************************************/
558 /* D-channel l1 state call for leased NT-mode */
559 /**********************************************/
561 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
563 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
566 case (PH_DATA | REQUEST):
567 case (PH_PULL | REQUEST):
568 case (PH_PULL | INDICATION):
569 st->l1.l1hw(st, pr, arg);
571 case (PH_ACTIVATE | REQUEST):
572 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
574 case (PH_TESTLOOP | REQUEST):
576 debugl1(cs, "PH_TEST_LOOP B1");
578 debugl1(cs, "PH_TEST_LOOP B2");
579 if (!(3 & (long) arg))
580 debugl1(cs, "PH_TEST_LOOP DISABLED");
581 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
585 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
592 /***********************/
593 /* set/reset echo mode */
594 /***********************/
596 hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
599 int i = *(unsigned int *) ic->parm.num;
601 if ((ic->arg == 98) &&
602 (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) {
603 spin_lock_irqsave(&cs->lock, flags);
604 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */
606 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT;
607 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */
609 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */
611 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION);
612 cs->dc.hfcsx.ph_state = 1;
613 cs->hw.hfcsx.nt_mode = 1;
614 cs->hw.hfcsx.nt_timer = 0;
615 spin_unlock_irqrestore(&cs->lock, flags);
616 cs->stlist->l2.l2l1 = dch_nt_l2l1;
617 debugl1(cs, "NT mode activated");
620 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) ||
621 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12))
626 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */
627 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC;
628 /* reset Channel !!!!! */
631 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */
632 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC;
634 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
635 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
636 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */
637 cs->hw.hfcsx.ctmt &= ~2;
638 spin_lock_irqsave(&cs->lock, flags);
639 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
640 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
641 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
642 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
643 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
644 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
645 spin_unlock_irqrestore(&cs->lock, flags);
649 /*****************************/
650 /* E-channel receive routine */
651 /*****************************/
653 receive_emsg(struct IsdnCardState *cs)
659 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
660 debugl1(cs, "echo_rec_data blocked");
664 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0);
666 if (cs->debug & DEB_DLOG_HEX) {
668 if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) {
674 ptr += QuickHex(ptr, skb->data, skb->len);
678 HiSax_putstatus(cs, NULL, cs->dlog);
680 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);
682 dev_kfree_skb_any(skb);
684 } while (--count && skb);
686 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
691 /*********************/
692 /* Interrupt handler */
693 /*********************/
695 hfcsx_interrupt(int intno, void *dev_id, struct pt_regs *regs)
697 struct IsdnCardState *cs = dev_id;
704 if (!(cs->hw.hfcsx.int_m2 & 0x08))
705 return IRQ_NONE; /* not initialised */
707 spin_lock_irqsave(&cs->lock, flags);
708 if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) {
709 val = Read_hfc(cs, HFCSX_INT_S1);
710 if (cs->debug & L1_DEB_ISAC)
711 debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val);
713 spin_unlock_irqrestore(&cs->lock, flags);
716 if (cs->debug & L1_DEB_ISAC)
717 debugl1(cs, "HFC-SX irq %x %s", val,
718 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
719 "locked" : "unlocked");
720 val &= cs->hw.hfcsx.int_m1;
721 if (val & 0x40) { /* state machine irq */
722 exval = Read_hfc(cs, HFCSX_STATES) & 0xf;
723 if (cs->debug & L1_DEB_ISAC)
724 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state,
726 cs->dc.hfcsx.ph_state = exval;
727 schedule_event(cs, D_L1STATECHANGE);
730 if (val & 0x80) { /* timer irq */
731 if (cs->hw.hfcsx.nt_mode) {
732 if ((--cs->hw.hfcsx.nt_timer) < 0)
733 schedule_event(cs, D_L1STATECHANGE);
736 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
739 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
740 cs->hw.hfcsx.int_s1 |= val;
741 spin_unlock_irqrestore(&cs->lock, flags);
744 if (cs->hw.hfcsx.int_s1 & 0x18) {
746 val = cs->hw.hfcsx.int_s1;
747 cs->hw.hfcsx.int_s1 = exval;
750 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
752 debugl1(cs, "hfcsx spurious 0x08 IRQ");
759 else if (!(bcs = Sel_BCS(cs, 1))) {
761 debugl1(cs, "hfcsx spurious 0x10 IRQ");
766 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
768 debugl1(cs, "hfcsx spurious 0x01 IRQ");
771 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
772 hfcsx_fill_fifo(bcs);
773 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
775 debugl1(cs, "fill_data %d blocked", bcs->channel);
777 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
778 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
779 hfcsx_fill_fifo(bcs);
780 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
782 debugl1(cs, "fill_data %d blocked", bcs->channel);
784 schedule_event(bcs, B_XMTBUFREADY);
790 if (!(bcs = Sel_BCS(cs, 1))) {
792 debugl1(cs, "hfcsx spurious 0x02 IRQ");
795 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
796 hfcsx_fill_fifo(bcs);
797 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
799 debugl1(cs, "fill_data %d blocked", bcs->channel);
801 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
802 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
803 hfcsx_fill_fifo(bcs);
804 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
806 debugl1(cs, "fill_data %d blocked", bcs->channel);
808 schedule_event(bcs, B_XMTBUFREADY);
813 if (val & 0x20) { /* receive dframe */
816 if (val & 0x04) { /* dframe transmitted */
817 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
818 del_timer(&cs->dbusytimer);
819 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
820 schedule_event(cs, D_CLEARBUSY);
822 if (cs->tx_skb->len) {
823 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
824 hfcsx_fill_dfifo(cs);
825 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
827 debugl1(cs, "hfcsx_fill_dfifo irq blocked");
831 dev_kfree_skb_irq(cs->tx_skb);
836 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
838 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
839 hfcsx_fill_dfifo(cs);
840 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
842 debugl1(cs, "hfcsx_fill_dfifo irq blocked");
845 schedule_event(cs, D_XMTBUFREADY);
848 if (cs->hw.hfcsx.int_s1 && count--) {
849 val = cs->hw.hfcsx.int_s1;
850 cs->hw.hfcsx.int_s1 = 0;
851 if (cs->debug & L1_DEB_ISAC)
852 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count);
856 spin_unlock_irqrestore(&cs->lock, flags);
860 /********************************************************************/
861 /* timer callback for D-chan busy resolution. Currently no function */
862 /********************************************************************/
864 hfcsx_dbusy_timer(struct IsdnCardState *cs)
868 /*************************************/
869 /* Layer 1 D-channel hardware access */
870 /*************************************/
872 HFCSX_l1hw(struct PStack *st, int pr, void *arg)
874 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
875 struct sk_buff *skb = arg;
879 case (PH_DATA | REQUEST):
880 if (cs->debug & DEB_DLOG_HEX)
881 LogFrame(cs, skb->data, skb->len);
882 if (cs->debug & DEB_DLOG_VERBOSE)
883 dlogframe(cs, skb, 0);
884 spin_lock_irqsave(&cs->lock, flags);
886 skb_queue_tail(&cs->sq, skb);
887 #ifdef L2FRAME_DEBUG /* psa */
888 if (cs->debug & L1_DEB_LAPD)
889 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
894 #ifdef L2FRAME_DEBUG /* psa */
895 if (cs->debug & L1_DEB_LAPD)
896 Logl2Frame(cs, skb, "PH_DATA", 0);
898 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
899 hfcsx_fill_dfifo(cs);
900 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
902 debugl1(cs, "hfcsx_fill_dfifo blocked");
905 spin_unlock_irqrestore(&cs->lock, flags);
907 case (PH_PULL | INDICATION):
908 spin_lock_irqsave(&cs->lock, flags);
910 if (cs->debug & L1_DEB_WARN)
911 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
912 skb_queue_tail(&cs->sq, skb);
913 spin_unlock_irqrestore(&cs->lock, flags);
916 if (cs->debug & DEB_DLOG_HEX)
917 LogFrame(cs, skb->data, skb->len);
918 if (cs->debug & DEB_DLOG_VERBOSE)
919 dlogframe(cs, skb, 0);
922 #ifdef L2FRAME_DEBUG /* psa */
923 if (cs->debug & L1_DEB_LAPD)
924 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
926 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
927 hfcsx_fill_dfifo(cs);
928 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
930 debugl1(cs, "hfcsx_fill_dfifo blocked");
931 spin_unlock_irqrestore(&cs->lock, flags);
933 case (PH_PULL | REQUEST):
934 #ifdef L2FRAME_DEBUG /* psa */
935 if (cs->debug & L1_DEB_LAPD)
936 debugl1(cs, "-> PH_REQUEST_PULL");
939 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
940 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
942 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
944 case (HW_RESET | REQUEST):
945 spin_lock_irqsave(&cs->lock, flags);
946 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */
948 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */
949 cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
950 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
951 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
952 spin_unlock_irqrestore(&cs->lock, flags);
953 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
955 case (HW_ENABLE | REQUEST):
956 spin_lock_irqsave(&cs->lock, flags);
957 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
958 spin_unlock_irqrestore(&cs->lock, flags);
960 case (HW_DEACTIVATE | REQUEST):
961 spin_lock_irqsave(&cs->lock, flags);
962 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER;
963 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
964 spin_unlock_irqrestore(&cs->lock, flags);
966 case (HW_INFO3 | REQUEST):
967 spin_lock_irqsave(&cs->lock, flags);
968 cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
969 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
970 spin_unlock_irqrestore(&cs->lock, flags);
972 case (HW_TESTLOOP | REQUEST):
973 spin_lock_irqsave(&cs->lock, flags);
976 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */
977 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */
978 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1;
979 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
982 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */
983 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */
984 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08;
985 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
988 spin_unlock_irqrestore(&cs->lock, flags);
989 if (cs->debug & L1_DEB_WARN)
990 debugl1(cs, "hfcsx_l1hw loop invalid %4x", (int) arg);
993 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */
994 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
995 spin_unlock_irqrestore(&cs->lock, flags);
998 if (cs->debug & L1_DEB_WARN)
999 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr);
1004 /***********************************************/
1005 /* called during init setting l1 stack pointer */
1006 /***********************************************/
1008 setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs)
1010 st->l1.l1hw = HFCSX_l1hw;
1013 /**************************************/
1014 /* send B-channel data if not blocked */
1015 /**************************************/
1017 hfcsx_send_data(struct BCState *bcs)
1019 struct IsdnCardState *cs = bcs->cs;
1021 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1022 hfcsx_fill_fifo(bcs);
1023 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1025 debugl1(cs, "send_data %d blocked", bcs->channel);
1028 /***************************************************************/
1029 /* activate/deactivate hardware for selected channels and mode */
1030 /***************************************************************/
1032 mode_hfcsx(struct BCState *bcs, int mode, int bc)
1034 struct IsdnCardState *cs = bcs->cs;
1037 if (cs->debug & L1_DEB_HSCX)
1038 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d",
1039 mode, bc, bcs->channel);
1043 if (cs->chanlimit > 1) {
1044 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1045 cs->hw.hfcsx.sctrl_e &= ~0x80;
1048 if (mode != L1_MODE_NULL) {
1049 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */
1050 cs->hw.hfcsx.sctrl_e |= 0x80;
1052 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1053 cs->hw.hfcsx.sctrl_e &= ~0x80;
1057 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1058 cs->hw.hfcsx.sctrl_e &= ~0x80;
1062 case (L1_MODE_NULL):
1064 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
1065 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
1067 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA;
1068 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA;
1071 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1073 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1076 case (L1_MODE_TRANS):
1078 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1079 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1081 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1082 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1085 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1086 cs->hw.hfcsx.ctmt |= 2;
1087 cs->hw.hfcsx.conn &= ~0x18;
1089 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1090 cs->hw.hfcsx.ctmt |= 1;
1091 cs->hw.hfcsx.conn &= ~0x03;
1094 case (L1_MODE_HDLC):
1096 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1097 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1099 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1100 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1103 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1104 cs->hw.hfcsx.ctmt &= ~2;
1105 cs->hw.hfcsx.conn &= ~0x18;
1107 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1108 cs->hw.hfcsx.ctmt &= ~1;
1109 cs->hw.hfcsx.conn &= ~0x03;
1112 case (L1_MODE_EXTRN):
1114 cs->hw.hfcsx.conn |= 0x10;
1115 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1116 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1117 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1119 cs->hw.hfcsx.conn |= 0x02;
1120 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1121 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1122 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1126 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);
1127 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1128 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
1129 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
1130 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
1131 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1132 if (mode != L1_MODE_EXTRN) {
1133 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX);
1134 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX);
1138 /******************************/
1139 /* Layer2 -> Layer 1 Transfer */
1140 /******************************/
1142 hfcsx_l2l1(struct PStack *st, int pr, void *arg)
1144 struct BCState *bcs = st->l1.bcs;
1145 struct sk_buff *skb = arg;
1149 case (PH_DATA | REQUEST):
1150 spin_lock_irqsave(&bcs->cs->lock, flags);
1152 skb_queue_tail(&bcs->squeue, skb);
1155 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1156 bcs->cs->BC_Send_Data(bcs);
1158 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1160 case (PH_PULL | INDICATION):
1161 spin_lock_irqsave(&bcs->cs->lock, flags);
1163 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1165 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1167 bcs->cs->BC_Send_Data(bcs);
1169 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1171 case (PH_PULL | REQUEST):
1173 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1174 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1176 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1178 case (PH_ACTIVATE | REQUEST):
1179 spin_lock_irqsave(&bcs->cs->lock, flags);
1180 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1181 mode_hfcsx(bcs, st->l1.mode, st->l1.bc);
1182 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1183 l1_msg_b(st, pr, arg);
1185 case (PH_DEACTIVATE | REQUEST):
1186 l1_msg_b(st, pr, arg);
1188 case (PH_DEACTIVATE | CONFIRM):
1189 spin_lock_irqsave(&bcs->cs->lock, flags);
1190 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1191 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1192 mode_hfcsx(bcs, 0, st->l1.bc);
1193 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1194 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1199 /******************************************/
1200 /* deactivate B-channel access and queues */
1201 /******************************************/
1203 close_hfcsx(struct BCState *bcs)
1205 mode_hfcsx(bcs, 0, bcs->channel);
1206 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1207 skb_queue_purge(&bcs->rqueue);
1208 skb_queue_purge(&bcs->squeue);
1210 dev_kfree_skb_any(bcs->tx_skb);
1212 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1217 /*************************************/
1218 /* init B-channel queues and control */
1219 /*************************************/
1221 open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs)
1223 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1224 skb_queue_head_init(&bcs->rqueue);
1225 skb_queue_head_init(&bcs->squeue);
1228 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1234 /*********************************/
1235 /* inits the stack for B-channel */
1236 /*********************************/
1238 setstack_2b(struct PStack *st, struct BCState *bcs)
1240 bcs->channel = st->l1.bc;
1241 if (open_hfcsxstate(st->l1.hardware, bcs))
1244 st->l2.l2l1 = hfcsx_l2l1;
1245 setstack_manager(st);
1251 /***************************/
1252 /* handle L1 state changes */
1253 /***************************/
1255 hfcsx_bh(struct IsdnCardState *cs)
1261 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1262 if (!cs->hw.hfcsx.nt_mode)
1263 switch (cs->dc.hfcsx.ph_state) {
1265 l1_msg(cs, HW_RESET | INDICATION, NULL);
1268 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1271 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1274 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1277 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1282 switch (cs->dc.hfcsx.ph_state) {
1284 spin_lock_irqsave(&cs->lock, flags);
1285 if (cs->hw.hfcsx.nt_timer < 0) {
1286 cs->hw.hfcsx.nt_timer = 0;
1287 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1288 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1289 /* Clear already pending ints */
1290 if (Read_hfc(cs, HFCSX_INT_S1));
1292 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1294 Write_hfc(cs, HFCSX_STATES, 4);
1295 cs->dc.hfcsx.ph_state = 4;
1297 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER;
1298 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1299 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER;
1300 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125;
1301 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1302 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1303 cs->hw.hfcsx.nt_timer = NT_T1_COUNT;
1304 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */
1306 spin_unlock_irqrestore(&cs->lock, flags);
1311 spin_lock_irqsave(&cs->lock, flags);
1312 cs->hw.hfcsx.nt_timer = 0;
1313 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1314 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1315 spin_unlock_irqrestore(&cs->lock, flags);
1322 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1323 DChannel_proc_rcv(cs);
1324 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1325 DChannel_proc_xmt(cs);
1329 /********************************/
1330 /* called for card init message */
1331 /********************************/
1333 inithfcsx(struct IsdnCardState *cs)
1335 cs->setstack_d = setstack_hfcsx;
1336 cs->BC_Send_Data = &hfcsx_send_data;
1337 cs->bcs[0].BC_SetStack = setstack_2b;
1338 cs->bcs[1].BC_SetStack = setstack_2b;
1339 cs->bcs[0].BC_Close = close_hfcsx;
1340 cs->bcs[1].BC_Close = close_hfcsx;
1341 mode_hfcsx(cs->bcs, 0, 0);
1342 mode_hfcsx(cs->bcs + 1, 0, 1);
1347 /*******************************************/
1348 /* handle card messages from control layer */
1349 /*******************************************/
1351 hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1355 if (cs->debug & L1_DEB_ISAC)
1356 debugl1(cs, "HFCSX: card_msg %x", mt);
1359 spin_lock_irqsave(&cs->lock, flags);
1361 spin_unlock_irqrestore(&cs->lock, flags);
1364 release_io_hfcsx(cs);
1367 spin_lock_irqsave(&cs->lock, flags);
1369 spin_unlock_irqrestore(&cs->lock, flags);
1370 set_current_state(TASK_UNINTERRUPTIBLE);
1371 schedule_timeout((80 * HZ) / 1000); /* Timeout 80ms */
1372 /* now switch timer interrupt off */
1373 spin_lock_irqsave(&cs->lock, flags);
1374 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1375 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1376 /* reinit mode reg */
1377 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1378 spin_unlock_irqrestore(&cs->lock, flags);
1387 static struct isapnp_device_id hfc_ids[] __initdata = {
1388 { ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1389 ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1390 (unsigned long) "Teles 16.3c2" },
1394 static struct isapnp_device_id *ipid __initdata = &hfc_ids[0];
1395 static struct pnp_card *pnp_c __devinitdata = NULL;
1399 setup_hfcsx(struct IsdnCard *card)
1401 struct IsdnCardState *cs = card->cs;
1404 strcpy(tmp, hfcsx_revision);
1405 printk(KERN_INFO "HiSax: HFC-SX driver Rev. %s\n", HiSax_getrev(tmp));
1407 if (!card->para[1] && isapnp_present()) {
1408 struct pnp_dev *pnp_d;
1409 while(ipid->card_vendor) {
1410 if ((pnp_c = pnp_find_card(ipid->card_vendor,
1411 ipid->card_device, pnp_c))) {
1413 if ((pnp_d = pnp_find_dev(pnp_c,
1414 ipid->vendor, ipid->function, pnp_d))) {
1417 printk(KERN_INFO "HiSax: %s detected\n",
1418 (char *)ipid->driver_data);
1419 pnp_disable_dev(pnp_d);
1420 err = pnp_activate_dev(pnp_d);
1422 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
1426 card->para[1] = pnp_port_start(pnp_d, 0);
1427 card->para[0] = pnp_irq(pnp_d, 0);
1428 if (!card->para[0] || !card->para[1]) {
1429 printk(KERN_ERR "HFC PnP:some resources are missing %ld/%lx\n",
1430 card->para[0], card->para[1]);
1431 pnp_disable_dev(pnp_d);
1436 printk(KERN_ERR "HFC PnP: PnP error card found, no device\n");
1442 if (!ipid->card_vendor) {
1443 printk(KERN_INFO "HFC PnP: no ISAPnP card found\n");
1448 cs->hw.hfcsx.base = card->para[1] & 0xfffe;
1449 cs->irq = card->para[0];
1450 cs->hw.hfcsx.int_s1 = 0;
1451 cs->dc.hfcsx.ph_state = 0;
1452 cs->hw.hfcsx.fifo = 255;
1453 if ((cs->typ == ISDN_CTYPE_HFC_SX) ||
1454 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) {
1455 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) {
1457 "HiSax: HFC-SX io-base %#lx already in use\n",
1461 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF);
1462 byteout(cs->hw.hfcsx.base + 1,
1463 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54);
1465 cs->hw.hfcsx.chip = Read_hfc(cs,HFCSX_CHIP_ID);
1466 switch (cs->hw.hfcsx.chip >> 4) {
1475 "HFC-SX: invalid chip id 0x%x\n",
1476 cs->hw.hfcsx.chip >> 4);
1477 release_region(cs->hw.hfcsx.base, 2);
1480 if (!ccd_sp_irqtab[cs->irq & 0xF]) {
1482 "HFC_SX: invalid irq %d specified\n",cs->irq & 0xF);
1483 release_region(cs->hw.hfcsx.base, 2);
1486 if (!(cs->hw.hfcsx.extra = (void *)
1487 kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) {
1488 release_region(cs->hw.hfcsx.base, 2);
1489 printk(KERN_WARNING "HFC-SX: unable to allocate memory\n");
1492 printk(KERN_INFO "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n",
1493 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ);
1494 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */
1495 cs->hw.hfcsx.int_m1 = 0;
1496 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1497 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
1499 return (0); /* no valid card type */
1501 cs->dbusytimer.function = (void *) hfcsx_dbusy_timer;
1502 cs->dbusytimer.data = (long) cs;
1503 init_timer(&cs->dbusytimer);
1504 INIT_WORK(&cs->tqueue, (void *)(void *) hfcsx_bh, cs);
1505 cs->readisac = NULL;
1506 cs->writeisac = NULL;
1507 cs->readisacfifo = NULL;
1508 cs->writeisacfifo = NULL;
1509 cs->BC_Read_Reg = NULL;
1510 cs->BC_Write_Reg = NULL;
1511 cs->irq_func = &hfcsx_interrupt;
1513 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer;
1514 cs->hw.hfcsx.timer.data = (long) cs;
1515 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */
1516 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */
1517 init_timer(&cs->hw.hfcsx.timer);
1520 cs->cardmsg = &hfcsx_card_msg;
1521 cs->auxcmd = &hfcsx_auxcmd;