2 * skystar2.c - driver for the Technisat SkyStar2 PCI DVB card
3 * based on the FlexCopII by B2C2,Inc.
5 * Copyright (C) 2003 Vadim Catana, skystar@moldova.cc
7 * FIX: DISEQC Tone Burst in flexcop_diseqc_ioctl()
8 * FIX: FULL soft DiSEqC for skystar2 (FlexCopII rev 130) VP310 equipped
9 * Vincenzo Di Massa, hawk.it at tiscalinet.it
11 * Converted to Linux coding style
12 * Misc reorganization, polishing, restyling
13 * Roberto Ragusa, r.ragusa at libero.it
15 * Added hardware filtering support,
16 * Niklas Peinecke, peinecke at gdv.uni-hannover.de
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU Lesser General Public License
21 * as published by the Free Software Foundation; either version 2.1
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU Lesser General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/module.h>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
41 #include "dvb_frontend.h"
43 #include <linux/dvb/frontend.h>
44 #include <linux/dvb/dmx.h>
45 #include "dvb_demux.h"
47 #include "dvb_filter.h"
52 #include "dvb_functions.h"
55 #define dprintk(x...) do { if (debug>=1) printk(x); } while (0)
56 #define ddprintk(x...) do { if (debug>=2) printk(x); } while (0)
57 static int enable_hw_filters = 2;
59 #define SIZE_OF_BUF_DMA1 0x3ac00
60 #define SIZE_OF_BUF_DMA2 0x758
62 #define MAX_N_HW_FILTERS (6+32)
63 #define N_PID_SLOTS 256
83 unsigned long io_port;
87 struct dvb_adapter *dvb_adapter;
88 struct dvb_demux demux;
90 struct dmx_frontend hw_frontend;
91 struct dmx_frontend mem_frontend;
92 struct dvb_i2c_bus *i2c_bus;
93 struct dvb_net dvbnet;
95 struct semaphore i2c_sem;
107 int useable_hw_filters;
108 u16 hw_pids[MAX_N_HW_FILTERS];
109 u16 pid_list[N_PID_SLOTS];
110 int pid_rc[N_PID_SLOTS]; // ref counters for the pids
112 int whole_bandwidth_count;
116 #define write_reg_dw(adapter,reg,value) writel(value, adapter->io_mem + reg)
117 #define read_reg_dw(adapter,reg) readl(adapter->io_mem + reg)
119 static void write_reg_bitfield(struct adapter *adapter, u32 reg, u32 zeromask, u32 orvalue)
123 tmp = read_reg_dw(adapter, reg);
124 tmp = (tmp & ~zeromask) | orvalue;
125 write_reg_dw(adapter, reg, tmp);
129 static int i2c_main_write_for_flex2(struct adapter *adapter, u32 command, u8 *buf, int retries)
134 write_reg_dw(adapter, 0x100, 0);
135 write_reg_dw(adapter, 0x100, command);
137 for (i = 0; i < retries; i++) {
138 value = read_reg_dw(adapter, 0x100);
140 if ((value & 0x40000000) == 0) {
141 if ((value & 0x81000000) == 0x80000000) {
143 *buf = (value >> 0x10) & 0xff;
148 write_reg_dw(adapter, 0x100, 0);
149 write_reg_dw(adapter, 0x100, command);
156 /* device = 0x10000000 for tuner, 0x20000000 for eeprom */
157 static void i2c_main_setup(u32 device, u32 chip_addr, u8 op, u8 addr, u32 value, u32 len, u32 *command)
159 *command = device | ((len - 1) << 26) | (value << 16) | (addr << 8) | chip_addr;
162 *command = *command | 0x03000000;
164 *command = *command | 0x01000000;
167 static int flex_i2c_read4(struct adapter *adapter, u32 device, u32 chip_addr, u16 addr, u8 *buf, u8 len)
174 i2c_main_setup(device, chip_addr, 1, addr, 0, len, &command);
176 result = i2c_main_write_for_flex2(adapter, command, buf, 100000);
178 if ((result & 0xff) != 0) {
180 value = read_reg_dw(adapter, 0x104);
182 for (i = 1; i < len; i++) {
183 buf[i] = value & 0xff;
192 static int flex_i2c_write4(struct adapter *adapter, u32 device, u32 chip_addr, u32 addr, u8 *buf, u8 len)
201 for (i = len; i > 1; i--) {
203 value = value | buf[i - 1];
206 write_reg_dw(adapter, 0x104, value);
209 i2c_main_setup(device, chip_addr, 0, addr, buf[0], len, &command);
211 return i2c_main_write_for_flex2(adapter, command, NULL, 100000);
214 static void fixchipaddr(u32 device, u32 bus, u32 addr, u32 *ret)
216 if (device == 0x20000000)
217 *ret = bus | ((addr >> 8) & 3);
222 static u32 flex_i2c_read(struct adapter *adapter, u32 device, u32 bus, u32 addr, u8 *buf, u32 len)
225 u32 bytes_to_transfer;
228 ddprintk("%s:\n", __FUNCTION__);
233 bytes_to_transfer = len;
235 if (bytes_to_transfer > 4)
236 bytes_to_transfer = 4;
238 fixchipaddr(device, bus, addr, &chipaddr);
240 if (flex_i2c_read4(adapter, device, chipaddr, addr, buf, bytes_to_transfer) == 0)
243 buf = buf + bytes_to_transfer;
244 addr = addr + bytes_to_transfer;
245 len = len - bytes_to_transfer;
251 static u32 flex_i2c_write(struct adapter *adapter, u32 device, u32 bus, u32 addr, u8 *buf, u32 len)
254 u32 bytes_to_transfer;
257 ddprintk("%s:\n", __FUNCTION__);
262 bytes_to_transfer = len;
264 if (bytes_to_transfer > 4)
265 bytes_to_transfer = 4;
267 fixchipaddr(device, bus, addr, &chipaddr);
269 if (flex_i2c_write4(adapter, device, chipaddr, addr, buf, bytes_to_transfer) == 0)
272 buf = buf + bytes_to_transfer;
273 addr = addr + bytes_to_transfer;
274 len = len - bytes_to_transfer;
280 static int master_xfer(struct dvb_i2c_bus *i2c, const struct i2c_msg *msgs, int num)
282 struct adapter *tmp = i2c->data;
285 if (down_interruptible(&tmp->i2c_sem))
288 ddprintk("%s: %d messages to transfer\n", __FUNCTION__, num);
290 for (i = 0; i < num; i++) {
291 ddprintk("message %d: flags=0x%x, addr=0x%x, buf=0x%x, len=%d \n", i,
292 msgs[i].flags, msgs[i].addr, msgs[i].buf[0], msgs[i].len);
294 /* allow only the mt312 and stv0299 frontends to access the bus */
295 if ((msgs[i].addr != 0x0e) && (msgs[i].addr != 0x68) && (msgs[i].addr != 0x61)) {
303 if ((num == 2) && (msgs[0].flags == 0) && (msgs[1].flags == I2C_M_RD) && (msgs[0].buf != NULL) && (msgs[1].buf != NULL)) {
305 ret = flex_i2c_read(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], msgs[1].buf, msgs[1].len);
309 if (ret != msgs[1].len) {
310 printk("%s: read error !\n", __FUNCTION__);
312 for (i = 0; i < 2; i++) {
313 printk("message %d: flags=0x%x, addr=0x%x, buf=0x%x, len=%d \n", i,
314 msgs[i].flags, msgs[i].addr, msgs[i].buf[0], msgs[i].len);
323 for (i = 0; i < num; i++) {
325 if ((msgs[i].flags != 0) || (msgs[i].buf == NULL) || (msgs[i].len < 2))
328 ret = flex_i2c_write(tmp, 0x10000000, msgs[i].addr, msgs[i].buf[0], &msgs[i].buf[1], msgs[i].len - 1);
332 if (ret != msgs[0].len - 1) {
333 printk("%s: write error %i !\n", __FUNCTION__, ret);
335 printk("message %d: flags=0x%x, addr=0x%x, buf[0]=0x%x, len=%d \n", i,
336 msgs[i].flags, msgs[i].addr, msgs[i].buf[0], msgs[i].len);
344 printk("%s: unknown command format !\n", __FUNCTION__);
349 /* SRAM (Skystar2 rev2.3 has one "ISSI IS61LV256" chip on board,
350 but it seems that FlexCopII can work with more than one chip) */
351 static void sram_set_net_dest(struct adapter *adapter, u8 dest)
357 tmp = (read_reg_dw(adapter, 0x714) & 0xfffffffc) | (dest & 3);
361 write_reg_dw(adapter, 0x714, tmp);
362 write_reg_dw(adapter, 0x714, tmp);
366 /* return value is never used? */
370 static void sram_set_cai_dest(struct adapter *adapter, u8 dest)
376 tmp = (read_reg_dw(adapter, 0x714) & 0xfffffff3) | ((dest & 3) << 2);
381 write_reg_dw(adapter, 0x714, tmp);
382 write_reg_dw(adapter, 0x714, tmp);
386 /* return value is never used? */
390 static void sram_set_cao_dest(struct adapter *adapter, u8 dest)
396 tmp = (read_reg_dw(adapter, 0x714) & 0xffffffcf) | ((dest & 3) << 4);
401 write_reg_dw(adapter, 0x714, tmp);
402 write_reg_dw(adapter, 0x714, tmp);
406 /* return value is never used? */
410 static void sram_set_media_dest(struct adapter *adapter, u8 dest)
416 tmp = (read_reg_dw(adapter, 0x714) & 0xffffff3f) | ((dest & 3) << 6);
421 write_reg_dw(adapter, 0x714, tmp);
422 write_reg_dw(adapter, 0x714, tmp);
426 /* return value is never used? */
430 /* SRAM memory is accessed through a buffer register in the FlexCop
431 chip (0x700). This register has the following structure:
433 bit 15 : read/write flag
434 bits 16-23 : 8-bit word to write
436 bits 28-29 : memory bank selector
439 static void flex_sram_write(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)
444 for (i = 0; i < len; i++) {
445 command = bank | addr | 0x04000000 | (*buf << 0x10);
449 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
455 printk("%s: SRAM timeout\n", __FUNCTION__);
457 write_reg_dw(adapter, 0x700, command);
464 static void flex_sram_read(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)
469 for (i = 0; i < len; i++) {
470 command = bank | addr | 0x04008000;
474 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
480 printk("%s: SRAM timeout\n", __FUNCTION__);
482 write_reg_dw(adapter, 0x700, command);
486 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
492 printk("%s: SRAM timeout\n", __FUNCTION__);
494 value = read_reg_dw(adapter, 0x700) >> 0x10;
496 *buf = (value & 0xff);
503 static void sram_write_chunk(struct adapter *adapter, u32 addr, u8 *buf, u16 len)
509 if (adapter->dw_sram_type == 0x20000) {
510 bank = (addr & 0x18000) << 0x0d;
513 if (adapter->dw_sram_type == 0x00000) {
514 if ((addr >> 0x0f) == 0)
520 flex_sram_write(adapter, bank, addr & 0x7fff, buf, len);
523 static void sram_read_chunk(struct adapter *adapter, u32 addr, u8 *buf, u16 len)
529 if (adapter->dw_sram_type == 0x20000) {
530 bank = (addr & 0x18000) << 0x0d;
533 if (adapter->dw_sram_type == 0x00000) {
534 if ((addr >> 0x0f) == 0)
540 flex_sram_read(adapter, bank, addr & 0x7fff, buf, len);
543 static void sram_read(struct adapter *adapter, u32 addr, u8 *buf, u32 len)
550 // check if the address range belongs to the same
551 // 32K memory chip. If not, the data is read from
552 // one chip at a time.
553 if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {
554 length = (((addr >> 0x0f) + 1) << 0x0f) - addr;
557 sram_read_chunk(adapter, addr, buf, length);
559 addr = addr + length;
565 static void sram_write(struct adapter *adapter, u32 addr, u8 *buf, u32 len)
572 // check if the address range belongs to the same
573 // 32K memory chip. If not, the data is written to
574 // one chip at a time.
575 if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {
576 length = (((addr >> 0x0f) + 1) << 0x0f) - addr;
579 sram_write_chunk(adapter, addr, buf, length);
581 addr = addr + length;
587 static void sram_set_size(struct adapter *adapter, u32 mask)
589 write_reg_dw(adapter, 0x71c, (mask | (~0x30000 & read_reg_dw(adapter, 0x71c))));
592 static void sram_init(struct adapter *adapter)
596 tmp = read_reg_dw(adapter, 0x71c);
598 write_reg_dw(adapter, 0x71c, 1);
600 if (read_reg_dw(adapter, 0x71c) != 0) {
601 write_reg_dw(adapter, 0x71c, tmp);
603 adapter->dw_sram_type = tmp & 0x30000;
605 ddprintk("%s: dw_sram_type = %x\n", __FUNCTION__, adapter->dw_sram_type);
609 adapter->dw_sram_type = 0x10000;
611 ddprintk("%s: dw_sram_type = %x\n", __FUNCTION__, adapter->dw_sram_type);
614 /* return value is never used? */
615 /* return adapter->dw_sram_type; */
618 static int sram_test_location(struct adapter *adapter, u32 mask, u32 addr)
622 dprintk("%s: mask = %x, addr = %x\n", __FUNCTION__, mask, addr);
624 sram_set_size(adapter, mask);
630 sram_write(adapter, addr, &tmp2, 1);
631 sram_write(adapter, addr + 4, &tmp1, 1);
637 sram_read(adapter, addr, &tmp2, 1);
638 sram_read(adapter, addr, &tmp2, 1);
640 dprintk("%s: wrote 0xa5, read 0x%2x\n", __FUNCTION__, tmp2);
648 sram_write(adapter, addr, &tmp2, 1);
649 sram_write(adapter, addr + 4, &tmp1, 1);
655 sram_read(adapter, addr, &tmp2, 1);
656 sram_read(adapter, addr, &tmp2, 1);
658 dprintk("%s: wrote 0x5a, read 0x%2x\n", __FUNCTION__, tmp2);
666 static u32 sram_length(struct adapter *adapter)
668 if (adapter->dw_sram_type == 0x10000)
670 if (adapter->dw_sram_type == 0x00000)
672 if (adapter->dw_sram_type == 0x20000)
673 return 131072; // 128K
678 /* FlexcopII can work with 32K, 64K or 128K of external SRAM memory.
679 - for 128K there are 4x32K chips at bank 0,1,2,3.
680 - for 64K there are 2x32K chips at bank 1,2.
681 - for 32K there is one 32K chip at bank 0.
683 FlexCop works only with one bank at a time. The bank is selected
684 by bits 28-29 of the 0x700 register.
686 bank 0 covers addresses 0x00000-0x07fff
687 bank 1 covers addresses 0x08000-0x0ffff
688 bank 2 covers addresses 0x10000-0x17fff
689 bank 3 covers addresses 0x18000-0x1ffff
691 static int sram_detect_for_flex2(struct adapter *adapter)
695 dprintk("%s:\n", __FUNCTION__);
697 tmp = read_reg_dw(adapter, 0x208);
698 write_reg_dw(adapter, 0x208, 0);
700 tmp2 = read_reg_dw(adapter, 0x71c);
702 dprintk("%s: tmp2 = %x\n", __FUNCTION__, tmp2);
704 write_reg_dw(adapter, 0x71c, 1);
706 tmp3 = read_reg_dw(adapter, 0x71c);
708 dprintk("%s: tmp3 = %x\n", __FUNCTION__, tmp3);
710 write_reg_dw(adapter, 0x71c, tmp2);
712 // check for internal SRAM ???
715 sram_set_size(adapter, 0x10000);
717 write_reg_dw(adapter, 0x208, tmp);
719 dprintk("%s: sram size = 32K\n", __FUNCTION__);
724 if (sram_test_location(adapter, 0x20000, 0x18000) != 0) {
725 sram_set_size(adapter, 0x20000);
727 write_reg_dw(adapter, 0x208, tmp);
729 dprintk("%s: sram size = 128K\n", __FUNCTION__);
734 if (sram_test_location(adapter, 0x00000, 0x10000) != 0) {
735 sram_set_size(adapter, 0x00000);
737 write_reg_dw(adapter, 0x208, tmp);
739 dprintk("%s: sram size = 64K\n", __FUNCTION__);
744 if (sram_test_location(adapter, 0x10000, 0x00000) != 0) {
745 sram_set_size(adapter, 0x10000);
747 write_reg_dw(adapter, 0x208, tmp);
749 dprintk("%s: sram size = 32K\n", __FUNCTION__);
754 sram_set_size(adapter, 0x10000);
756 write_reg_dw(adapter, 0x208, tmp);
758 dprintk("%s: SRAM detection failed. Set to 32K \n", __FUNCTION__);
763 static void sll_detect_sram_size(struct adapter *adapter)
765 sram_detect_for_flex2(adapter);
768 /* EEPROM (Skystar2 has one "24LC08B" chip on board) */
770 static int eeprom_write(struct adapter *adapter, u16 addr, u8 *buf, u16 len)
772 return flex_i2c_write(adapter, 0x20000000, 0x50, addr, buf, len);
776 static int eeprom_read(struct adapter *adapter, u16 addr, u8 *buf, u16 len)
778 return flex_i2c_read(adapter, 0x20000000, 0x50, addr, buf, len);
781 u8 calc_lrc(u8 *buf, int len)
788 for (i = 0; i < len; i++)
794 static int eeprom_lrc_read(struct adapter *adapter, u32 addr, u32 len, u8 *buf, int retries)
798 for (i = 0; i < retries; i++) {
799 if (eeprom_read(adapter, addr, buf, len) == len) {
800 if (calc_lrc(buf, len - 1) == buf[len - 1])
809 static int eeprom_lrc_write(struct adapter *adapter, u32 addr, u32 len, u8 *wbuf, u8 *rbuf, int retries)
813 for (i = 0; i < retries; i++) {
814 if (eeprom_write(adapter, addr, wbuf, len) == len) {
815 if (eeprom_lrc_read(adapter, addr, len, rbuf, retries) == 1)
825 /* These functions could be used to unlock SkyStar2 cards. */
828 static int eeprom_writeKey(struct adapter *adapter, u8 *key, u32 len)
836 memcpy(wbuf, key, len);
841 wbuf[19] = calc_lrc(wbuf, 19);
843 return eeprom_lrc_write(adapter, 0x3e4, 20, wbuf, rbuf, 4);
846 static int eeprom_readKey(struct adapter *adapter, u8 *key, u32 len)
853 if (eeprom_lrc_read(adapter, 0x3e4, 20, buf, 4) == 0)
856 memcpy(key, buf, len);
862 static int eeprom_get_mac_addr(struct adapter *adapter, char type, u8 *mac)
866 if (eeprom_lrc_read(adapter, 0x3f8, 8, tmp, 4) != 0) {
904 static char eeprom_set_mac_addr(struct adapter *adapter, char type, u8 *mac)
927 tmp[7] = calc_lrc(tmp, 7);
929 if (eeprom_write(adapter, 0x3f8, tmp, 8) == 8)
938 /* every flexcop has 6 "lower" hw PID filters */
939 /* these are enabled by setting bits 0-5 of 0x208 */
940 /* for the 32 additional filters we have to select one */
941 /* of them through 0x310 and modify through 0x314 */
942 /* op: 0=disable, 1=enable */
943 static void filter_enable_hw_filter(struct adapter *adapter, int id, u8 op)
945 dprintk("%s: id=%d op=%d\n", __FUNCTION__, id, op);
947 u32 mask = (0x00000001 << id);
948 write_reg_bitfield(adapter, 0x208, mask, op ? mask : 0);
951 write_reg_bitfield(adapter, 0x310, 0x1f, (id - 6) & 0x1f);
953 write_reg_bitfield(adapter, 0x314, 0x00006000, op ? 0x00004000 : 0);
957 /* this sets the PID that should pass the specified filter */
958 static void pid_set_hw_pid(struct adapter *adapter, int id, u16 pid)
960 dprintk("%s: id=%d pid=%d\n", __FUNCTION__, id, pid);
962 u32 adr = 0x300 + ((id & 6) << 1);
963 int shift = (id & 1) ? 16 : 0;
964 dprintk("%s: id=%d addr=%x %c pid=%d\n", __FUNCTION__, id, adr, (id & 1) ? 'h' : 'l', pid);
965 write_reg_bitfield(adapter, adr, (0x7fff) << shift, (pid & 0x1fff) << shift);
968 write_reg_bitfield(adapter, 0x310, 0x1f, (id - 6) & 0x1f);
970 write_reg_bitfield(adapter, 0x314, 0x1fff, pid & 0x1fff);
976 static void filter_enable_null_filter(struct adapter *adapter, u32 op)
978 dprintk("%s: op=%x\n", __FUNCTION__, op);
980 write_reg_bitfield(adapter, 0x208, 0x00000040, op?0x00000040:0);
984 static void filter_enable_mask_filter(struct adapter *adapter, u32 op)
986 dprintk("%s: op=%x\n", __FUNCTION__, op);
988 write_reg_bitfield(adapter, 0x208, 0x00000080, op ? 0x00000080 : 0);
992 static void ctrl_enable_mac(struct adapter *adapter, u32 op)
994 write_reg_bitfield(adapter, 0x208, 0x00004000, op ? 0x00004000 : 0);
997 static int ca_set_mac_dst_addr_filter(struct adapter *adapter, u8 *mac)
1001 tmp1 = (mac[3] << 0x18) | (mac[2] << 0x10) | (mac[1] << 0x08) | mac[0];
1002 tmp2 = (mac[5] << 0x08) | mac[4];
1004 write_reg_dw(adapter, 0x418, tmp1);
1005 write_reg_dw(adapter, 0x41c, tmp2);
1011 static void set_ignore_mac_filter(struct adapter *adapter, u8 op)
1014 write_reg_bitfield(adapter, 0x208, 0x00004000, 0);
1015 adapter->mac_filter = 1;
1017 if (adapter->mac_filter != 0) {
1018 adapter->mac_filter = 0;
1019 write_reg_bitfield(adapter, 0x208, 0x00004000, 0x00004000);
1026 static void check_null_filter_enable(struct adapter *adapter)
1028 filter_enable_null_filter(adapter, 1);
1029 filter_enable_mask_filter(adapter, 1);
1033 static void pid_set_group_pid(struct adapter *adapter, u16 pid)
1037 dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1038 value = (pid & 0x3fff) | (read_reg_dw(adapter, 0x30c) & 0xffff0000);
1039 write_reg_dw(adapter, 0x30c, value);
1042 static void pid_set_group_mask(struct adapter *adapter, u16 pid)
1046 dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1047 value = ((pid & 0x3fff) << 0x10) | (read_reg_dw(adapter, 0x30c) & 0xffff);
1048 write_reg_dw(adapter, 0x30c, value);
1052 static int pid_get_group_pid(struct adapter *adapter)
1054 return read_reg_dw(adapter, 0x30c) & 0x00001fff;
1057 static int pid_get_group_mask(struct adapter *adapter)
1059 return (read_reg_dw(adapter, 0x30c) >> 0x10)& 0x00001fff;
1064 static void reset_hardware_pid_filter(struct adapter *adapter)
1066 pid_set_stream1_pid(adapter, 0x1fff);
1068 pid_set_stream2_pid(adapter, 0x1fff);
1069 filter_enable_stream2_filter(adapter, 0);
1071 pid_set_pcr_pid(adapter, 0x1fff);
1072 filter_enable_pcr_filter(adapter, 0);
1074 pid_set_pmt_pid(adapter, 0x1fff);
1075 filter_enable_pmt_filter(adapter, 0);
1077 pid_set_ecm_pid(adapter, 0x1fff);
1078 filter_enable_ecm_filter(adapter, 0);
1080 pid_set_emm_pid(adapter, 0x1fff);
1081 filter_enable_emm_filter(adapter, 0);
1085 static void init_pids(struct adapter *adapter)
1089 adapter->pid_count = 0;
1090 adapter->whole_bandwidth_count = 0;
1091 for (i = 0; i < adapter->useable_hw_filters; i++) {
1092 dprintk("%s: setting filter %d to 0x1fff\n", __FUNCTION__, i);
1093 adapter->hw_pids[i] = 0x1fff;
1094 pid_set_hw_pid(adapter, i, 0x1fff);
1097 pid_set_group_pid(adapter, 0);
1098 pid_set_group_mask(adapter, 0x1fe0);
1101 static void open_whole_bandwidth(struct adapter *adapter)
1103 dprintk("%s:\n", __FUNCTION__);
1104 pid_set_group_pid(adapter, 0);
1105 pid_set_group_mask(adapter, 0);
1107 filter_enable_mask_filter(adapter, 1);
1111 static void close_whole_bandwidth(struct adapter *adapter)
1113 dprintk("%s:\n", __FUNCTION__);
1114 pid_set_group_pid(adapter, 0);
1115 pid_set_group_mask(adapter, 0x1fe0);
1117 filter_enable_mask_filter(adapter, 1);
1121 static void whole_bandwidth_inc(struct adapter *adapter)
1123 if (adapter->whole_bandwidth_count++ == 0)
1124 open_whole_bandwidth(adapter);
1127 static void whole_bandwidth_dec(struct adapter *adapter)
1129 if (--adapter->whole_bandwidth_count <= 0)
1130 close_whole_bandwidth(adapter);
1133 /* The specified PID has to be let through the
1135 We try to allocate an hardware filter and open whole
1136 bandwidth when allocation is impossible.
1137 All pids<=0x1f pass through the group filter.
1138 Returns 1 on success, -1 on error */
1139 static int add_hw_pid(struct adapter *adapter, u16 pid)
1143 dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1148 /* we can't use a filter for 0x2000, so no search */
1149 if (pid != 0x2000) {
1150 /* find an unused hardware filter */
1151 for (i = 0; i < adapter->useable_hw_filters; i++) {
1152 dprintk("%s: pid=%d searching slot=%d\n", __FUNCTION__, pid, i);
1153 if (adapter->hw_pids[i] == 0x1fff) {
1154 dprintk("%s: pid=%d slot=%d\n", __FUNCTION__, pid, i);
1155 adapter->hw_pids[i] = pid;
1156 pid_set_hw_pid(adapter, i, pid);
1157 filter_enable_hw_filter(adapter, i, 1);
1162 /* if we have not used a filter, this pid depends on whole bandwidth */
1163 dprintk("%s: pid=%d whole_bandwidth\n", __FUNCTION__, pid);
1164 whole_bandwidth_inc(adapter);
1168 /* returns -1 if the pid was not present in the filters */
1169 static int remove_hw_pid(struct adapter *adapter, u16 pid)
1173 dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1178 /* we can't use a filter for 0x2000, so no search */
1179 if (pid != 0x2000) {
1180 for (i = 0; i < adapter->useable_hw_filters; i++) {
1181 dprintk("%s: pid=%d searching slot=%d\n", __FUNCTION__, pid, i);
1182 if (adapter->hw_pids[i] == pid) { // find the pid slot
1183 dprintk("%s: pid=%d slot=%d\n", __FUNCTION__, pid, i);
1184 adapter->hw_pids[i] = 0x1fff;
1185 pid_set_hw_pid(adapter, i, 0x1fff);
1186 filter_enable_hw_filter(adapter, i, 0);
1191 /* if we have not used a filter, this pid depended on whole bandwith */
1192 dprintk("%s: pid=%d whole_bandwidth\n", __FUNCTION__, pid);
1193 whole_bandwidth_dec(adapter);
1197 /* Adds a PID to the filters.
1198 Adding a pid more than once is possible, we keep reference counts.
1199 Whole stream available through pid==0x2000.
1200 Returns 1 on success, -1 on error */
1201 static int add_pid(struct adapter *adapter, u16 pid)
1205 dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1207 if (pid > 0x1ffe && pid != 0x2000)
1210 // check if the pid is already present
1211 for (i = 0; i < adapter->pid_count; i++)
1212 if (adapter->pid_list[i] == pid) {
1213 adapter->pid_rc[i]++; // increment ref counter
1217 if (adapter->pid_count == N_PID_SLOTS)
1218 return -1; // no more pids can be added
1219 adapter->pid_list[adapter->pid_count] = pid; // register pid
1220 adapter->pid_rc[adapter->pid_count] = 1;
1221 adapter->pid_count++;
1223 add_hw_pid(adapter, pid);
1228 /* Removes a PID from the filters. */
1229 static int remove_pid(struct adapter *adapter, u16 pid)
1233 dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1235 if (pid > 0x1ffe && pid != 0x2000)
1238 // check if the pid is present (it must be!)
1239 for (i = 0; i < adapter->pid_count; i++) {
1240 if (adapter->pid_list[i] == pid) {
1241 adapter->pid_rc[i]--;
1242 if (adapter->pid_rc[i] <= 0) {
1243 // remove from the list
1244 adapter->pid_count--;
1245 adapter->pid_list[i]=adapter->pid_list[adapter->pid_count];
1246 adapter->pid_rc[i] = adapter->pid_rc[adapter->pid_count];
1248 remove_hw_pid(adapter, pid);
1259 static void ctrl_enable_smc(struct adapter *adapter, u32 op)
1261 write_reg_bitfield(adapter, 0x208, 0x00000800, op ? 0x00000800 : 0);
1264 static void dma_enable_disable_irq(struct adapter *adapter, u32 flag1, u32 flag2, u32 flag3)
1266 adapter->dma_ctrl = adapter->dma_ctrl & 0x000f0000;
1270 adapter->dma_ctrl = adapter->dma_ctrl & ~0x00010000;
1272 adapter->dma_ctrl = adapter->dma_ctrl | 0x00010000;
1275 adapter->dma_ctrl = adapter->dma_ctrl & ~0x00020000;
1277 adapter->dma_ctrl = adapter->dma_ctrl | 0x00020000;
1282 adapter->dma_ctrl = adapter->dma_ctrl & ~0x00040000;
1284 adapter->dma_ctrl = adapter->dma_ctrl | 0x00040000;
1287 adapter->dma_ctrl = adapter->dma_ctrl & ~0x00080000;
1289 adapter->dma_ctrl = adapter->dma_ctrl | 0x00080000;
1293 static void irq_dma_enable_disable_irq(struct adapter *adapter, u32 op)
1297 value = read_reg_dw(adapter, 0x208) & 0xfff0ffff;
1300 value = value | (adapter->dma_ctrl & 0x000f0000);
1302 write_reg_dw(adapter, 0x208, value);
1305 /* FlexCopII has 2 dma channels. DMA1 is used to transfer TS data to
1308 The DMA1 buffer is divided in 2 subbuffers of equal size.
1309 FlexCopII will transfer TS data to one subbuffer, signal an interrupt
1310 when the subbuffer is full and continue fillig the second subbuffer.
1313 subbuffer size in 32-bit words is stored in the first 24 bits of
1314 register 0x004. The last 8 bits of register 0x004 contain the number
1317 the first 30 bits of register 0x000 contain the address of the first
1318 subbuffer. The last 2 bits contain 0, when dma1 is disabled and 1,
1319 when dma1 is enabled.
1321 the first 30 bits of register 0x00c contain the address of the second
1322 subbuffer. the last 2 bits contain 1.
1324 register 0x008 will contain the address of the subbuffer that was filled
1325 with TS data, when FlexCopII will generate an interrupt.
1328 subbuffer size in 32-bit words is stored in the first 24 bits of
1329 register 0x014. The last 8 bits of register 0x014 contain the number
1332 the first 30 bits of register 0x010 contain the address of the first
1333 subbuffer. The last 2 bits contain 0, when dma1 is disabled and 1,
1334 when dma1 is enabled.
1336 the first 30 bits of register 0x01c contain the address of the second
1337 subbuffer. the last 2 bits contain 1.
1339 register 0x018 contains the address of the subbuffer that was filled
1340 with TS data, when FlexCopII generates an interrupt.
1342 static int dma_init_dma(struct adapter *adapter, u32 dma_channel)
1344 u32 subbuffers, subbufsize, subbuf0, subbuf1;
1346 if (dma_channel == 0) {
1347 dprintk("%s: Initializing DMA1 channel\n", __FUNCTION__);
1351 subbufsize = (((adapter->dmaq1.buffer_size / 2) / 4) << 8) | subbuffers;
1353 subbuf0 = adapter->dmaq1.bus_addr & 0xfffffffc;
1355 subbuf1 = ((adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) & 0xfffffffc) | 1;
1357 dprintk("%s: first subbuffer address = 0x%x\n", __FUNCTION__, subbuf0);
1359 write_reg_dw(adapter, 0x000, subbuf0);
1361 dprintk("%s: subbuffer size = 0x%x\n", __FUNCTION__, (subbufsize >> 8) * 4);
1363 write_reg_dw(adapter, 0x004, subbufsize);
1365 dprintk("%s: second subbuffer address = 0x%x\n", __FUNCTION__, subbuf1);
1367 write_reg_dw(adapter, 0x00c, subbuf1);
1369 dprintk("%s: counter = 0x%x\n", __FUNCTION__, adapter->dmaq1.bus_addr & 0xfffffffc);
1370 write_reg_dw(adapter, 0x008, adapter->dmaq1.bus_addr & 0xfffffffc);
1373 if (subbuffers == 0)
1374 dma_enable_disable_irq(adapter, 0, 1, 0);
1376 dma_enable_disable_irq(adapter, 0, 1, 1);
1378 irq_dma_enable_disable_irq(adapter, 1);
1380 sram_set_media_dest(adapter, 1);
1381 sram_set_net_dest(adapter, 1);
1382 sram_set_cai_dest(adapter, 2);
1383 sram_set_cao_dest(adapter, 2);
1386 if (dma_channel == 1) {
1387 dprintk("%s: Initializing DMA2 channel\n", __FUNCTION__);
1391 subbufsize = (((adapter->dmaq2.buffer_size / 2) / 4) << 8) | subbuffers;
1393 subbuf0 = adapter->dmaq2.bus_addr & 0xfffffffc;
1395 subbuf1 = ((adapter->dmaq2.bus_addr + adapter->dmaq2.buffer_size / 2) & 0xfffffffc) | 1;
1397 dprintk("%s: first subbuffer address = 0x%x\n", __FUNCTION__, subbuf0);
1399 write_reg_dw(adapter, 0x010, subbuf0);
1401 dprintk("%s: subbuffer size = 0x%x\n", __FUNCTION__, (subbufsize >> 8) * 4);
1403 write_reg_dw(adapter, 0x014, subbufsize);
1405 dprintk("%s: second buffer address = 0x%x\n", __FUNCTION__, subbuf1);
1407 write_reg_dw(adapter, 0x01c, subbuf1);
1409 sram_set_cai_dest(adapter, 2);
1415 static void ctrl_enable_receive_data(struct adapter *adapter, u32 op)
1418 write_reg_bitfield(adapter, 0x208, 0x00008000, 0);
1419 adapter->dma_status = adapter->dma_status & ~0x00000004;
1421 write_reg_bitfield(adapter, 0x208, 0x00008000, 0x00008000);
1422 adapter->dma_status = adapter->dma_status | 0x00000004;
1426 /* bit 0 of dma_mask is set to 1 if dma1 channel has to be enabled/disabled
1427 bit 1 of dma_mask is set to 1 if dma2 channel has to be enabled/disabled
1429 static void dma_start_stop(struct adapter *adapter, u32 dma_mask, int start_stop)
1431 u32 dma_enable, dma1_enable, dma2_enable;
1433 dprintk("%s: dma_mask=%x\n", __FUNCTION__, dma_mask);
1435 if (start_stop == 1) {
1436 dprintk("%s: starting dma\n", __FUNCTION__);
1441 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) == 0) && (adapter->dmaq1.bus_addr != 0)) {
1442 adapter->dma_status = adapter->dma_status | 1;
1446 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) == 0) && (adapter->dmaq2.bus_addr != 0)) {
1447 adapter->dma_status = adapter->dma_status | 2;
1450 // enable dma1 and dma2
1451 if ((dma1_enable == 1) && (dma2_enable == 1)) {
1452 write_reg_dw(adapter, 0x000, adapter->dmaq1.bus_addr | 1);
1453 write_reg_dw(adapter, 0x00c, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1454 write_reg_dw(adapter, 0x010, adapter->dmaq2.bus_addr | 1);
1456 ctrl_enable_receive_data(adapter, 1);
1461 if ((dma1_enable == 1) && (dma2_enable == 0)) {
1462 write_reg_dw(adapter, 0x000, adapter->dmaq1.bus_addr | 1);
1463 write_reg_dw(adapter, 0x00c, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1465 ctrl_enable_receive_data(adapter, 1);
1470 if ((dma1_enable == 0) && (dma2_enable == 1)) {
1471 write_reg_dw(adapter, 0x010, adapter->dmaq2.bus_addr | 1);
1473 ctrl_enable_receive_data(adapter, 1);
1478 if ((dma1_enable == 0) && (dma2_enable == 0)) {
1479 ctrl_enable_receive_data(adapter, 1);
1486 dprintk("%s: stopping dma\n", __FUNCTION__);
1488 dma_enable = adapter->dma_status & 0x00000003;
1490 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) != 0)) {
1491 dma_enable = dma_enable & 0xfffffffe;
1494 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) != 0)) {
1495 dma_enable = dma_enable & 0xfffffffd;
1498 if ((dma_enable == 0) && ((adapter->dma_status & 4) != 0)) {
1499 ctrl_enable_receive_data(adapter, 0);
1504 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) != 0) && (adapter->dmaq1.bus_addr != 0)) {
1505 write_reg_dw(adapter, 0x000, adapter->dmaq1.bus_addr);
1506 write_reg_dw(adapter, 0x00c, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1508 adapter->dma_status = adapter->dma_status & ~0x00000001;
1511 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) != 0) && (adapter->dmaq2.bus_addr != 0)) {
1512 write_reg_dw(adapter, 0x010, adapter->dmaq2.bus_addr);
1514 adapter->dma_status = adapter->dma_status & ~0x00000002;
1519 static void open_stream(struct adapter *adapter, u16 pid)
1523 ++adapter->capturing;
1525 filter_enable_mask_filter(adapter, 1);
1527 add_pid(adapter, pid);
1529 dprintk("%s: adapter->dma_status=%x\n", __FUNCTION__, adapter->dma_status);
1531 if ((adapter->dma_status & 7) != 7) {
1534 if (((adapter->dma_status & 0x10000000) != 0) && ((adapter->dma_status & 1) == 0)) {
1535 dma_mask = dma_mask | 1;
1537 adapter->dmaq1.head = 0;
1538 adapter->dmaq1.tail = 0;
1540 memset(adapter->dmaq1.buffer, 0, adapter->dmaq1.buffer_size);
1543 if (((adapter->dma_status & 0x20000000) != 0) && ((adapter->dma_status & 2) == 0)) {
1544 dma_mask = dma_mask | 2;
1546 adapter->dmaq2.head = 0;
1547 adapter->dmaq2.tail = 0;
1550 if (dma_mask != 0) {
1551 irq_dma_enable_disable_irq(adapter, 1);
1553 dma_start_stop(adapter, dma_mask, 1);
1558 static void close_stream(struct adapter *adapter, u16 pid)
1560 if (adapter->capturing > 0)
1561 --adapter->capturing;
1563 dprintk("%s: dma_status=%x\n", __FUNCTION__, adapter->dma_status);
1565 if (adapter->capturing == 0) {
1568 if ((adapter->dma_status & 1) != 0)
1569 dma_mask = dma_mask | 0x00000001;
1570 if ((adapter->dma_status & 2) != 0)
1571 dma_mask = dma_mask | 0x00000002;
1573 if (dma_mask != 0) {
1574 dma_start_stop(adapter, dma_mask, 0);
1577 remove_pid(adapter, pid);
1580 static void interrupt_service_dma1(struct adapter *adapter)
1582 struct dvb_demux *dvbdmx = &adapter->demux;
1584 int n_cur_dma_counter;
1585 u32 n_num_bytes_parsed;
1586 u32 n_num_new_bytes_transferred;
1587 u32 dw_default_packet_size = 188;
1588 u8 gb_tmp_buffer[188];
1589 u8 *pb_dma_buf_cur_pos;
1591 n_cur_dma_counter = readl(adapter->io_mem + 0x008) - adapter->dmaq1.bus_addr;
1592 n_cur_dma_counter = (n_cur_dma_counter / dw_default_packet_size) * dw_default_packet_size;
1594 if ((n_cur_dma_counter < 0) || (n_cur_dma_counter > adapter->dmaq1.buffer_size)) {
1595 dprintk("%s: dma counter outside dma buffer\n", __FUNCTION__);
1599 adapter->dmaq1.head = n_cur_dma_counter;
1601 if (adapter->dmaq1.tail <= n_cur_dma_counter) {
1602 n_num_new_bytes_transferred = n_cur_dma_counter - adapter->dmaq1.tail;
1606 n_num_new_bytes_transferred = (adapter->dmaq1.buffer_size - adapter->dmaq1.tail) + n_cur_dma_counter;
1609 ddprintk("%s: n_cur_dma_counter = %d\n", __FUNCTION__, n_cur_dma_counter);
1610 ddprintk("%s: dmaq1.tail = %d\n", __FUNCTION__, adapter->dmaq1.tail);
1611 ddprintk("%s: bytes_transferred = %d\n", __FUNCTION__, n_num_new_bytes_transferred);
1613 if (n_num_new_bytes_transferred < dw_default_packet_size)
1616 n_num_bytes_parsed = 0;
1618 while (n_num_bytes_parsed < n_num_new_bytes_transferred) {
1619 pb_dma_buf_cur_pos = adapter->dmaq1.buffer + adapter->dmaq1.tail;
1621 if (adapter->dmaq1.buffer + adapter->dmaq1.buffer_size < adapter->dmaq1.buffer + adapter->dmaq1.tail + 188) {
1622 memcpy(gb_tmp_buffer, adapter->dmaq1.buffer + adapter->dmaq1.tail,
1623 adapter->dmaq1.buffer_size - adapter->dmaq1.tail);
1624 memcpy(gb_tmp_buffer + (adapter->dmaq1.buffer_size - adapter->dmaq1.tail), adapter->dmaq1.buffer,
1625 (188 - (adapter->dmaq1.buffer_size - adapter->dmaq1.tail)));
1627 pb_dma_buf_cur_pos = gb_tmp_buffer;
1630 if (adapter->capturing != 0) {
1631 dvb_dmx_swfilter_packets(dvbdmx, pb_dma_buf_cur_pos, dw_default_packet_size / 188);
1634 n_num_bytes_parsed = n_num_bytes_parsed + dw_default_packet_size;
1636 adapter->dmaq1.tail = adapter->dmaq1.tail + dw_default_packet_size;
1638 if (adapter->dmaq1.tail >= adapter->dmaq1.buffer_size)
1639 adapter->dmaq1.tail = adapter->dmaq1.tail - adapter->dmaq1.buffer_size;
1643 static void interrupt_service_dma2(struct adapter *adapter)
1645 printk("%s:\n", __FUNCTION__);
1648 static irqreturn_t isr(int irq, void *dev_id, struct pt_regs *regs)
1650 struct adapter *tmp = dev_id;
1654 ddprintk("%s:\n", __FUNCTION__);
1656 spin_lock_irq(&tmp->lock);
1658 if (0 == ((value = read_reg_dw(tmp, 0x20c)) & 0x0f)) {
1659 spin_unlock_irq(&tmp->lock);
1663 while (value != 0) {
1664 if ((value & 0x03) != 0)
1665 interrupt_service_dma1(tmp);
1666 if ((value & 0x0c) != 0)
1667 interrupt_service_dma2(tmp);
1668 value = read_reg_dw(tmp, 0x20c) & 0x0f;
1671 spin_unlock_irq(&tmp->lock);
1675 static void init_dma_queue(struct adapter *adapter)
1677 dma_addr_t dma_addr;
1679 if (adapter->dmaq1.buffer != 0)
1682 adapter->dmaq1.head = 0;
1683 adapter->dmaq1.tail = 0;
1684 adapter->dmaq1.buffer = NULL;
1686 adapter->dmaq1.buffer = pci_alloc_consistent(adapter->pdev, SIZE_OF_BUF_DMA1 + 0x80, &dma_addr);
1688 if (adapter->dmaq1.buffer != 0) {
1689 memset(adapter->dmaq1.buffer, 0, SIZE_OF_BUF_DMA1);
1691 adapter->dmaq1.bus_addr = dma_addr;
1692 adapter->dmaq1.buffer_size = SIZE_OF_BUF_DMA1;
1694 dma_init_dma(adapter, 0);
1696 adapter->dma_status = adapter->dma_status | 0x10000000;
1698 ddprintk("%s: allocated dma buffer at 0x%p, length=%d\n", __FUNCTION__, adapter->dmaq1.buffer, SIZE_OF_BUF_DMA1);
1702 adapter->dma_status = adapter->dma_status & ~0x10000000;
1705 if (adapter->dmaq2.buffer != 0)
1708 adapter->dmaq2.head = 0;
1709 adapter->dmaq2.tail = 0;
1710 adapter->dmaq2.buffer = NULL;
1712 adapter->dmaq2.buffer = pci_alloc_consistent(adapter->pdev, SIZE_OF_BUF_DMA2 + 0x80, &dma_addr);
1714 if (adapter->dmaq2.buffer != 0) {
1715 memset(adapter->dmaq2.buffer, 0, SIZE_OF_BUF_DMA2);
1717 adapter->dmaq2.bus_addr = dma_addr;
1718 adapter->dmaq2.buffer_size = SIZE_OF_BUF_DMA2;
1720 dma_init_dma(adapter, 1);
1722 adapter->dma_status = adapter->dma_status | 0x20000000;
1724 ddprintk("%s: allocated dma buffer at 0x%p, length=%d\n", __FUNCTION__, adapter->dmaq2.buffer, (int) SIZE_OF_BUF_DMA2);
1728 adapter->dma_status = adapter->dma_status & ~0x20000000;
1732 static void free_dma_queue(struct adapter *adapter)
1734 if (adapter->dmaq1.buffer != 0) {
1735 pci_free_consistent(adapter->pdev, SIZE_OF_BUF_DMA1 + 0x80, adapter->dmaq1.buffer, adapter->dmaq1.bus_addr);
1737 adapter->dmaq1.bus_addr = 0;
1738 adapter->dmaq1.head = 0;
1739 adapter->dmaq1.tail = 0;
1740 adapter->dmaq1.buffer_size = 0;
1741 adapter->dmaq1.buffer = NULL;
1744 if (adapter->dmaq2.buffer != 0) {
1745 pci_free_consistent(adapter->pdev, SIZE_OF_BUF_DMA2 + 0x80, adapter->dmaq2.buffer, adapter->dmaq2.bus_addr);
1747 adapter->dmaq2.bus_addr = 0;
1748 adapter->dmaq2.head = 0;
1749 adapter->dmaq2.tail = 0;
1750 adapter->dmaq2.buffer_size = 0;
1751 adapter->dmaq2.buffer = NULL;
1755 static void free_adapter_object(struct adapter *adapter)
1757 dprintk("%s:\n", __FUNCTION__);
1759 close_stream(adapter, 0);
1761 if (adapter->irq != 0)
1762 free_irq(adapter->irq, adapter);
1764 free_dma_queue(adapter);
1766 if (adapter->io_mem != 0)
1767 iounmap((void *) adapter->io_mem);
1773 static struct pci_driver skystar2_pci_driver;
1775 static int claim_adapter(struct adapter *adapter)
1777 struct pci_dev *pdev = adapter->pdev;
1781 if (!request_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1), skystar2_pci_driver.name))
1784 if (!request_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0), skystar2_pci_driver.name))
1787 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &adapter->card_revision);
1789 dprintk("%s: card revision %x \n", __FUNCTION__, adapter->card_revision);
1791 if (pci_enable_device(pdev))
1794 pci_read_config_word(pdev, 4, &var);
1797 pci_set_master(pdev);
1799 adapter->io_port = pdev->resource[1].start;
1801 adapter->io_mem = (unsigned long) ioremap(pdev->resource[0].start, 0x800);
1803 if (adapter->io_mem == 0) {
1804 dprintk("%s: can not map io memory\n", __FUNCTION__);
1809 dprintk("%s: io memory maped at %lx\n", __FUNCTION__, adapter->io_mem);
1815 static int sll_reset_flexcop(struct adapter *adapter)
1817 write_reg_dw(adapter, 0x208, 0);
1818 write_reg_dw(adapter, 0x210, 0xb2ff);
1824 static void decide_how_many_hw_filters(struct adapter *adapter)
1827 int mod_option_hw_filters;
1829 // FlexCop IIb & III have 6+32 hw filters
1830 // FlexCop II has 6 hw filters, every other should have at least 6
1831 switch (adapter->b2c2_revision) {
1835 case 0xc3: /* IIB */
1836 hw_filters = 6 + 32;
1838 case 0xc0: /* III */
1839 hw_filters = 6 + 32;
1845 printk("%s: the chip has %i hardware filters", __FILE__, hw_filters);
1847 mod_option_hw_filters = 0;
1848 if (enable_hw_filters >= 1)
1849 mod_option_hw_filters += 6;
1850 if (enable_hw_filters >= 2)
1851 mod_option_hw_filters += 32;
1853 if (mod_option_hw_filters >= hw_filters) {
1854 adapter->useable_hw_filters = hw_filters;
1856 adapter->useable_hw_filters = mod_option_hw_filters;
1857 printk(", but only %d will be used because of module option", mod_option_hw_filters);
1860 dprintk("%s: useable_hardware_filters set to %i\n", __FILE__, adapter->useable_hw_filters);
1863 static int driver_initialize(struct pci_dev *pdev)
1865 struct adapter *adapter;
1868 if (!(adapter = kmalloc(sizeof(struct adapter), GFP_KERNEL))) {
1869 dprintk("%s: out of memory!\n", __FUNCTION__);
1874 memset(adapter, 0, sizeof(struct adapter));
1876 pci_set_drvdata(pdev,adapter);
1878 adapter->pdev = pdev;
1879 adapter->irq = pdev->irq;
1881 if ((claim_adapter(adapter)) != 1) {
1882 free_adapter_object(adapter);
1887 irq_dma_enable_disable_irq(adapter, 0);
1889 if (request_irq(pdev->irq, isr, 0x4000000, "Skystar2", adapter) != 0) {
1890 dprintk("%s: unable to allocate irq=%d !\n", __FUNCTION__, pdev->irq);
1892 free_adapter_object(adapter);
1897 read_reg_dw(adapter, 0x208);
1898 write_reg_dw(adapter, 0x208, 0);
1899 write_reg_dw(adapter, 0x210, 0xb2ff);
1900 write_reg_dw(adapter, 0x208, 0x40);
1902 init_dma_queue(adapter);
1904 if ((adapter->dma_status & 0x30000000) == 0) {
1905 free_adapter_object(adapter);
1910 adapter->b2c2_revision = (read_reg_dw(adapter, 0x204) >> 0x18);
1912 switch (adapter->b2c2_revision) {
1914 printk("%s: FlexCopII(rev.130) chip found\n", __FILE__);
1917 printk("%s: FlexCopIIB(rev.195) chip found\n", __FILE__);
1920 printk("%s: FlexCopIII(rev.192) chip found\n", __FILE__);
1923 printk("%s: The revision of the FlexCop chip on your card is %d\n", __FILE__, adapter->b2c2_revision);
1924 printk("%s: This driver works only with FlexCopII(rev.130), FlexCopIIB(rev.195) and FlexCopIII(rev.192).\n", __FILE__);
1925 free_adapter_object(adapter);
1926 pci_set_drvdata(pdev, NULL);
1927 release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
1928 release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
1932 decide_how_many_hw_filters(adapter);
1936 tmp = read_reg_dw(adapter, 0x204);
1938 write_reg_dw(adapter, 0x204, 0);
1941 write_reg_dw(adapter, 0x204, tmp);
1944 tmp = read_reg_dw(adapter, 0x308);
1945 write_reg_dw(adapter, 0x308, 0x4000 | tmp);
1947 adapter->dw_sram_type = 0x10000;
1949 sll_detect_sram_size(adapter);
1951 dprintk("%s sram length = %d, sram type= %x\n", __FUNCTION__, sram_length(adapter), adapter->dw_sram_type);
1953 sram_set_media_dest(adapter, 1);
1954 sram_set_net_dest(adapter, 1);
1956 ctrl_enable_smc(adapter, 0);
1958 sram_set_cai_dest(adapter, 2);
1959 sram_set_cao_dest(adapter, 2);
1961 dma_enable_disable_irq(adapter, 1, 0, 0);
1963 if (eeprom_get_mac_addr(adapter, 0, adapter->mac_addr) != 0) {
1964 printk("%s MAC address = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x \n", __FUNCTION__, adapter->mac_addr[0],
1965 adapter->mac_addr[1], adapter->mac_addr[2], adapter->mac_addr[3], adapter->mac_addr[4], adapter->mac_addr[5],
1966 adapter->mac_addr[6], adapter->mac_addr[7]
1969 ca_set_mac_dst_addr_filter(adapter, adapter->mac_addr);
1970 ctrl_enable_mac(adapter, 1);
1973 adapter->lock = SPIN_LOCK_UNLOCKED;
1978 static void driver_halt(struct pci_dev *pdev)
1980 struct adapter *adapter;
1982 adapter = pci_get_drvdata(pdev);
1984 irq_dma_enable_disable_irq(adapter, 0);
1986 ctrl_enable_receive_data(adapter, 0);
1988 free_adapter_object(adapter);
1990 pci_set_drvdata(pdev, NULL);
1992 release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
1994 release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
1997 static int dvb_start_feed(struct dvb_demux_feed *dvbdmxfeed)
1999 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
2000 struct adapter *adapter = (struct adapter *) dvbdmx->priv;
2002 dprintk("%s: PID=%d, type=%d\n", __FUNCTION__, dvbdmxfeed->pid, dvbdmxfeed->type);
2004 open_stream(adapter, dvbdmxfeed->pid);
2009 static int dvb_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
2011 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
2012 struct adapter *adapter = (struct adapter *) dvbdmx->priv;
2014 dprintk("%s: PID=%d, type=%d\n", __FUNCTION__, dvbdmxfeed->pid, dvbdmxfeed->type);
2016 close_stream(adapter, dvbdmxfeed->pid);
2022 static void set_tuner_tone(struct adapter *adapter, u8 tone)
2024 u16 wz_half_period_for_45_mhz[] = { 0x01ff, 0x0154, 0x00ff, 0x00cc };
2027 dprintk("%s: %u\n", __FUNCTION__, tone);
2031 ax = wz_half_period_for_45_mhz[0];
2034 ax = wz_half_period_for_45_mhz[1];
2037 ax = wz_half_period_for_45_mhz[2];
2040 ax = wz_half_period_for_45_mhz[3];
2048 write_reg_dw(adapter, 0x200, ((ax << 0x0f) + (ax & 0x7fff)) | 0x40000000);
2052 write_reg_dw(adapter, 0x200, 0x40ff8000);
2056 static void set_tuner_polarity(struct adapter *adapter, u8 polarity)
2060 dprintk("%s : polarity = %u \n", __FUNCTION__, polarity);
2062 var = read_reg_dw(adapter, 0x204);
2064 if (polarity == 0) {
2065 dprintk("%s: LNB power off\n", __FUNCTION__);
2069 if (polarity == 1) {
2074 if (polarity == 2) {
2079 write_reg_dw(adapter, 0x204, var);
2082 static void diseqc_send_bit(struct adapter *adapter, int data)
2084 set_tuner_tone(adapter, 1);
2085 udelay(data ? 500 : 1000);
2086 set_tuner_tone(adapter, 0);
2087 udelay(data ? 1000 : 500);
2091 static void diseqc_send_byte(struct adapter *adapter, int data)
2095 for (i = 7; i >= 0; i--) {
2096 d = (data >> i) & 1;
2098 diseqc_send_bit(adapter, d);
2101 diseqc_send_bit(adapter, par);
2105 static int send_diseqc_msg(struct adapter *adapter, int len, u8 *msg, unsigned long burst)
2109 set_tuner_tone(adapter, 0);
2112 for (i = 0; i < len; i++)
2113 diseqc_send_byte(adapter, msg[i]);
2119 diseqc_send_byte(adapter, 0xff);
2121 set_tuner_tone(adapter, 1);
2123 set_tuner_tone(adapter, 0);
2132 int soft_diseqc(struct adapter *adapter, unsigned int cmd, void *arg)
2136 switch ((fe_sec_tone_mode_t) arg) {
2138 set_tuner_tone(adapter, 1);
2141 set_tuner_tone(adapter, 0);
2148 case FE_DISEQC_SEND_MASTER_CMD:
2150 struct dvb_diseqc_master_cmd *cmd = arg;
2152 send_diseqc_msg(adapter, cmd->msg_len, cmd->msg, 0);
2156 case FE_DISEQC_SEND_BURST:
2157 send_diseqc_msg(adapter, 0, NULL, (unsigned long) arg);
2167 static int flexcop_diseqc_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
2169 struct adapter *adapter = fe->before_after_data;
2171 struct dvb_frontend_info info;
2173 fe->ioctl(fe, FE_GET_INFO, &info);
2175 // we must use different DiSEqC hw
2177 if (strcmp(info.name, "Zarlink MT312") == 0) {
2178 //VP310 using mt312 driver for tuning only: diseqc not wired
2180 if (!soft_diseqc(adapter, cmd, arg))
2187 dprintk("%s: FE_SLEEP\n", __FUNCTION__);
2189 set_tuner_polarity(adapter, 0);
2191 // return -EOPNOTSUPP, to make DVB core also send "FE_SLEEP" command to frontend.
2195 case FE_SET_VOLTAGE:
2197 dprintk("%s: FE_SET_VOLTAGE\n", __FUNCTION__);
2199 switch ((fe_sec_voltage_t) arg) {
2200 case SEC_VOLTAGE_13:
2202 dprintk("%s: SEC_VOLTAGE_13, %x\n", __FUNCTION__, SEC_VOLTAGE_13);
2204 set_tuner_polarity(adapter, 1);
2208 case SEC_VOLTAGE_18:
2210 dprintk("%s: SEC_VOLTAGE_18, %x\n", __FUNCTION__, SEC_VOLTAGE_18);
2212 set_tuner_polarity(adapter, 2);
2231 static int skystar2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2233 struct adapter *adapter;
2234 struct dvb_adapter *dvb_adapter;
2235 struct dvb_demux *dvbdemux;
2242 if (driver_initialize(pdev) != 0)
2245 dvb_register_adapter(&dvb_adapter, skystar2_pci_driver.name, THIS_MODULE);
2247 if (dvb_adapter == NULL) {
2248 printk("%s: Error registering DVB adapter\n", __FUNCTION__);
2255 adapter = (struct adapter *) pci_get_drvdata(pdev);
2257 adapter->dvb_adapter = dvb_adapter;
2259 init_MUTEX(&adapter->i2c_sem);
2261 adapter->i2c_bus = dvb_register_i2c_bus(master_xfer, adapter, adapter->dvb_adapter, 0);
2263 if (!adapter->i2c_bus)
2266 dvb_add_frontend_ioctls(adapter->dvb_adapter, flexcop_diseqc_ioctl, NULL, adapter);
2268 dvbdemux = &adapter->demux;
2270 dvbdemux->priv = (void *) adapter;
2271 dvbdemux->filternum = N_PID_SLOTS;
2272 dvbdemux->feednum = N_PID_SLOTS;
2273 dvbdemux->start_feed = dvb_start_feed;
2274 dvbdemux->stop_feed = dvb_stop_feed;
2275 dvbdemux->write_to_decoder = NULL;
2276 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
2278 dvb_dmx_init(&adapter->demux);
2280 adapter->hw_frontend.source = DMX_FRONTEND_0;
2282 adapter->dmxdev.filternum = N_PID_SLOTS;
2283 adapter->dmxdev.demux = &dvbdemux->dmx;
2284 adapter->dmxdev.capabilities = 0;
2286 dvb_dmxdev_init(&adapter->dmxdev, adapter->dvb_adapter);
2288 ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2292 adapter->mem_frontend.source = DMX_MEMORY_FE;
2294 ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &adapter->mem_frontend);
2298 ret = dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2302 dvb_net_init(adapter->dvb_adapter, &adapter->dvbnet, &dvbdemux->dmx);
2306 static void skystar2_remove(struct pci_dev *pdev)
2308 struct adapter *adapter;
2309 struct dvb_demux *dvbdemux;
2314 adapter = pci_get_drvdata(pdev);
2316 if (adapter != NULL) {
2317 dvb_net_release(&adapter->dvbnet);
2318 dvbdemux = &adapter->demux;
2320 dvbdemux->dmx.close(&dvbdemux->dmx);
2321 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2322 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &adapter->mem_frontend);
2324 dvb_dmxdev_release(&adapter->dmxdev);
2325 dvb_dmx_release(&adapter->demux);
2327 if (adapter->dvb_adapter != NULL) {
2328 dvb_remove_frontend_ioctls(adapter->dvb_adapter, flexcop_diseqc_ioctl, NULL);
2330 if (adapter->i2c_bus != NULL)
2331 dvb_unregister_i2c_bus(master_xfer, adapter->i2c_bus->adapter, adapter->i2c_bus->id);
2333 dvb_unregister_adapter(adapter->dvb_adapter);
2339 static struct pci_device_id skystar2_pci_tbl[] = {
2340 {0x000013d0, 0x00002103, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000},
2341 {0x000013d0, 0x00002200, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000}, //FCIII
2345 MODULE_DEVICE_TABLE(pci, skystar2_pci_tbl);
2347 static struct pci_driver skystar2_pci_driver = {
2349 .id_table = skystar2_pci_tbl,
2350 .probe = skystar2_probe,
2351 .remove = skystar2_remove,
2354 static int skystar2_init(void)
2356 return pci_module_init(&skystar2_pci_driver);
2359 static void skystar2_cleanup(void)
2361 pci_unregister_driver(&skystar2_pci_driver);
2364 module_init(skystar2_init);
2365 module_exit(skystar2_cleanup);
2367 MODULE_PARM(debug, "i");
2368 MODULE_PARM_DESC(debug, "enable verbose debug messages: supported values: 1 and 2");
2369 MODULE_PARM(enable_hw_filters, "i");
2370 MODULE_PARM_DESC(enable_hw_filters, "enable hardware filters: supported values: 0 (none), 1, 2");
2372 MODULE_DESCRIPTION("Technisat SkyStar2 DVB PCI Driver");
2373 MODULE_LICENSE("GPL");