2 * Frontend driver for mobile DVB-T demodulator DiBcom 3000-MB
3 * DiBcom (http://www.dibcom.fr/)
5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
7 * based on GPL code from DibCom, which has
9 * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation, version 2.
17 * Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18 * sources, on which this driver (and the dvb-dibusb) are based.
20 * see Documentation/dvb/README.dibusb for more information
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/version.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
32 #include "dib3000-common.h"
33 #include "dib3000mb_priv.h"
36 /* Version information */
37 #define DRIVER_VERSION "0.1"
38 #define DRIVER_DESC "DiBcom 3000-MB DVB-T demodulator driver"
39 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
41 #ifdef CONFIG_DVB_DIBCOM_DEBUG
43 module_param(debug, int, 0644);
44 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
46 #define deb_info(args...) dprintk(0x01,args)
47 #define deb_xfer(args...) dprintk(0x02,args)
48 #define deb_setf(args...) dprintk(0x04,args)
49 #define deb_getf(args...) dprintk(0x08,args)
51 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr);
53 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
54 struct dvb_frontend_parameters *fep);
56 static int dib3000mb_set_frontend(struct dvb_frontend* fe,
57 struct dvb_frontend_parameters *fep, int tuner)
59 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
60 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
61 fe_code_rate_t fe_cr = FEC_NONE;
65 dib3000mb_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));
66 state->config.pll_set(fe, fep, NULL);
67 dib3000mb_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));
69 deb_setf("bandwidth: ");
70 switch (ofdm->bandwidth) {
73 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
74 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
78 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[1]);
79 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_7mhz);
83 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[0]);
84 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_6mhz);
89 err("unkown bandwidth value.");
93 wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
95 deb_setf("transmission mode: ");
96 switch (ofdm->transmission_mode) {
97 case TRANSMISSION_MODE_2K:
99 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
101 case TRANSMISSION_MODE_8K:
103 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
105 case TRANSMISSION_MODE_AUTO:
113 switch (ofdm->guard_interval) {
114 case GUARD_INTERVAL_1_32:
116 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
118 case GUARD_INTERVAL_1_16:
120 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
122 case GUARD_INTERVAL_1_8:
124 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
126 case GUARD_INTERVAL_1_4:
128 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
130 case GUARD_INTERVAL_AUTO:
137 deb_setf("inversion: ");
138 switch (fep->inversion) {
141 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
148 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
154 deb_setf("constellation: ");
155 switch (ofdm->constellation) {
158 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
162 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
166 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
173 deb_setf("hierachy: ");
174 switch (ofdm->hierarchy_information) {
179 deb_setf("alpha=1\n");
180 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
183 deb_setf("alpha=2\n");
184 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
187 deb_setf("alpha=4\n");
188 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
191 deb_setf("alpha=auto\n");
197 deb_setf("hierarchy: ");
198 if (ofdm->hierarchy_information == HIERARCHY_NONE) {
200 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
201 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
202 fe_cr = ofdm->code_rate_HP;
203 } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
205 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
206 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
207 fe_cr = ofdm->code_rate_LP;
213 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
217 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
221 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
225 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
229 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
242 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
243 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
244 [fep->inversion == INVERSION_AUTO];
246 deb_setf("seq? %d\n",seq);
248 wr(DIB3000MB_REG_SEQ,seq);
250 wr(DIB3000MB_REG_ISI,seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
252 if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
253 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
254 wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_2K_1_8);
256 wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_DEFAULT);
259 wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_2K);
261 wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_DEFAULT);
264 wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_OFF);
265 wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
266 wr(DIB3000MB_REG_MOBILE_MODE,DIB3000MB_MOBILE_MODE_OFF);
268 wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_high);
270 wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_ACTIVATE);
272 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AGC+DIB3000MB_RESTART_CTRL);
273 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
275 /* wait for AGC lock */
278 wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
280 /* something has to be auto searched */
281 if (ofdm->constellation == QAM_AUTO ||
282 ofdm->hierarchy_information == HIERARCHY_AUTO ||
284 fep->inversion == INVERSION_AUTO) {
287 deb_setf("autosearch enabled.\n");
289 wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
291 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AUTO_SEARCH);
292 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
294 while ((search_state =
295 dib3000_search_status(
296 rd(DIB3000MB_REG_AS_IRQ_PENDING),
297 rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
300 deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
302 if (search_state == 1) {
303 struct dvb_frontend_parameters feps;
304 if (dib3000mb_get_frontend(fe, &feps) == 0) {
305 deb_setf("reading tuning data from frontend succeeded.\n");
306 return dib3000mb_set_frontend(fe, &feps, 0);
311 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_CTRL);
312 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
318 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
320 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
322 wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_UP);
324 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
326 wr(DIB3000MB_REG_RESET_DEVICE,DIB3000MB_RESET_DEVICE);
327 wr(DIB3000MB_REG_RESET_DEVICE,DIB3000MB_RESET_DEVICE_RST);
329 wr(DIB3000MB_REG_CLOCK,DIB3000MB_CLOCK_DEFAULT);
331 wr(DIB3000MB_REG_ELECT_OUT_MODE,DIB3000MB_ELECT_OUT_MODE_ON);
333 wr(DIB3000MB_REG_DDS_FREQ_MSB,DIB3000MB_DDS_FREQ_MSB);
334 wr(DIB3000MB_REG_DDS_FREQ_LSB,DIB3000MB_DDS_FREQ_LSB);
336 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
338 wr_foreach(dib3000mb_reg_impulse_noise,
339 dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
341 wr_foreach(dib3000mb_reg_agc_gain,dib3000mb_default_agc_gain);
343 wr(DIB3000MB_REG_PHASE_NOISE,DIB3000MB_PHASE_NOISE_DEFAULT);
345 wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
347 wr_foreach(dib3000mb_reg_lock_duration,dib3000mb_default_lock_duration);
349 wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
351 wr(DIB3000MB_REG_LOCK0_MASK,DIB3000MB_LOCK0_DEFAULT);
352 wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
353 wr(DIB3000MB_REG_LOCK2_MASK,DIB3000MB_LOCK2_DEFAULT);
354 wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
356 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
358 wr(DIB3000MB_REG_UNK_68,DIB3000MB_UNK_68);
359 wr(DIB3000MB_REG_UNK_69,DIB3000MB_UNK_69);
360 wr(DIB3000MB_REG_UNK_71,DIB3000MB_UNK_71);
361 wr(DIB3000MB_REG_UNK_77,DIB3000MB_UNK_77);
362 wr(DIB3000MB_REG_UNK_78,DIB3000MB_UNK_78);
363 wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
364 wr(DIB3000MB_REG_UNK_92,DIB3000MB_UNK_92);
365 wr(DIB3000MB_REG_UNK_96,DIB3000MB_UNK_96);
366 wr(DIB3000MB_REG_UNK_97,DIB3000MB_UNK_97);
367 wr(DIB3000MB_REG_UNK_106,DIB3000MB_UNK_106);
368 wr(DIB3000MB_REG_UNK_107,DIB3000MB_UNK_107);
369 wr(DIB3000MB_REG_UNK_108,DIB3000MB_UNK_108);
370 wr(DIB3000MB_REG_UNK_122,DIB3000MB_UNK_122);
371 wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
372 wr(DIB3000MB_REG_BERLEN,DIB3000MB_BERLEN_DEFAULT);
374 wr_foreach(dib3000mb_reg_filter_coeffs,dib3000mb_filter_coeffs);
376 wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_ON);
377 wr(DIB3000MB_REG_MULTI_DEMOD_MSB,DIB3000MB_MULTI_DEMOD_MSB);
378 wr(DIB3000MB_REG_MULTI_DEMOD_LSB,DIB3000MB_MULTI_DEMOD_LSB);
380 wr(DIB3000MB_REG_OUTPUT_MODE,DIB3000MB_OUTPUT_MODE_SLAVE);
382 wr(DIB3000MB_REG_FIFO_142,DIB3000MB_FIFO_142);
383 wr(DIB3000MB_REG_MPEG2_OUT_MODE,DIB3000MB_MPEG2_OUT_MODE_188);
384 wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
385 wr(DIB3000MB_REG_FIFO,DIB3000MB_FIFO_INHIBIT);
386 wr(DIB3000MB_REG_FIFO_146,DIB3000MB_FIFO_146);
387 wr(DIB3000MB_REG_FIFO_147,DIB3000MB_FIFO_147);
389 wr(DIB3000MB_REG_DATA_IN_DIVERSITY,DIB3000MB_DATA_DIVERSITY_IN_OFF);
391 if (state->config.pll_init) {
392 dib3000mb_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));
393 state->config.pll_init(fe,NULL);
394 dib3000mb_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));
400 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
401 struct dvb_frontend_parameters *fep)
403 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
404 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
407 int inv_test1,inv_test2;
408 u32 dds_val, threshold = 0x800000;
410 if (!rd(DIB3000MB_REG_TPS_LOCK))
413 dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
414 deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
415 if (dds_val < threshold)
417 else if (dds_val == threshold)
422 dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
423 deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
424 if (dds_val < threshold)
426 else if (dds_val == threshold)
432 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
433 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
434 INVERSION_ON : INVERSION_OFF;
436 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
438 switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
439 case DIB3000_CONSTELLATION_QPSK:
441 ofdm->constellation = QPSK;
443 case DIB3000_CONSTELLATION_16QAM:
445 ofdm->constellation = QAM_16;
447 case DIB3000_CONSTELLATION_64QAM:
449 ofdm->constellation = QAM_64;
452 err("Unexpected constellation returned by TPS (%d)", tps_val);
455 deb_getf("TPS: %d\n", tps_val);
457 if (rd(DIB3000MB_REG_TPS_HRCH)) {
458 deb_getf("HRCH ON\n");
459 cr = &ofdm->code_rate_LP;
460 ofdm->code_rate_HP = FEC_NONE;
461 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
462 case DIB3000_ALPHA_0:
463 deb_getf("HIERARCHY_NONE ");
464 ofdm->hierarchy_information = HIERARCHY_NONE;
466 case DIB3000_ALPHA_1:
467 deb_getf("HIERARCHY_1 ");
468 ofdm->hierarchy_information = HIERARCHY_1;
470 case DIB3000_ALPHA_2:
471 deb_getf("HIERARCHY_2 ");
472 ofdm->hierarchy_information = HIERARCHY_2;
474 case DIB3000_ALPHA_4:
475 deb_getf("HIERARCHY_4 ");
476 ofdm->hierarchy_information = HIERARCHY_4;
479 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
482 deb_getf("TPS: %d\n", tps_val);
484 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
486 deb_getf("HRCH OFF\n");
487 cr = &ofdm->code_rate_HP;
488 ofdm->code_rate_LP = FEC_NONE;
489 ofdm->hierarchy_information = HIERARCHY_NONE;
491 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
495 case DIB3000_FEC_1_2:
496 deb_getf("FEC_1_2 ");
499 case DIB3000_FEC_2_3:
500 deb_getf("FEC_2_3 ");
503 case DIB3000_FEC_3_4:
504 deb_getf("FEC_3_4 ");
507 case DIB3000_FEC_5_6:
508 deb_getf("FEC_5_6 ");
511 case DIB3000_FEC_7_8:
512 deb_getf("FEC_7_8 ");
516 err("Unexpected FEC returned by TPS (%d)", tps_val);
519 deb_getf("TPS: %d\n",tps_val);
521 switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
522 case DIB3000_GUARD_TIME_1_32:
523 deb_getf("GUARD_INTERVAL_1_32 ");
524 ofdm->guard_interval = GUARD_INTERVAL_1_32;
526 case DIB3000_GUARD_TIME_1_16:
527 deb_getf("GUARD_INTERVAL_1_16 ");
528 ofdm->guard_interval = GUARD_INTERVAL_1_16;
530 case DIB3000_GUARD_TIME_1_8:
531 deb_getf("GUARD_INTERVAL_1_8 ");
532 ofdm->guard_interval = GUARD_INTERVAL_1_8;
534 case DIB3000_GUARD_TIME_1_4:
535 deb_getf("GUARD_INTERVAL_1_4 ");
536 ofdm->guard_interval = GUARD_INTERVAL_1_4;
539 err("Unexpected Guard Time returned by TPS (%d)", tps_val);
542 deb_getf("TPS: %d\n", tps_val);
544 switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
545 case DIB3000_TRANSMISSION_MODE_2K:
546 deb_getf("TRANSMISSION_MODE_2K ");
547 ofdm->transmission_mode = TRANSMISSION_MODE_2K;
549 case DIB3000_TRANSMISSION_MODE_8K:
550 deb_getf("TRANSMISSION_MODE_8K ");
551 ofdm->transmission_mode = TRANSMISSION_MODE_8K;
554 err("unexpected transmission mode return by TPS (%d)", tps_val);
557 deb_getf("TPS: %d\n", tps_val);
562 static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
564 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
568 if (rd(DIB3000MB_REG_AGC_LOCK))
569 *stat |= FE_HAS_SIGNAL;
570 if (rd(DIB3000MB_REG_CARRIER_LOCK))
571 *stat |= FE_HAS_CARRIER;
572 if (rd(DIB3000MB_REG_VIT_LCK))
573 *stat |= FE_HAS_VITERBI;
574 if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
575 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
577 deb_info("actual status is %2x\n",*stat);
579 deb_getf("tps %x %x %x %x %x\n",
580 rd(DIB3000MB_REG_TPS_1),
581 rd(DIB3000MB_REG_TPS_2),
582 rd(DIB3000MB_REG_TPS_3),
583 rd(DIB3000MB_REG_TPS_4),
584 rd(DIB3000MB_REG_TPS_5));
586 deb_info("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
587 rd(DIB3000MB_REG_TPS_LOCK),
588 rd(DIB3000MB_REG_TPS_QAM),
589 rd(DIB3000MB_REG_TPS_HRCH),
590 rd(DIB3000MB_REG_TPS_VIT_ALPHA),
591 rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
592 rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
593 rd(DIB3000MB_REG_TPS_GUARD_TIME),
594 rd(DIB3000MB_REG_TPS_FFT),
595 rd(DIB3000MB_REG_TPS_CELL_ID));
597 //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
601 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
603 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
605 *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB) );
610 * signal strength is measured with dBm (power compared to mW)
611 * the standard range is -90dBm(low power) to -10 dBm (strong power),
612 * but the calibration is done for -100 dBm to 0dBm
615 #define DIB3000MB_AGC_REF_dBm -14
616 #define DIB3000MB_GAIN_SLOPE_dBm 100
617 #define DIB3000MB_GAIN_DELTA_dBm -2
618 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
620 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
623 u16 sigpow = rd(DIB3000MB_REG_SIGNAL_POWER),
624 n_agc_power = rd(DIB3000MB_REG_AGC_POWER),
625 rf_power = rd(DIB3000MB_REG_RF_POWER);
626 double rf_power_dBm, ad_power_dBm, minar_power_dBm;
628 if (n_agc_power == 0 )
631 ad_power_dBm = 10 * log10 ( (float)n_agc_power / (float)(1<<16) );
632 minor_power_dBm = ad_power_dBm - DIB3000MB_AGC_REF_dBm;
633 rf_power_dBm = (-DIB3000MB_GAIN_SLOPE_dBm * (float)rf_power / (float)(1<<16) +
634 DIB3000MB_GAIN_DELTA_dBm) + minor_power_dBm;
636 *strength = (u16) ((rf_power_dBm + 100) / 100 * 0xffff);
638 *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
644 * snr is the signal quality measured in dB.
645 * snr = 10*log10(signal power / noise power)
646 * the best quality is near 35dB (cable transmission & good modulator)
647 * the minimum without errors depend of transmission parameters
648 * some indicative values are given in en300744 Annex A
649 * ex : 16QAM 2/3 (Gaussian) = 11.1 dB
651 * If SNR is above 20dB, BER should be always 0.
652 * choose 0dB as the minimum
654 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
656 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
657 short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
658 int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
659 rd(DIB3000MB_REG_NOISE_POWER_LSB);
663 if (sigpow > 0 && icipow > 0)
664 snr_dBm = 10.0 * log10( (float) (sigpow<<8) / (float)icipow ) ;
668 *snr = (u16) ((snr_dBm / 35) * 0xffff);
670 *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
674 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
676 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
678 *unc = rd(DIB3000MB_REG_UNC);
682 static int dib3000mb_sleep(struct dvb_frontend* fe)
684 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
686 wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_DOWN);
690 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
692 tune->min_delay_ms = 800;
693 tune->step_size = 166667;
694 tune->max_drift = 166667*2;
699 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
701 return dib3000mb_fe_init(fe, 0);
704 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
706 return dib3000mb_set_frontend(fe, fep, 1);
709 static void dib3000mb_release(struct dvb_frontend* fe)
711 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
715 /* pid filter and transfer stuff */
716 static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
718 struct dib3000_state *state = fe->demodulator_priv;
719 pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
720 wr(index+DIB3000MB_REG_FIRST_PID,pid);
724 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
726 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
728 deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
730 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
732 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
737 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
739 //struct dib3000_state *state = fe->demodulator_priv;
740 /* switch it off and on */
744 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
746 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
748 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
750 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
755 static struct dvb_frontend_ops dib3000mb_ops;
757 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
758 struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
760 struct dib3000_state* state = NULL;
762 /* allocate memory for the internal state */
763 state = (struct dib3000_state*) kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
767 /* setup the state */
769 memcpy(&state->config,config,sizeof(struct dib3000_config));
770 memcpy(&state->ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
772 /* check for the correct demod */
773 if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
776 if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
779 /* create dvb_frontend */
780 state->frontend.ops = &state->ops;
781 state->frontend.demodulator_priv = state;
783 /* set the xfer operations */
784 xfer_ops->pid_parse = dib3000mb_pid_parse;
785 xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
786 xfer_ops->pid_ctrl = dib3000mb_pid_control;
787 xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
789 return &state->frontend;
797 static struct dvb_frontend_ops dib3000mb_ops = {
800 .name = "DiBcom 3000-MB DVB-T",
802 .frequency_min = 44250000,
803 .frequency_max = 867250000,
804 .frequency_stepsize = 62500,
805 .caps = FE_CAN_INVERSION_AUTO |
806 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
807 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
808 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
809 FE_CAN_TRANSMISSION_MODE_AUTO |
810 FE_CAN_GUARD_INTERVAL_AUTO |
812 FE_CAN_HIERARCHY_AUTO,
815 .release = dib3000mb_release,
817 .init = dib3000mb_fe_init_nonmobile,
818 .sleep = dib3000mb_sleep,
820 .set_frontend = dib3000mb_set_frontend_and_tuner,
821 .get_frontend = dib3000mb_get_frontend,
822 .get_tune_settings = dib3000mb_fe_get_tune_settings,
824 .read_status = dib3000mb_read_status,
825 .read_ber = dib3000mb_read_ber,
826 .read_signal_strength = dib3000mb_read_signal_strength,
827 .read_snr = dib3000mb_read_snr,
828 .read_ucblocks = dib3000mb_read_unc_blocks,
831 MODULE_AUTHOR(DRIVER_AUTHOR);
832 MODULE_DESCRIPTION(DRIVER_DESC);
833 MODULE_LICENSE("GPL");
835 EXPORT_SYMBOL(dib3000mb_attach);