2 * Frontend driver for mobile DVB-T demodulator DiBcom 3000-MC/P
3 * DiBcom (http://www.dibcom.fr/)
5 * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
7 * based on GPL code from DibCom, which has
9 * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation, version 2.
17 * Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18 * sources, on which this driver (and the dvb-dibusb) are based.
20 * see Documentation/dvb/README.dibusb for more information
23 #include <linux/config.h>
24 #include <linux/kernel.h>
25 #include <linux/version.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
31 #include "dvb_frontend.h"
32 #include "dib3000-common.h"
33 #include "dib3000mc_priv.h"
36 /* Version information */
37 #define DRIVER_VERSION "0.1"
38 #define DRIVER_DESC "DiBcom 3000-MC DVB-T demodulator driver"
39 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
41 #ifdef CONFIG_DVB_DIBCOM_DEBUG
43 module_param(debug, int, 0x644);
44 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
46 #define deb_info(args...) dprintk(0x01,args)
47 #define deb_xfer(args...) dprintk(0x02,args)
48 #define deb_setf(args...) dprintk(0x04,args)
49 #define deb_getf(args...) dprintk(0x08,args)
52 static int dib3000mc_set_impulse_noise(struct dib3000_state * state, int mode,
53 fe_transmit_mode_t transmission_mode, fe_bandwidth_t bandwidth)
55 switch (transmission_mode) {
56 case TRANSMISSION_MODE_2K:
57 wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[0]);
59 case TRANSMISSION_MODE_8K:
60 wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[1]);
67 /* case BANDWIDTH_5_MHZ:
68 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[0]);
71 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[1]);
74 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[2]);
77 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[3]);
84 case 0: /* no impulse */ /* fall through */
85 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[0]);
87 case 1: /* new algo */
88 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[1]);
89 set_or(DIB3000MC_REG_IMP_NOISE_55,DIB3000MC_IMP_NEW_ALGO(0)); /* gives 1<<10 */
91 default: /* old algo */
92 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[3]);
98 static int dib3000mc_set_timing(struct dib3000_state *state, int upd_offset,
99 fe_transmit_mode_t fft, fe_bandwidth_t bw)
101 u16 timf_msb,timf_lsb;
102 s32 tim_offset,tim_sgn;
103 u64 comp1,comp2,comp=0;
106 case BANDWIDTH_8_MHZ: comp = DIB3000MC_CLOCK_REF*8; break;
107 case BANDWIDTH_7_MHZ: comp = DIB3000MC_CLOCK_REF*7; break;
108 case BANDWIDTH_6_MHZ: comp = DIB3000MC_CLOCK_REF*6; break;
109 default: err("unknown bandwidth (%d)",bw); break;
111 timf_msb = (comp >> 16) & 0xff;
112 timf_lsb = (comp & 0xffff);
114 // Update the timing offset ;
115 if (upd_offset > 0) {
116 if (!state->timing_offset_comp_done) {
118 state->timing_offset_comp_done = 1;
120 tim_offset = rd(DIB3000MC_REG_TIMING_OFFS_MSB);
121 if ((tim_offset & 0x2000) == 0x2000)
122 tim_offset |= 0xC000;
123 if (fft == TRANSMISSION_MODE_2K)
125 state->timing_offset += tim_offset;
128 tim_offset = state->timing_offset;
129 if (tim_offset < 0) {
131 tim_offset = -tim_offset;
135 comp1 = (u32)tim_offset * (u32)timf_lsb ;
136 comp2 = (u32)tim_offset * (u32)timf_msb ;
137 comp = ((comp1 >> 16) + comp2) >> 7;
140 comp = (u32)(timf_msb << 16) + (u32) timf_lsb + comp;
142 comp = (u32)(timf_msb << 16) + (u32) timf_lsb - comp ;
144 timf_msb = (comp >> 16) & 0xff;
145 timf_lsb = comp & 0xffff;
147 wr(DIB3000MC_REG_TIMING_FREQ_MSB,timf_msb);
148 wr(DIB3000MC_REG_TIMING_FREQ_LSB,timf_lsb);
152 static int dib3000mc_init_auto_scan(struct dib3000_state *state, fe_bandwidth_t bw, int boost)
155 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_ON);
157 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_OFF);
160 case BANDWIDTH_8_MHZ:
161 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
163 case BANDWIDTH_7_MHZ:
164 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_7mhz);
166 case BANDWIDTH_6_MHZ:
167 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_6mhz);
169 /* case BANDWIDTH_5_MHZ:
170 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_5mhz);
175 err("unknown bandwidth value (%d).",bw);
179 u32 timeout = (rd(DIB3000MC_REG_BW_TIMOUT_MSB) << 16) +
180 rd(DIB3000MC_REG_BW_TIMOUT_LSB);
181 timeout *= 85; timeout >>= 7;
182 wr(DIB3000MC_REG_BW_TIMOUT_MSB,(timeout >> 16) & 0xffff);
183 wr(DIB3000MC_REG_BW_TIMOUT_LSB,timeout & 0xffff);
188 static int dib3000mc_get_frontend(struct dvb_frontend* fe,
189 struct dvb_frontend_parameters *fep);
191 static int dib3000mc_set_frontend(struct dvb_frontend* fe,
192 struct dvb_frontend_parameters *fep, int tuner)
194 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
195 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
196 fe_code_rate_t fe_cr = FEC_NONE;
197 int search_state, seq;
199 u8 fft=0, guard=0, qam=0, alpha=0, sel_hp=0, cr=0, hrch=0;
202 wr(DIB3000MC_REG_TUNER,
203 DIB3000_TUNER_WRITE_ENABLE(state->config.pll_addr));
204 state->config.pll_set(fe, fep);
205 wr(DIB3000MC_REG_TUNER,
206 DIB3000_TUNER_WRITE_DISABLE(state->config.pll_addr));
209 dib3000mc_set_timing(state,0,ofdm->transmission_mode,ofdm->bandwidth);
210 dib3000mc_init_auto_scan(state, ofdm->bandwidth, 0);
212 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_AGC);
213 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
215 /* Default cfg isi offset adp */
216 wr_foreach(dib3000mc_reg_offset,dib3000mc_offset[0]);
218 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT | DIB3000MC_ISI_INHIBIT);
219 wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[1]);
220 wr(DIB3000MC_REG_UNK_133,DIB3000MC_UNK_133);
222 wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
223 if (ofdm->bandwidth == BANDWIDTH_8_MHZ) {
224 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[3]);
226 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[0]);
229 switch (ofdm->transmission_mode) {
230 case TRANSMISSION_MODE_2K: fft = DIB3000_TRANSMISSION_MODE_2K; break;
231 case TRANSMISSION_MODE_8K: fft = DIB3000_TRANSMISSION_MODE_8K; break;
232 case TRANSMISSION_MODE_AUTO: break;
233 default: return -EINVAL;
235 switch (ofdm->guard_interval) {
236 case GUARD_INTERVAL_1_32: guard = DIB3000_GUARD_TIME_1_32; break;
237 case GUARD_INTERVAL_1_16: guard = DIB3000_GUARD_TIME_1_16; break;
238 case GUARD_INTERVAL_1_8: guard = DIB3000_GUARD_TIME_1_8; break;
239 case GUARD_INTERVAL_1_4: guard = DIB3000_GUARD_TIME_1_4; break;
240 case GUARD_INTERVAL_AUTO: break;
241 default: return -EINVAL;
243 switch (ofdm->constellation) {
244 case QPSK: qam = DIB3000_CONSTELLATION_QPSK; break;
245 case QAM_16: qam = DIB3000_CONSTELLATION_16QAM; break;
246 case QAM_64: qam = DIB3000_CONSTELLATION_64QAM; break;
247 case QAM_AUTO: break;
248 default: return -EINVAL;
250 switch (ofdm->hierarchy_information) {
251 case HIERARCHY_NONE: /* fall through */
252 case HIERARCHY_1: alpha = DIB3000_ALPHA_1; break;
253 case HIERARCHY_2: alpha = DIB3000_ALPHA_2; break;
254 case HIERARCHY_4: alpha = DIB3000_ALPHA_4; break;
255 case HIERARCHY_AUTO: break;
256 default: return -EINVAL;
258 if (ofdm->hierarchy_information == HIERARCHY_NONE) {
259 hrch = DIB3000_HRCH_OFF;
260 sel_hp = DIB3000_SELECT_HP;
261 fe_cr = ofdm->code_rate_HP;
262 } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
263 hrch = DIB3000_HRCH_ON;
264 sel_hp = DIB3000_SELECT_LP;
265 fe_cr = ofdm->code_rate_LP;
268 case FEC_1_2: cr = DIB3000_FEC_1_2; break;
269 case FEC_2_3: cr = DIB3000_FEC_2_3; break;
270 case FEC_3_4: cr = DIB3000_FEC_3_4; break;
271 case FEC_5_6: cr = DIB3000_FEC_5_6; break;
272 case FEC_7_8: cr = DIB3000_FEC_7_8; break;
273 case FEC_NONE: break;
274 case FEC_AUTO: break;
275 default: return -EINVAL;
278 wr(DIB3000MC_REG_DEMOD_PARM,DIB3000MC_DEMOD_PARM(alpha,qam,guard,fft));
279 wr(DIB3000MC_REG_HRCH_PARM,DIB3000MC_HRCH_PARM(sel_hp,cr,hrch));
281 switch (fep->inversion) {
283 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
288 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_ON);
295 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
296 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
297 [fep->inversion == INVERSION_AUTO];
299 deb_setf("seq? %d\n", seq);
300 wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS(seq,1));
302 dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
304 val = rd(DIB3000MC_REG_DEMOD_PARM);
305 wr(DIB3000MC_REG_DEMOD_PARM,val|DIB3000MC_DEMOD_RST_DEMOD_ON);
306 wr(DIB3000MC_REG_DEMOD_PARM,val);
310 wr_foreach(dib3000mc_reg_agc_bandwidth, dib3000mc_agc_bandwidth);
312 /* something has to be auto searched */
313 if (ofdm->constellation == QAM_AUTO ||
314 ofdm->hierarchy_information == HIERARCHY_AUTO ||
315 ofdm->guard_interval == GUARD_INTERVAL_AUTO ||
316 ofdm->transmission_mode == TRANSMISSION_MODE_AUTO ||
318 fep->inversion == INVERSION_AUTO
322 deb_setf("autosearch enabled.\n");
324 val = rd(DIB3000MC_REG_DEMOD_PARM);
325 wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
326 wr(DIB3000MC_REG_DEMOD_PARM,val);
328 while ((search_state = dib3000_search_status(
329 rd(DIB3000MC_REG_AS_IRQ),1)) < 0 && as_count++ < 100)
332 deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
334 if (search_state == 1) {
335 struct dvb_frontend_parameters feps;
336 feps.u.ofdm.bandwidth = ofdm->bandwidth; /* bw is not auto searched */;
337 if (dib3000mc_get_frontend(fe, &feps) == 0) {
338 deb_setf("reading tuning data from frontend succeeded.\n");
339 return dib3000mc_set_frontend(fe, &feps, 0);
343 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
344 wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[qam]);
346 wr_foreach(dib3000mc_reg_offset,
347 dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
349 // dib3000mc_set_timing(1,ofdm->transmission_mode,ofdm->bandwidth);
351 // wr(DIB3000MC_REG_LOCK_MASK,DIB3000MC_ACTIVATE_LOCK_MASK); /* activates some locks if needed */
353 /* set_or(DIB3000MC_REG_DEMOD_PARM,DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
354 set_or(DIB3000MC_REG_DEMOD_PARM,DIB3000MC_DEMOD_RST_AUTO_SRCH_OFF);
355 wr(DIB3000MC_REG_RESTART_VIT,DIB3000MC_RESTART_VIT_ON);
356 wr(DIB3000MC_REG_RESTART_VIT,DIB3000MC_RESTART_VIT_OFF);*/
363 static int dib3000mc_fe_init(struct dvb_frontend* fe, int mobile_mode)
365 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
367 state->timing_offset = 0;
368 state->timing_offset_comp_done = 0;
370 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
371 wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_PAR_CONT_CLK);
372 wr(DIB3000MC_REG_RST_I2C_ADDR,
373 DIB3000MC_DEMOD_ADDR(state->config.demod_address) |
374 DIB3000MC_DEMOD_ADDR_ON);
376 wr(DIB3000MC_REG_RST_I2C_ADDR,
377 DIB3000MC_DEMOD_ADDR(state->config.demod_address));
379 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_CONFIG);
380 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
382 wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_UP);
383 wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_PUP_MOBILE);
384 wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_UP);
385 wr(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_INIT);
387 wr(DIB3000MC_REG_RST_UNC,DIB3000MC_RST_UNC_OFF);
388 wr(DIB3000MC_REG_UNK_19,DIB3000MC_UNK_19);
392 wr(DIB3000MC_REG_UNK_88,DIB3000MC_UNK_88);
394 wr(DIB3000MC_REG_UNK_99,DIB3000MC_UNK_99);
395 wr(DIB3000MC_REG_UNK_111,DIB3000MC_UNK_111_PH_N_MODE_0); /* phase noise algo off */
397 /* mobile mode - portable reception */
398 wr_foreach(dib3000mc_reg_mobile_mode,dib3000mc_mobile_mode[1]);
400 /* TUNER_PANASONIC_ENV57H12D5: */
401 wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
402 wr_foreach(dib3000mc_reg_agc_bandwidth_general,dib3000mc_agc_bandwidth_general);
403 wr_foreach(dib3000mc_reg_agc,dib3000mc_agc_tuner[1]);
405 wr(DIB3000MC_REG_UNK_110,DIB3000MC_UNK_110);
407 wr(DIB3000MC_REG_UNK_1,DIB3000MC_UNK_1);
408 wr(DIB3000MC_REG_UNK_2,DIB3000MC_UNK_2);
409 wr(DIB3000MC_REG_UNK_3,DIB3000MC_UNK_3);
410 wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS_DEFAULT);
412 wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
413 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
415 wr(DIB3000MC_REG_UNK_4,DIB3000MC_UNK_4);
417 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
418 wr(DIB3000MC_REG_SET_DDS_FREQ_LSB,DIB3000MC_DDS_FREQ_LSB);
420 dib3000mc_set_timing(state,0,TRANSMISSION_MODE_2K,BANDWIDTH_8_MHZ);
421 // wr_foreach(dib3000mc_reg_timing_freq,dib3000mc_timing_freq[3]);
423 wr(DIB3000MC_REG_UNK_120,DIB3000MC_UNK_120);
424 wr(DIB3000MC_REG_UNK_134,DIB3000MC_UNK_134);
425 wr(DIB3000MC_REG_FEC_CFG,DIB3000MC_FEC_CFG);
427 dib3000mc_set_impulse_noise(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
429 /* output mode control, just the MPEG2_SLAVE */
430 set_or(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
431 wr(DIB3000MC_REG_SMO_MODE,DIB3000MC_SMO_MODE_SLAVE);
432 wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_SLAVE);
433 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_SLAVE);
435 /* MPEG2_PARALLEL_CONTINUOUS_CLOCK
436 wr(DIB3000MC_REG_OUTMODE,
437 DIB3000MC_SET_OUTMODE(DIB3000MC_OM_PAR_CONT_CLK,
438 rd(DIB3000MC_REG_OUTMODE)));
440 wr(DIB3000MC_REG_SMO_MODE,
441 DIB3000MC_SMO_MODE_DEFAULT |
442 DIB3000MC_SMO_MODE_188);
444 wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_DEFAULT);
445 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
448 wr(DIB3000MC_REG_DIVERSITY1,DIB3000MC_DIVERSITY1_DEFAULT);
449 wr(DIB3000MC_REG_DIVERSITY2,DIB3000MC_DIVERSITY2_DEFAULT);
451 wr(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
453 set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_DIV_IN_OFF);
456 /* if (state->config->pll_init) {
457 wr(DIB3000MC_REG_TUNER,
458 DIB3000_TUNER_WRITE_ENABLE(state->config->pll_addr));
459 state->config->pll_init(fe);
460 wr(DIB3000MC_REG_TUNER,
461 DIB3000_TUNER_WRITE_DISABLE(state->config->pll_addr));
466 static int dib3000mc_get_frontend(struct dvb_frontend* fe,
467 struct dvb_frontend_parameters *fep)
469 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
470 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
473 int inv_test1,inv_test2;
474 u32 dds_val, threshold = 0x1000000;
476 if (!(rd(DIB3000MC_REG_LOCK_507) & DIB3000MC_LOCK_507))
479 dds_val = ((rd(DIB3000MC_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MC_REG_DDS_FREQ_LSB);
480 if (dds_val < threshold)
482 else if (dds_val == threshold)
487 dds_val = ((rd(DIB3000MC_REG_SET_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MC_REG_SET_DDS_FREQ_LSB);
488 if (dds_val < threshold)
490 else if (dds_val == threshold)
496 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
497 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
498 INVERSION_ON : INVERSION_OFF;
500 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
502 tps_val = rd(DIB3000MC_REG_TUNING_PARM);
504 switch (DIB3000MC_TP_QAM(tps_val)) {
505 case DIB3000_CONSTELLATION_QPSK:
507 ofdm->constellation = QPSK;
509 case DIB3000_CONSTELLATION_16QAM:
511 ofdm->constellation = QAM_16;
513 case DIB3000_CONSTELLATION_64QAM:
515 ofdm->constellation = QAM_64;
518 err("Unexpected constellation returned by TPS (%d)", tps_val);
522 if (DIB3000MC_TP_HRCH(tps_val)) {
523 deb_getf("HRCH ON ");
524 cr = &ofdm->code_rate_LP;
525 ofdm->code_rate_HP = FEC_NONE;
526 switch (DIB3000MC_TP_ALPHA(tps_val)) {
527 case DIB3000_ALPHA_0:
528 deb_getf("HIERARCHY_NONE ");
529 ofdm->hierarchy_information = HIERARCHY_NONE;
531 case DIB3000_ALPHA_1:
532 deb_getf("HIERARCHY_1 ");
533 ofdm->hierarchy_information = HIERARCHY_1;
535 case DIB3000_ALPHA_2:
536 deb_getf("HIERARCHY_2 ");
537 ofdm->hierarchy_information = HIERARCHY_2;
539 case DIB3000_ALPHA_4:
540 deb_getf("HIERARCHY_4 ");
541 ofdm->hierarchy_information = HIERARCHY_4;
544 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
547 cr_val = DIB3000MC_TP_FEC_CR_LP(tps_val);
549 deb_getf("HRCH OFF ");
550 cr = &ofdm->code_rate_HP;
551 ofdm->code_rate_LP = FEC_NONE;
552 ofdm->hierarchy_information = HIERARCHY_NONE;
553 cr_val = DIB3000MC_TP_FEC_CR_HP(tps_val);
557 case DIB3000_FEC_1_2:
558 deb_getf("FEC_1_2 ");
561 case DIB3000_FEC_2_3:
562 deb_getf("FEC_2_3 ");
565 case DIB3000_FEC_3_4:
566 deb_getf("FEC_3_4 ");
569 case DIB3000_FEC_5_6:
570 deb_getf("FEC_5_6 ");
573 case DIB3000_FEC_7_8:
574 deb_getf("FEC_7_8 ");
578 err("Unexpected FEC returned by TPS (%d)", tps_val);
582 switch (DIB3000MC_TP_GUARD(tps_val)) {
583 case DIB3000_GUARD_TIME_1_32:
584 deb_getf("GUARD_INTERVAL_1_32 ");
585 ofdm->guard_interval = GUARD_INTERVAL_1_32;
587 case DIB3000_GUARD_TIME_1_16:
588 deb_getf("GUARD_INTERVAL_1_16 ");
589 ofdm->guard_interval = GUARD_INTERVAL_1_16;
591 case DIB3000_GUARD_TIME_1_8:
592 deb_getf("GUARD_INTERVAL_1_8 ");
593 ofdm->guard_interval = GUARD_INTERVAL_1_8;
595 case DIB3000_GUARD_TIME_1_4:
596 deb_getf("GUARD_INTERVAL_1_4 ");
597 ofdm->guard_interval = GUARD_INTERVAL_1_4;
600 err("Unexpected Guard Time returned by TPS (%d)", tps_val);
604 switch (DIB3000MC_TP_FFT(tps_val)) {
605 case DIB3000_TRANSMISSION_MODE_2K:
606 deb_getf("TRANSMISSION_MODE_2K ");
607 ofdm->transmission_mode = TRANSMISSION_MODE_2K;
609 case DIB3000_TRANSMISSION_MODE_8K:
610 deb_getf("TRANSMISSION_MODE_8K ");
611 ofdm->transmission_mode = TRANSMISSION_MODE_8K;
614 err("unexpected transmission mode return by TPS (%d)", tps_val);
620 static int dib3000mc_read_status(struct dvb_frontend* fe, fe_status_t *stat)
622 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
623 u16 lock = rd(DIB3000MC_REG_LOCKING);
626 if (DIB3000MC_AGC_LOCK(lock))
627 *stat |= FE_HAS_SIGNAL;
628 if (DIB3000MC_CARRIER_LOCK(lock))
629 *stat |= FE_HAS_CARRIER;
630 if (DIB3000MC_TPS_LOCK(lock)) /* VIT_LOCK ? */
631 *stat |= FE_HAS_VITERBI;
632 if (DIB3000MC_MPEG_SYNC_LOCK(lock))
633 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
635 deb_info("actual status is %2x\n",*stat);
640 static int dib3000mc_read_ber(struct dvb_frontend* fe, u32 *ber)
642 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
643 *ber = ((rd(DIB3000MC_REG_BER_MSB) << 16) | rd(DIB3000MC_REG_BER_LSB));
647 static int dib3000mc_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
649 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
651 *unc = rd(DIB3000MC_REG_PACKET_ERROR_COUNT);
655 /* see dib3000mb.c for calculation comments */
656 static int dib3000mc_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
658 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
659 u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB);
660 *strength = (((val >> 6) & 0xff) << 8) + (val & 0x3f);
662 deb_info("signal: mantisse = %d, exponent = %d\n",(*strength >> 8) & 0xff, *strength & 0xff);
666 /* see dib3000mb.c for calculation comments */
667 static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
669 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
671 u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_MSB),
672 val2 = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB);
675 sig = (((val >> 6) & 0xff) << 8) + (val & 0x3f);
676 noise = (((val >> 4) & 0xff) << 8) + ((val & 0xf) << 2) + ((val2 >> 14) & 0x3);
680 *snr = (u16) sig/noise;
682 deb_info("signal: mantisse = %d, exponent = %d\n",(sig >> 8) & 0xff, sig & 0xff);
683 deb_info("noise: mantisse = %d, exponent = %d\n",(noise >> 8) & 0xff, noise & 0xff);
684 deb_info("snr: %d\n",*snr);
688 static int dib3000mc_sleep(struct dvb_frontend* fe)
690 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
692 set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_PWR_DOWN);
693 wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_DOWN);
694 wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_POWER_DOWN);
695 wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_DOWN);
699 static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
701 tune->min_delay_ms = 800;
702 tune->step_size = 166667;
703 tune->max_drift = 166667 * 2;
708 static int dib3000mc_fe_init_nonmobile(struct dvb_frontend* fe)
710 return dib3000mc_fe_init(fe, 0);
713 static int dib3000mc_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
715 return dib3000mc_set_frontend(fe, fep, 1);
718 static void dib3000mc_release(struct dvb_frontend* fe)
720 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
721 dib3000_dealloc_pid_list(state);
725 /* pid filter and transfer stuff */
726 static int dib3000mc_pid_control(struct dvb_frontend *fe,int pid,int onoff)
728 struct dib3000_state *state = fe->demodulator_priv;
729 int index = dib3000_get_pid_index(state->pid_list, DIB3000MC_NUM_PIDS, pid, &state->pid_list_lock,onoff);
730 pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
733 wr(index+DIB3000MC_REG_FIRST_PID,pid);
735 err("no more pids for filtering.");
741 static int dib3000mc_fifo_control(struct dvb_frontend *fe, int onoff)
743 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
744 u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
745 deb_xfer("%s fifo",onoff ? "enabling" : "disabling");
747 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
749 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
754 static int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
756 struct dib3000_state *state = fe->demodulator_priv;
757 u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
758 deb_xfer("%s pid parsing",onoff ? "enabling" : "disabling");
760 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_PID_PARSE);
762 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_NO_PID_PARSE);
767 static struct dvb_frontend_ops dib3000mc_ops;
769 struct dvb_frontend* dib3000mc_attach(const struct dib3000_config* config,
770 struct i2c_adapter* i2c, struct dib3000_xfer_ops *xfer_ops)
772 struct dib3000_state* state = NULL;
775 /* allocate memory for the internal state */
776 state = (struct dib3000_state*) kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
780 /* setup the state */
782 memcpy(&state->config,config,sizeof(struct dib3000_config));
783 memcpy(&state->ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
785 /* check for the correct demod */
786 if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
789 devid = rd(DIB3000_REG_DEVICE_ID);
790 if (devid != DIB3000MC_DEVICE_ID && devid != DIB3000P_DEVICE_ID)
795 case DIB3000MC_DEVICE_ID:
796 info("Found a DiBcom 3000-MC.");
798 case DIB3000P_DEVICE_ID:
799 info("Found a DiBcom 3000-P.");
803 if (dib3000_init_pid_list(state,DIB3000MC_NUM_PIDS))
806 /* create dvb_frontend */
807 state->frontend.ops = &state->ops;
808 state->frontend.demodulator_priv = state;
810 /* set the xfer operations */
811 xfer_ops->pid_parse = dib3000mc_pid_parse;
812 xfer_ops->fifo_ctrl = dib3000mc_fifo_control;
813 xfer_ops->pid_ctrl = dib3000mc_pid_control;
815 return &state->frontend;
823 static struct dvb_frontend_ops dib3000mc_ops = {
826 .name = "DiBcom 3000-MC/P DVB-T",
828 .frequency_min = 44250000,
829 .frequency_max = 867250000,
830 .frequency_stepsize = 62500,
831 .caps = FE_CAN_INVERSION_AUTO |
832 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
833 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
834 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
835 FE_CAN_TRANSMISSION_MODE_AUTO |
836 FE_CAN_GUARD_INTERVAL_AUTO |
837 FE_CAN_HIERARCHY_AUTO,
840 .release = dib3000mc_release,
842 .init = dib3000mc_fe_init_nonmobile,
843 .sleep = dib3000mc_sleep,
845 .set_frontend = dib3000mc_set_frontend_and_tuner,
846 .get_frontend = dib3000mc_get_frontend,
847 .get_tune_settings = dib3000mc_fe_get_tune_settings,
849 .read_status = dib3000mc_read_status,
850 .read_ber = dib3000mc_read_ber,
851 .read_signal_strength = dib3000mc_read_signal_strength,
852 .read_snr = dib3000mc_read_snr,
853 .read_ucblocks = dib3000mc_read_unc_blocks,
856 MODULE_AUTHOR(DRIVER_AUTHOR);
857 MODULE_DESCRIPTION(DRIVER_DESC);
858 MODULE_LICENSE("GPL");
860 EXPORT_SYMBOL(dib3000mc_attach);