2 Driver for Zarlink MT312 Satellite Channel Decoder
4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 http://products.zarlink.com/product_profiles/MT312.htm
23 http://products.zarlink.com/product_profiles/SL1935.htm
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
32 #include "dvb_frontend.h"
35 #define I2C_ADDR_MT312 0x0e
36 #define I2C_ADDR_SL1935 0x61
37 #define I2C_ADDR_TSA5059 0x61
41 #define MT312_SYS_CLK 90000000UL /* 90 MHz */
42 #define MT312_LPOWER_SYS_CLK 60000000UL /* 60 MHz */
43 #define MT312_PLL_CLK 10000000UL /* 10 MHz */
45 /* number of active frontends */
46 static int mt312_count = 0;
52 #define dprintk if(debug == 1) printk
55 static struct dvb_frontend_info mt312_info = {
56 .name = "Zarlink MT312",
58 .frequency_min = 950000,
59 .frequency_max = 2150000,
60 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
61 /*.frequency_tolerance = 29500, FIXME: binary compatibility waste? */
62 .symbol_rate_min = MT312_SYS_CLK / 128,
63 .symbol_rate_max = MT312_SYS_CLK / 2,
64 /*.symbol_rate_tolerance = 500, FIXME: binary compatibility waste? 2% */
67 FE_CAN_INVERSION_AUTO | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
68 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
69 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
73 static int mt312_read(struct dvb_i2c_bus *i2c,
74 const enum mt312_reg_addr reg, void *buf,
78 struct i2c_msg msg[2];
79 u8 regbuf[1] = { reg };
81 msg[0].addr = I2C_ADDR_MT312;
85 msg[1].addr = I2C_ADDR_MT312;
86 msg[1].flags = I2C_M_RD;
90 ret = i2c->xfer(i2c, msg, 2);
92 if ((ret != 2) && (mt312_count != 0)) {
93 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
99 printk(KERN_INFO "R(%d):", reg & 0x7f);
100 for (i = 0; i < count; i++)
101 printk(" %02x", ((const u8 *) buf)[i]);
109 static int mt312_write(struct dvb_i2c_bus *i2c,
110 const enum mt312_reg_addr reg, const void *src,
120 printk(KERN_INFO "W(%d):", reg & 0x7f);
121 for (i = 0; i < count; i++)
122 printk(" %02x", ((const u8 *) src)[i]);
128 memcpy(&buf[1], src, count);
130 msg.addr = I2C_ADDR_MT312;
135 ret = i2c->xfer(i2c, &msg, 1);
138 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
145 static inline int mt312_readreg(struct dvb_i2c_bus *i2c,
146 const enum mt312_reg_addr reg, u8 * val)
148 return mt312_read(i2c, reg, val, 1);
151 static inline int mt312_writereg(struct dvb_i2c_bus *i2c,
152 const enum mt312_reg_addr reg, const u8 val)
154 return mt312_write(i2c, reg, &val, 1);
157 static int mt312_pll_write(struct dvb_i2c_bus *i2c, const u8 addr,
158 u8 * buf, const u8 len)
168 if ((ret = mt312_writereg(i2c, GPP_CTRL, 0x40)) < 0)
171 if ((ret = i2c->xfer(i2c, &msg, 1)) != 1)
172 printk(KERN_ERR "%s: i/o error (ret == %d)\n", __FUNCTION__, ret);
174 if ((ret = mt312_writereg(i2c, GPP_CTRL, 0x00)) < 0)
180 static inline u32 mt312_div(u32 a, u32 b)
182 return (a + (b / 2)) / b;
185 static int sl1935_set_tv_freq(struct dvb_i2c_bus *i2c, u32 freq, u32 sr)
187 /* 155 uA, Baseband Path B */
188 u8 buf[4] = { 0x00, 0x00, 0x80, 0x00 };
194 if (sr < 10000000) { /* 1-10 MSym/s: ratio 2 ^ 3 */
196 buf[2] |= 0x40; /* 690 uA */
197 } else if (sr < 15000000) { /* 10-15 MSym/s: ratio 2 ^ 4 */
199 buf[2] |= 0x20; /* 330 uA */
200 } else { /* 15-45 MSym/s: ratio 2 ^ 7 */
202 buf[3] |= 0x08; /* Baseband Path A */
205 div = mt312_div(MT312_PLL_CLK, 1 << exp);
206 ref = mt312_div(freq * 1000, div);
207 mt312_info.frequency_stepsize = mt312_div(div, 1000);
209 buf[0] = (ref >> 8) & 0x7f;
210 buf[1] = (ref >> 0) & 0xff;
216 dprintk(KERN_INFO "synth dword = %02x%02x%02x%02x\n", buf[0],
217 buf[1], buf[2], buf[3]);
219 return mt312_pll_write(i2c, I2C_ADDR_SL1935, buf, sizeof(buf));
222 static int tsa5059_set_tv_freq(struct dvb_i2c_bus *i2c, u32 freq, u32 sr)
226 u32 ref = mt312_div(freq, 125);
228 buf[0] = (ref >> 8) & 0x7f;
229 buf[1] = (ref >> 0) & 0xff;
230 buf[2] = 0x84 | ((ref >> 10) & 0x60);
236 dprintk(KERN_INFO "synth dword = %02x%02x%02x%02x\n", buf[0],
237 buf[1], buf[2], buf[3]);
239 return mt312_pll_write(i2c, I2C_ADDR_TSA5059, buf, sizeof(buf));
242 static int mt312_reset(struct dvb_i2c_bus *i2c, const u8 full)
244 return mt312_writereg(i2c, RESET, full ? 0x80 : 0x40);
247 static int mt312_init(struct dvb_i2c_bus *i2c, const long id, u8 pll)
253 if ((ret = mt312_writereg(i2c, CONFIG, (pll == 60 ? 0x88 : 0x8c))) < 0)
256 /* wait at least 150 usec */
260 if ((ret = mt312_reset(i2c, 1)) < 0)
263 // Per datasheet, write correct values. 09/28/03 ACCJr.
264 // If we don't do this, we won't get FE_HAS_VITERBI in the VP310.
266 u8 buf_def[8]={0x14, 0x12, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00};
268 if ((ret = mt312_write(i2c, VIT_SETUP, buf_def, sizeof(buf_def))) < 0)
273 buf[0] = mt312_div((pll == 60 ? MT312_LPOWER_SYS_CLK : MT312_SYS_CLK) * 2, 1000000);
276 buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
278 if ((ret = mt312_write(i2c, SYS_CLK, buf, sizeof(buf))) < 0)
281 if ((ret = mt312_writereg(i2c, SNR_THS_HIGH, 0x32)) < 0)
284 if ((ret = mt312_writereg(i2c, OP_CTRL, 0x53)) < 0)
291 if ((ret = mt312_write(i2c, TS_SW_LIM_L, buf, sizeof(buf))) < 0)
294 if ((ret = mt312_writereg(i2c, CS_SW_LIM, 0x69)) < 0)
300 static int mt312_send_master_cmd(struct dvb_i2c_bus *i2c,
301 const struct dvb_diseqc_master_cmd *c)
306 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
309 if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)
313 mt312_write(i2c, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0)
317 mt312_writereg(i2c, DISEQC_MODE,
318 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
322 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
323 if (c->msg[0] & 0x02)
325 mt312_writereg(i2c, DISEQC_MODE, (diseqc_mode & 0x40))) < 0)
331 static int mt312_recv_slave_reply(struct dvb_i2c_bus *i2c,
332 struct dvb_diseqc_slave_reply *r)
338 static int mt312_send_burst(struct dvb_i2c_bus *i2c, const fe_sec_mini_cmd_t c)
340 const u8 mini_tab[2] = { 0x02, 0x03 };
348 if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)
352 mt312_writereg(i2c, DISEQC_MODE,
353 (diseqc_mode & 0x40) | mini_tab[c])) < 0)
359 static int mt312_set_tone(struct dvb_i2c_bus *i2c, const fe_sec_tone_mode_t t)
361 const u8 tone_tab[2] = { 0x01, 0x00 };
366 if (t > SEC_TONE_OFF)
369 if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)
373 mt312_writereg(i2c, DISEQC_MODE,
374 (diseqc_mode & 0x40) | tone_tab[t])) < 0)
380 static int mt312_set_voltage(struct dvb_i2c_bus *i2c, const fe_sec_voltage_t v)
382 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
384 if (v > SEC_VOLTAGE_OFF)
387 return mt312_writereg(i2c, DISEQC_MODE, volt_tab[v]);
390 static int mt312_read_status(struct dvb_i2c_bus *i2c, fe_status_t *s, const long id)
393 u8 status[3], vit_mode;
397 if ((ret = mt312_read(i2c, QPSK_STAT_H, status, sizeof(status))) < 0)
400 dprintk(KERN_DEBUG "QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
402 if (status[0] & 0xc0)
403 *s |= FE_HAS_SIGNAL; /* signal noise ratio */
404 if (status[0] & 0x04)
405 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */
406 if (status[2] & 0x02)
407 *s |= FE_HAS_VITERBI; /* viterbi lock */
408 if (status[2] & 0x04)
409 *s |= FE_HAS_SYNC; /* byte align lock */
410 if (status[0] & 0x01)
411 *s |= FE_HAS_LOCK; /* qpsk lock */
412 // VP310 doesn't have AUTO, so we "implement it here" ACCJr
413 if ((id == ID_VP310) && !(status[0] & 0x01)) {
414 if ((ret = mt312_readreg(i2c, VIT_MODE, &vit_mode)) < 0)
417 if ((ret = mt312_writereg(i2c, VIT_MODE, vit_mode)) < 0)
419 if ((ret = mt312_writereg(i2c, GO, 0x01)) < 0)
426 static int mt312_read_bercnt(struct dvb_i2c_bus *i2c, u32 * ber)
431 if ((ret = mt312_read(i2c, RS_BERCNT_H, buf, 3)) < 0)
434 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
439 static int mt312_read_agc(struct dvb_i2c_bus *i2c, u16 * signal_strength)
446 if ((ret = mt312_read(i2c, AGC_H, buf, sizeof(buf))) < 0)
449 agc = (buf[0] << 6) | (buf[1] >> 2);
450 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
452 *signal_strength = agc;
454 dprintk(KERN_DEBUG "agc=%08x err_db=%hd\n", agc, err_db);
459 static int mt312_read_snr(struct dvb_i2c_bus *i2c, u16 * snr)
464 if ((ret = mt312_read(i2c, M_SNR_H, &buf, sizeof(buf))) < 0)
467 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
472 static int mt312_read_ubc(struct dvb_i2c_bus *i2c, u32 * ubc)
477 if ((ret = mt312_read(i2c, RS_UBC_H, &buf, sizeof(buf))) < 0)
480 *ubc = (buf[0] << 8) | buf[1];
485 static int mt312_set_frontend(struct dvb_i2c_bus *i2c,
486 const struct dvb_frontend_parameters *p,
490 u8 buf[5], config_val;
493 const u8 fec_tab[10] =
494 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
495 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
497 int (*set_tv_freq)(struct dvb_i2c_bus *i2c, u32 freq, u32 sr);
499 dprintk("%s: Freq %d\n", __FUNCTION__, p->frequency);
501 if ((p->frequency < mt312_info.frequency_min)
502 || (p->frequency > mt312_info.frequency_max))
505 if ((p->inversion < INVERSION_OFF)
506 || (p->inversion > INVERSION_AUTO))
509 if ((p->u.qpsk.symbol_rate < mt312_info.symbol_rate_min)
510 || (p->u.qpsk.symbol_rate > mt312_info.symbol_rate_max))
513 if ((p->u.qpsk.fec_inner < FEC_NONE)
514 || (p->u.qpsk.fec_inner > FEC_AUTO))
517 if ((p->u.qpsk.fec_inner == FEC_4_5)
518 || (p->u.qpsk.fec_inner == FEC_8_9))
523 // For now we will do this only for the VP310.
524 // It should be better for the mt312 as well, but tunning will be slower. ACCJr 09/29/03
525 if ((ret = mt312_readreg(i2c, CONFIG, &config_val) < 0))
527 if (p->u.qpsk.symbol_rate >= 30000000) //Note that 30MS/s should use 90MHz
529 if ((config_val & 0x0c) == 0x08) //We are running 60MHz
530 if ((ret = mt312_init(i2c, id, (u8) 90)) < 0)
535 if ((config_val & 0x0c) == 0x0C) //We are running 90MHz
536 if ((ret = mt312_init(i2c, id, (u8) 60)) < 0)
539 set_tv_freq = tsa5059_set_tv_freq;
542 set_tv_freq = sl1935_set_tv_freq;
548 if ((ret = set_tv_freq(i2c, p->frequency, p->u.qpsk.symbol_rate)) < 0)
551 /* sr = (u16)(sr * 256.0 / 1000000.0) */
552 sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
555 buf[0] = (sr >> 8) & 0x3f;
556 buf[1] = (sr >> 0) & 0xff;
559 buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
562 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
564 if (p->u.qpsk.symbol_rate < 10000000)
565 buf[3] |= 0x04; /* use afc mode */
570 if ((ret = mt312_write(i2c, SYM_RATE_H, buf, sizeof(buf))) < 0)
578 static int mt312_get_inversion(struct dvb_i2c_bus *i2c,
579 fe_spectral_inversion_t * i)
584 if ((ret = mt312_readreg(i2c, VIT_MODE, &vit_mode)) < 0)
587 if (vit_mode & 0x80) /* auto inversion was used */
588 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
593 static int mt312_get_symbol_rate(struct dvb_i2c_bus *i2c, u32 * sr)
602 if ((ret = mt312_readreg(i2c, SYM_RATE_H, &sym_rate_h)) < 0)
605 if (sym_rate_h & 0x80) { /* symbol rate search was used */
606 if ((ret = mt312_writereg(i2c, MON_CTRL, 0x03)) < 0)
609 if ((ret = mt312_read(i2c, MONITOR_H, buf, sizeof(buf))) < 0)
612 monitor = (buf[0] << 8) | buf[1];
614 dprintk(KERN_DEBUG "sr(auto) = %u\n",
615 mt312_div(monitor * 15625, 4));
617 if ((ret = mt312_writereg(i2c, MON_CTRL, 0x05)) < 0)
620 if ((ret = mt312_read(i2c, MONITOR_H, buf, sizeof(buf))) < 0)
623 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
625 if ((ret = mt312_read(i2c, SYM_RAT_OP_H, buf, sizeof(buf))) < 0)
628 sym_rat_op = (buf[0] << 8) | buf[1];
630 dprintk(KERN_DEBUG "sym_rat_op=%d dec_ratio=%d\n",
631 sym_rat_op, dec_ratio);
632 dprintk(KERN_DEBUG "*sr(manual) = %lu\n",
633 (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
640 static int mt312_get_code_rate(struct dvb_i2c_bus *i2c, fe_code_rate_t * cr)
642 const fe_code_rate_t fec_tab[8] =
643 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
644 FEC_AUTO, FEC_AUTO };
649 if ((ret = mt312_readreg(i2c, FEC_STATUS, &fec_status)) < 0)
652 *cr = fec_tab[(fec_status >> 4) & 0x07];
657 static int mt312_get_frontend(struct dvb_i2c_bus *i2c,
658 struct dvb_frontend_parameters *p)
662 if ((ret = mt312_get_inversion(i2c, &p->inversion)) < 0)
665 if ((ret = mt312_get_symbol_rate(i2c, &p->u.qpsk.symbol_rate)) < 0)
668 if ((ret = mt312_get_code_rate(i2c, &p->u.qpsk.fec_inner)) < 0)
674 static int mt312_sleep(struct dvb_i2c_bus *i2c)
679 /* reset all registers to defaults */
680 if ((ret = mt312_reset(i2c, 1)) < 0)
683 if ((ret = mt312_readreg(i2c, CONFIG, &config)) < 0)
687 if ((ret = mt312_writereg(i2c, CONFIG, config & 0x7f)) < 0)
693 static int mt312_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
695 struct dvb_i2c_bus *i2c = fe->i2c;
699 memcpy(arg, &mt312_info, sizeof(struct dvb_frontend_info));
702 case FE_DISEQC_RESET_OVERLOAD:
705 case FE_DISEQC_SEND_MASTER_CMD:
706 return mt312_send_master_cmd(i2c, arg);
708 case FE_DISEQC_RECV_SLAVE_REPLY:
709 if ((long) fe->data == ID_MT312)
710 return mt312_recv_slave_reply(i2c, arg);
714 case FE_DISEQC_SEND_BURST:
715 return mt312_send_burst(i2c, (fe_sec_mini_cmd_t) arg);
718 return mt312_set_tone(i2c, (fe_sec_tone_mode_t) arg);
721 return mt312_set_voltage(i2c, (fe_sec_voltage_t) arg);
723 case FE_ENABLE_HIGH_LNB_VOLTAGE:
727 return mt312_read_status(i2c, arg, (long) fe->data);
730 return mt312_read_bercnt(i2c, arg);
732 case FE_READ_SIGNAL_STRENGTH:
733 return mt312_read_agc(i2c, arg);
736 return mt312_read_snr(i2c, arg);
738 case FE_READ_UNCORRECTED_BLOCKS:
739 return mt312_read_ubc(i2c, arg);
741 case FE_SET_FRONTEND:
742 return mt312_set_frontend(i2c, arg, (long) fe->data);
744 case FE_GET_FRONTEND:
745 return mt312_get_frontend(i2c, arg);
751 return mt312_sleep(i2c);
754 //For the VP310 we should run at 60MHz when ever possible.
755 //It should be better to run the mt312 ar lower speed when ever possible, but tunning will be slower. ACCJr 09/29/03
756 if ((long)fe->data == ID_MT312)
757 return mt312_init(i2c, (long) fe->data, (u8) 90);
759 return mt312_init(i2c, (long) fe->data, (u8) 60);
761 case FE_GET_TUNE_SETTINGS:
763 struct dvb_frontend_tune_settings* fesettings = (struct dvb_frontend_tune_settings*) arg;
764 fesettings->min_delay_ms = 50;
765 fesettings->step_size = 0;
766 fesettings->max_drift = 0;
777 static int mt312_attach(struct dvb_i2c_bus *i2c, void **data)
782 if ((ret = mt312_readreg(i2c, ID, &id)) < 0)
785 if ((id != ID_VP310) && (id != ID_MT312))
788 if ((ret = dvb_register_frontend(mt312_ioctl, i2c,
789 (void *)(long)id, &mt312_info)) < 0)
797 static void mt312_detach(struct dvb_i2c_bus *i2c, void *data)
799 dvb_unregister_frontend(mt312_ioctl, i2c);
805 static int __init mt312_module_init(void)
807 return dvb_register_i2c_device(THIS_MODULE, mt312_attach, mt312_detach);
810 static void __exit mt312_module_exit(void)
812 dvb_unregister_i2c_device(mt312_attach);
815 module_init(mt312_module_init);
816 module_exit(mt312_module_exit);
819 MODULE_PARM(debug,"i");
820 MODULE_PARM_DESC(debug, "enable verbose debug messages");
823 MODULE_DESCRIPTION("MT312 Satellite Channel Decoder Driver");
824 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
825 MODULE_LICENSE("GPL");