2 Driver for STV0297 demodulator
4 Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
5 Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
28 #include "dvb_frontend.h"
31 struct stv0297_state {
33 struct i2c_adapter* i2c;
35 struct dvb_frontend_ops ops;
37 const struct stv0297_config* config;
39 struct dvb_frontend frontend;
41 unsigned long base_freq;
46 #define dprintk(x...) printk(x)
51 #define STV0297_CLOCK_KHZ 28900
53 static u8 init_tab [] = {
142 static int stv0297_writereg (struct stv0297_state* state, u8 reg, u8 data)
145 u8 buf [] = { reg, data };
146 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
148 ret = i2c_transfer (state->i2c, &msg, 1);
151 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
152 "ret == %i)\n", __FUNCTION__, reg, data, ret);
154 return (ret != 1) ? -1 : 0;
157 static int stv0297_readreg (struct stv0297_state* state, u8 reg)
162 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len =
164 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
167 // this device needs a STOP between the register and data
168 if ((ret = i2c_transfer (state->i2c, &msg[0], 1)) != 1) {
169 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
172 if ((ret = i2c_transfer (state->i2c, &msg[1], 1)) != 1) {
173 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
180 static int stv0297_writereg_mask (struct stv0297_state* state, u8 reg, u8 mask, u8 data)
184 val = stv0297_readreg(state, reg);
186 val |= (data & mask);
187 stv0297_writereg(state, reg, val);
192 static int stv0297_readregs (struct stv0297_state* state, u8 reg1, u8 *b, u8 len)
195 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
197 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
200 // this device needs a STOP between the register and data
201 if ((ret = i2c_transfer (state->i2c, &msg[0], 1)) != 1) {
202 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
205 if ((ret = i2c_transfer (state->i2c, &msg[1], 1)) != 1) {
206 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
213 static u32 stv0297_get_symbolrate(struct stv0297_state *state)
217 tmp = stv0297_readreg(state, 0x55);
218 tmp |= stv0297_readreg(state, 0x56) << 8;
219 tmp |= stv0297_readreg(state, 0x57) << 16;
220 tmp |= stv0297_readreg(state, 0x58) << 24;
222 tmp *= STV0297_CLOCK_KHZ;
228 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
232 tmp = 131072L * srate; /* 131072 = 2^17 */
233 tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */
234 tmp = tmp * 8192L; /* 8192 = 2^13 */
236 stv0297_writereg (state, 0x55,(unsigned char)(tmp & 0xFF));
237 stv0297_writereg (state, 0x56,(unsigned char)(tmp>> 8));
238 stv0297_writereg (state, 0x57,(unsigned char)(tmp>>16));
239 stv0297_writereg (state, 0x58,(unsigned char)(tmp>>24));
242 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
246 tmp = (long) fshift *262144L; /* 262144 = 2*18 */
248 tmp *= 1024; /* 1024 = 2*10 */
258 stv0297_writereg(state, 0x60, tmp & 0xFF);
259 stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
262 static void stv0297_set_carrieroffset(struct stv0297_state* state, long offset)
266 /* symrate is hardcoded to 10000 */
267 tmp = offset * 26844L; /* (2**28)/10000 */
272 stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
273 stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
274 stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
275 stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
279 static long stv0297_get_carrieroffset(struct stv0297_state* state)
283 stv0297_writereg(state,0x6B, 0x00);
285 tmp = stv0297_readreg(state, 0x66);
286 tmp |= (stv0297_readreg(state, 0x67) << 8);
287 tmp |= (stv0297_readreg(state, 0x68) << 16);
288 tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
290 tmp *= stv0297_get_symbolrate(state);
297 static void stv0297_set_initialdemodfreq(struct stv0297_state* state, long freq)
302 freq -= STV0297_CLOCK_KHZ;
304 tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
305 tmp = (freq * 1000) / tmp;
309 stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
310 stv0297_writereg(state, 0x21, tmp >> 8);
311 stv0297_writereg(state, 0x20, tmp);
314 static int stv0297_set_qam(struct stv0297_state* state, fe_modulation_t modulation)
343 stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
348 static int stv0297_set_inversion(struct stv0297_state* state, fe_spectral_inversion_t inversion)
365 stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
382 int stv0297_enable_plli2c(struct dvb_frontend* fe)
384 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
386 stv0297_writereg(state, 0x87, 0x78);
387 stv0297_writereg(state, 0x86, 0xc8);
392 static int stv0297_init (struct dvb_frontend* fe)
394 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
398 stv0297_writereg_mask(state, 0x80, 1, 1);
399 stv0297_writereg_mask(state, 0x80, 1, 0);
401 /* reset deinterleaver */
402 stv0297_writereg_mask(state, 0x81, 1, 1);
403 stv0297_writereg_mask(state, 0x81, 1, 0);
405 /* load init table */
406 for (i=0; i<sizeof(init_tab); i+=2) {
407 stv0297_writereg (state, init_tab[i], init_tab[i+1]);
410 /* set a dummy symbol rate */
411 stv0297_set_symbolrate(state, 6900);
413 /* invert AGC1 polarity */
414 stv0297_writereg_mask(state, 0x88, 0x10, 0x10);
416 /* setup bit error counting */
417 stv0297_writereg_mask(state, 0xA0, 0x80, 0x00);
418 stv0297_writereg_mask(state, 0xA0, 0x10, 0x00);
419 stv0297_writereg_mask(state, 0xA0, 0x08, 0x00);
420 stv0297_writereg_mask(state, 0xA0, 0x07, 0x04);
423 stv0297_writereg(state, 0x4a, 0x00);
424 stv0297_writereg(state, 0x4b, state->pwm);
427 if (state->config->pll_init)
428 state->config->pll_init(fe);
433 static int stv0297_sleep(struct dvb_frontend *fe)
435 struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv;
437 stv0297_writereg_mask(state, 0x80, 1, 1);
442 static int stv0297_read_status(struct dvb_frontend* fe, fe_status_t* status)
444 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
446 u8 sync = stv0297_readreg (state, 0xDF);
451 FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
455 static int stv0297_read_ber(struct dvb_frontend* fe, u32* ber)
457 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
460 stv0297_writereg (state, 0xA0, 0x80); // Start Counting bit errors for 4096 Bytes
461 mdelay(25); // Hopefully got 4096 Bytes
462 stv0297_readregs (state, 0xA0, BER, 3);
464 *ber = (BER[2] << 8 | BER[1]) / ( 8 * 4096);
470 static int stv0297_read_signal_strength(struct dvb_frontend* fe, u16* strength)
472 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
475 stv0297_readregs (state, 0x41, STRENGTH, 2);
476 *strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
481 static int stv0297_read_snr(struct dvb_frontend* fe, u16* snr)
483 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
486 stv0297_readregs (state, 0x07, SNR, 2);
487 *snr = SNR[1] << 8 | SNR[0];
492 static int stv0297_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
494 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
496 *ucblocks = (stv0297_readreg (state, 0xD5) << 8)
497 | stv0297_readreg (state, 0xD4);
502 static int stv0297_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters * p)
504 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
511 unsigned long starttime;
512 unsigned long timeout;
513 fe_spectral_inversion_t inversion;
515 switch(p->u.qam.modulation) {
537 // determine inversion dependant parameters
538 inversion = p->inversion;
539 if (state->config->invert)
540 inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
541 carrieroffset = -330;
547 sweeprate = -sweeprate;
548 carrieroffset = -carrieroffset;
556 state->config->pll_set(fe, p);
558 /* clear software interrupts */
559 stv0297_writereg(state, 0x82, 0x0);
561 /* set initial demodulation frequency */
562 stv0297_set_initialdemodfreq(state, 7250);
565 stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
566 stv0297_writereg(state, 0x41, 0x00);
567 stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
568 stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
569 stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
570 stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
571 stv0297_writereg(state, 0x72, 0x00);
572 stv0297_writereg(state, 0x73, 0x00);
573 stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
574 stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
575 stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
578 stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
579 stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
580 stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
581 stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
582 stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
584 /* disable frequency sweep */
585 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
587 /* reset deinterleaver */
588 stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
589 stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
592 stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
593 stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
595 /* reset equaliser */
596 u_threshold = stv0297_readreg(state, 0x00) & 0xf;
597 initial_u = stv0297_readreg(state, 0x01) >> 4;
598 blind_u = stv0297_readreg(state, 0x01) & 0xf;
599 stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
600 stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
601 stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
602 stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
603 stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
605 /* data comes from internal A/D */
606 stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
608 /* clear phase registers */
609 stv0297_writereg(state, 0x63, 0x00);
610 stv0297_writereg(state, 0x64, 0x00);
611 stv0297_writereg(state, 0x65, 0x00);
612 stv0297_writereg(state, 0x66, 0x00);
613 stv0297_writereg(state, 0x67, 0x00);
614 stv0297_writereg(state, 0x68, 0x00);
615 stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
618 stv0297_set_qam(state, p->u.qam.modulation);
619 stv0297_set_symbolrate(state, p->u.qam.symbol_rate/1000);
620 stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
621 stv0297_set_carrieroffset(state, carrieroffset);
622 stv0297_set_inversion(state, inversion);
625 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
626 stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
627 stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
628 stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
629 stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
630 stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
631 stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
632 stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
634 /* wait for WGAGC lock */
636 timeout = jiffies + (200*HZ)/1000;
637 while(time_before(jiffies, timeout)) {
639 if (stv0297_readreg(state, 0x43) & 0x08)
642 if (time_after(jiffies, timeout)) {
647 /* wait for equaliser partial convergence */
648 timeout = jiffies + (50*HZ)/1000;
649 while(time_before(jiffies, timeout)) {
652 if (stv0297_readreg(state, 0x82) & 0x04) {
656 if (time_after(jiffies, timeout)) {
660 /* wait for equaliser full convergence */
661 timeout = jiffies + (delay*HZ)/1000;
662 while(time_before(jiffies, timeout)) {
665 if (stv0297_readreg(state, 0x82) & 0x08) {
669 if (time_after(jiffies, timeout)) {
674 stv0297_writereg_mask(state, 0x6a, 1, 0);
675 stv0297_writereg_mask(state, 0x88, 8, 0);
677 /* wait for main lock */
678 timeout = jiffies + (20*HZ)/1000;
679 while(time_before(jiffies, timeout)) {
682 if (stv0297_readreg(state, 0xDF) & 0x80) {
686 if (time_after(jiffies, timeout)) {
691 /* is it still locked after that delay? */
692 if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
697 stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
698 state->base_freq = p->frequency;
702 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
706 static int stv0297_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters * p)
708 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
711 reg_00 = stv0297_readreg(state, 0x00);
712 reg_83 = stv0297_readreg(state, 0x83);
714 p->frequency = state->base_freq;
715 p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
716 if (state->config->invert)
717 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
718 p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000;
719 p->u.qam.fec_inner = FEC_NONE;
721 switch((reg_00 >> 4) & 0x7) {
723 p->u.qam.modulation = QAM_16;
726 p->u.qam.modulation = QAM_32;
729 p->u.qam.modulation = QAM_128;
732 p->u.qam.modulation = QAM_256;
735 p->u.qam.modulation = QAM_64;
742 static void stv0297_release(struct dvb_frontend* fe)
744 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
748 static struct dvb_frontend_ops stv0297_ops;
750 struct dvb_frontend* stv0297_attach(const struct stv0297_config* config,
751 struct i2c_adapter *i2c, int pwm)
753 struct stv0297_state* state = NULL;
755 /* allocate memory for the internal state */
756 state = (struct stv0297_state*) kmalloc(sizeof(struct stv0297_state), GFP_KERNEL);
760 /* setup the state */
761 state->config = config;
763 memcpy(&state->ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
764 state->base_freq = 0;
767 /* check if the demod is there */
768 if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
771 /* create dvb_frontend */
772 state->frontend.ops = &state->ops;
773 state->frontend.demodulator_priv = state;
774 return &state->frontend;
782 static struct dvb_frontend_ops stv0297_ops = {
785 .name = "ST STV0297 DVB-C",
787 .frequency_min = 64000000,
788 .frequency_max = 1300000000,
789 .frequency_stepsize = 62500,
790 .symbol_rate_min = 870000,
791 .symbol_rate_max = 11700000,
792 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
793 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
795 .release = stv0297_release,
797 .init = stv0297_init,
798 .sleep = stv0297_sleep,
800 .set_frontend = stv0297_set_frontend,
801 .get_frontend = stv0297_get_frontend,
803 .read_status = stv0297_read_status,
804 .read_ber = stv0297_read_ber,
805 .read_signal_strength = stv0297_read_signal_strength,
806 .read_snr = stv0297_read_snr,
807 .read_ucblocks = stv0297_read_ucblocks,
810 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
811 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
812 MODULE_LICENSE("GPL");
814 EXPORT_SYMBOL(stv0297_attach);
815 EXPORT_SYMBOL(stv0297_enable_plli2c);