2 Driver for Philips tda1004xh OFDM Frontend
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 This driver needs a copy of the DLL "ttlcdacc.dll" from the Haupauge or Technotrend
25 windows driver saved as '/usr/lib/hotplug/firmware/tda1004x.bin'.
26 You can also pass the complete file name with the module parameter 'tda1004x_firmware'.
28 Currently the DLL from v2.15a of the technotrend driver is supported. Other versions can
29 be added reasonably painlessly.
31 Windows driver URL: http://www.technotrend.de/
35 #define __KERNEL_SYSCALLS__
36 #include <linux/kernel.h>
37 #include <linux/vmalloc.h>
38 #include <linux/module.h>
39 #include <linux/init.h>
40 #include <linux/string.h>
41 #include <linux/slab.h>
43 #include <linux/unistd.h>
44 #include <linux/fcntl.h>
45 #include <linux/errno.h>
46 #include <linux/syscalls.h>
48 #include "dvb_frontend.h"
49 #include "dvb_functions.h"
51 #ifndef DVB_TDA1004X_FIRMWARE_FILE
52 #define DVB_TDA1004X_FIRMWARE_FILE "/usr/lib/hotplug/firmware/tda1004x.bin"
55 static int tda1004x_debug = 0;
56 static char *tda1004x_firmware = DVB_TDA1004X_FIRMWARE_FILE;
58 #define MC44BC374_ADDRESS 0x65
60 #define TDA1004X_CHIPID 0x00
61 #define TDA1004X_AUTO 0x01
62 #define TDA1004X_IN_CONF1 0x02
63 #define TDA1004X_IN_CONF2 0x03
64 #define TDA1004X_OUT_CONF1 0x04
65 #define TDA1004X_OUT_CONF2 0x05
66 #define TDA1004X_STATUS_CD 0x06
67 #define TDA1004X_CONFC4 0x07
68 #define TDA1004X_DSSPARE2 0x0C
69 #define TDA10045H_CODE_IN 0x0D
70 #define TDA10045H_FWPAGE 0x0E
71 #define TDA1004X_SCAN_CPT 0x10
72 #define TDA1004X_DSP_CMD 0x11
73 #define TDA1004X_DSP_ARG 0x12
74 #define TDA1004X_DSP_DATA1 0x13
75 #define TDA1004X_DSP_DATA2 0x14
76 #define TDA1004X_CONFADC1 0x15
77 #define TDA1004X_CONFC1 0x16
78 #define TDA10045H_S_AGC 0x1a
79 #define TDA10046H_AGC_TUN_LEVEL 0x1a
80 #define TDA1004X_SNR 0x1c
81 #define TDA1004X_CONF_TS1 0x1e
82 #define TDA1004X_CONF_TS2 0x1f
83 #define TDA1004X_CBER_RESET 0x20
84 #define TDA1004X_CBER_MSB 0x21
85 #define TDA1004X_CBER_LSB 0x22
86 #define TDA1004X_CVBER_LUT 0x23
87 #define TDA1004X_VBER_MSB 0x24
88 #define TDA1004X_VBER_MID 0x25
89 #define TDA1004X_VBER_LSB 0x26
90 #define TDA1004X_UNCOR 0x27
92 #define TDA10045H_CONFPLL_P 0x2D
93 #define TDA10045H_CONFPLL_M_MSB 0x2E
94 #define TDA10045H_CONFPLL_M_LSB 0x2F
95 #define TDA10045H_CONFPLL_N 0x30
97 #define TDA10046H_CONFPLL1 0x2D
98 #define TDA10046H_CONFPLL2 0x2F
99 #define TDA10046H_CONFPLL3 0x30
100 #define TDA10046H_TIME_WREF1 0x31
101 #define TDA10046H_TIME_WREF2 0x32
102 #define TDA10046H_TIME_WREF3 0x33
103 #define TDA10046H_TIME_WREF4 0x34
104 #define TDA10046H_TIME_WREF5 0x35
106 #define TDA10045H_UNSURW_MSB 0x31
107 #define TDA10045H_UNSURW_LSB 0x32
108 #define TDA10045H_WREF_MSB 0x33
109 #define TDA10045H_WREF_MID 0x34
110 #define TDA10045H_WREF_LSB 0x35
111 #define TDA10045H_MUXOUT 0x36
112 #define TDA1004X_CONFADC2 0x37
114 #define TDA10045H_IOFFSET 0x38
116 #define TDA10046H_CONF_TRISTATE1 0x3B
117 #define TDA10046H_CONF_TRISTATE2 0x3C
118 #define TDA10046H_CONF_POLARITY 0x3D
119 #define TDA10046H_FREQ_OFFSET 0x3E
120 #define TDA10046H_GPIO_OUT_SEL 0x41
121 #define TDA10046H_GPIO_SELECT 0x42
122 #define TDA10046H_AGC_CONF 0x43
123 #define TDA10046H_AGC_GAINS 0x46
124 #define TDA10046H_AGC_TUN_MIN 0x47
125 #define TDA10046H_AGC_TUN_MAX 0x48
126 #define TDA10046H_AGC_IF_MIN 0x49
127 #define TDA10046H_AGC_IF_MAX 0x4A
129 #define TDA10046H_FREQ_PHY2_MSB 0x4D
130 #define TDA10046H_FREQ_PHY2_LSB 0x4E
132 #define TDA10046H_CVBER_CTRL 0x4F
133 #define TDA10046H_AGC_IF_LEVEL 0x52
134 #define TDA10046H_CODE_CPT 0x57
135 #define TDA10046H_CODE_IN 0x58
138 #define FE_TYPE_TDA10045H 0
139 #define FE_TYPE_TDA10046H 1
141 #define TUNER_TYPE_TD1344 0
142 #define TUNER_TYPE_TD1316 1
144 #define dprintk if (tda1004x_debug) printk
146 static struct dvb_frontend_info tda10045h_info = {
147 .name = "Philips TDA10045H",
149 .frequency_min = 51000000,
150 .frequency_max = 858000000,
151 .frequency_stepsize = 166667,
153 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
154 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
155 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
156 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
159 static struct dvb_frontend_info tda10046h_info = {
160 .name = "Philips TDA10046H",
162 .frequency_min = 51000000,
163 .frequency_max = 858000000,
164 .frequency_stepsize = 166667,
166 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
167 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
168 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
169 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
173 struct tda1004x_state {
187 static struct fwinfo tda10045h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x34cc5,.fw_size = 30555} };
188 static int tda10045h_fwinfo_count = sizeof(tda10045h_fwinfo) / sizeof(struct fwinfo);
190 static struct fwinfo tda10046h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x3c4f9,.fw_size = 24479} };
191 static int tda10046h_fwinfo_count = sizeof(tda10046h_fwinfo) / sizeof(struct fwinfo);
196 static int tda1004x_write_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int data)
199 u8 buf[] = { reg, data };
200 struct i2c_msg msg = { .addr=0, .flags=0, .buf=buf, .len=2 };
202 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
204 msg.addr = tda_state->tda1004x_address;
205 ret = i2c->xfer(i2c, &msg, 1);
208 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
209 __FUNCTION__, reg, data, ret);
211 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
213 return (ret != 1) ? -1 : 0;
216 static int tda1004x_read_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg)
221 struct i2c_msg msg[] = {{ .addr=0, .flags=0, .buf=b0, .len=1},
222 { .addr=0, .flags=I2C_M_RD, .buf=b1, .len = 1}};
224 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
226 msg[0].addr = tda_state->tda1004x_address;
227 msg[1].addr = tda_state->tda1004x_address;
228 ret = i2c->xfer(i2c, msg, 2);
231 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
236 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
241 static int tda1004x_write_mask(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int mask, int data)
244 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
247 // read a byte and check
248 val = tda1004x_read_byte(i2c, tda_state, reg);
256 // write it out again
257 return tda1004x_write_byte(i2c, tda_state, reg, val);
260 static int tda1004x_write_buf(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, unsigned char *buf, int len)
265 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
268 for (i = 0; i < len; i++) {
269 result = tda1004x_write_byte(i2c, tda_state, reg + i, buf[i]);
277 static int tda1004x_enable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
280 dprintk("%s\n", __FUNCTION__);
282 result = tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 2);
287 static int tda1004x_disable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
290 dprintk("%s\n", __FUNCTION__);
292 return tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 0);
296 static int tda10045h_set_bandwidth(struct dvb_i2c_bus *i2c,
297 struct tda1004x_state *tda_state,
298 fe_bandwidth_t bandwidth)
300 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
301 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
302 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
305 case BANDWIDTH_6_MHZ:
306 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
307 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
310 case BANDWIDTH_7_MHZ:
311 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x80);
312 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
315 case BANDWIDTH_8_MHZ:
316 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
317 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
324 tda1004x_write_byte(i2c, tda_state, TDA10045H_IOFFSET, 0);
331 static int tda10046h_set_bandwidth(struct dvb_i2c_bus *i2c,
332 struct tda1004x_state *tda_state,
333 fe_bandwidth_t bandwidth)
335 static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
336 static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
337 static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
340 case BANDWIDTH_6_MHZ:
341 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
342 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
345 case BANDWIDTH_7_MHZ:
346 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
347 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
350 case BANDWIDTH_8_MHZ:
351 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
352 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0xFF);
364 static int tda1004x_fwupload(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
367 struct i2c_msg fw_msg = {.addr = 0,.flags = 0,.buf = fw_buf,.len = 0 };
368 unsigned char *firmware = NULL;
373 int fw_pos, fw_offset;
375 mm_segment_t fs = get_fs();
376 int dspCodeCounterReg=0, dspCodeInReg=0, dspVersion=0;
378 struct fwinfo* fwInfo = NULL;
379 unsigned long timeout;
382 switch(tda_state->fe_type) {
383 case FE_TYPE_TDA10045H:
384 dspCodeCounterReg = TDA10045H_FWPAGE;
385 dspCodeInReg = TDA10045H_CODE_IN;
387 fwInfoCount = tda10045h_fwinfo_count;
388 fwInfo = tda10045h_fwinfo;
391 case FE_TYPE_TDA10046H:
392 dspCodeCounterReg = TDA10046H_CODE_CPT;
393 dspCodeInReg = TDA10046H_CODE_IN;
395 fwInfoCount = tda10046h_fwinfo_count;
396 fwInfo = tda10046h_fwinfo;
402 fd = open(tda1004x_firmware, 0, 0);
404 printk("%s: Unable to open firmware %s\n", __FUNCTION__,
408 filesize = lseek(fd, 0L, 2);
410 printk("%s: Firmware %s is empty\n", __FUNCTION__,
416 // find extraction parameters for firmware
417 for (fwinfo_idx = 0; fwinfo_idx < fwInfoCount; fwinfo_idx++) {
418 if (fwInfo[fwinfo_idx].file_size == filesize)
421 if (fwinfo_idx >= fwInfoCount) {
422 printk("%s: Unsupported firmware %s\n", __FUNCTION__, tda1004x_firmware);
426 fw_size = fwInfo[fwinfo_idx].fw_size;
427 fw_offset = fwInfo[fwinfo_idx].fw_offset;
429 // allocate buffer for it
430 firmware = vmalloc(fw_size);
431 if (firmware == NULL) {
432 printk("%s: Out of memory loading firmware\n",
439 lseek(fd, fw_offset, 0);
440 if (read(fd, firmware, fw_size) != fw_size) {
441 printk("%s: Failed to read firmware\n", __FUNCTION__);
449 // set some valid bandwith parameters before uploading
450 switch(tda_state->fe_type) {
451 case FE_TYPE_TDA10045H:
453 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0);
454 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
455 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
459 tda10045h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ);
462 case FE_TYPE_TDA10046H:
464 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0);
465 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 1, 0);
469 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10);
470 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0);
471 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99);
472 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
473 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
474 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
478 // do the firmware upload
479 tda1004x_write_byte(i2c, tda_state, dspCodeCounterReg, 0); // clear code counter
480 fw_msg.addr = tda_state->tda1004x_address;
482 while (fw_pos != fw_size) {
484 // work out how much to send this time
485 tx_size = fw_size - fw_pos;
486 if (tx_size > 0x10) {
491 fw_buf[0] = dspCodeInReg;
492 memcpy(fw_buf + 1, firmware + fw_pos, tx_size);
493 fw_msg.len = tx_size + 1;
494 if (i2c->xfer(i2c, &fw_msg, 1) != 1) {
495 printk("tda1004x: Error during firmware upload\n");
501 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, fw_pos);
505 // wait for DSP to initialise
506 switch(tda_state->fe_type) {
507 case FE_TYPE_TDA10045H:
508 // DSPREADY doesn't seem to work on the TDA10045H
512 case FE_TYPE_TDA10046H:
513 timeout = jiffies + HZ;
514 while(!(tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD) & 0x20)) {
515 if (time_after(jiffies, timeout)) {
516 printk("tda1004x: DSP failed to initialised.\n");
525 // check upload was OK
526 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
527 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSP_CMD, 0x67);
528 if ((tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA1) != 0x67) ||
529 (tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA2) != dspVersion)) {
530 printk("%s: firmware upload failed!\n", __FUNCTION__);
539 static int tda10045h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
541 struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = NULL,.len = 0 };
542 static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
544 dprintk("%s\n", __FUNCTION__);
546 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
548 // Disable the MC44BC374C
549 tda1004x_enable_tuner_i2c(i2c, tda_state);
550 tuner_msg.addr = MC44BC374_ADDRESS;
551 tuner_msg.buf = disable_mc44BC374c;
552 tuner_msg.len = sizeof(disable_mc44BC374c);
553 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
554 i2c->xfer(i2c, &tuner_msg, 1);
556 tda1004x_disable_tuner_i2c(i2c, tda_state);
559 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
560 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
561 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0); // no frequency inversion
562 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
563 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
564 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
565 tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
566 tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
567 tda1004x_write_mask(i2c, tda_state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
568 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
569 tda1004x_write_byte(i2c, tda_state, TDA1004X_CONFADC1, 0x2e);
577 static int tda10046h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
579 struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = NULL,.len = 0 };
580 static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
582 dprintk("%s\n", __FUNCTION__);
584 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0); // wake up the chip
586 // Disable the MC44BC374C
587 tda1004x_enable_tuner_i2c(i2c, tda_state);
588 tuner_msg.addr = MC44BC374_ADDRESS;
589 tuner_msg.buf = disable_mc44BC374c;
590 tuner_msg.len = sizeof(disable_mc44BC374c);
591 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
592 i2c->xfer(i2c, &tuner_msg, 1);
594 tda1004x_disable_tuner_i2c(i2c, tda_state);
597 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
598 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0x40); // TT TDA10046H needs inversion ON
599 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
600 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
601 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10); // PLL M = 10
602 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
603 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
604 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
605 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
606 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_CONF, 0); // AGC setup
607 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
608 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MIN, 0); // }
609 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
610 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MIN, 0); // }
611 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MAX, 0xff); // }
612 tda1004x_write_mask(i2c, tda_state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
613 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
614 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
615 tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
616 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
617 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
618 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
619 tda1004x_write_byte(i2c, tda_state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
620 tda1004x_write_mask(i2c, tda_state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
621 tda10046h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
629 static int tda1004x_encode_fec(int fec)
631 // convert known FEC values
649 static int tda1004x_decode_fec(int tdafec)
651 // convert known FEC values
669 static int tda1004x_set_frequency(struct dvb_i2c_bus *i2c,
670 struct tda1004x_state *tda_state,
671 struct dvb_frontend_parameters *fe_params)
674 struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=tuner_buf, .len=sizeof(tuner_buf) };
675 int tuner_frequency = 0;
677 int counter, counter2;
679 dprintk("%s\n", __FUNCTION__);
681 // setup the frequency buffer
682 switch (tda_state->tuner_type) {
683 case TUNER_TYPE_TD1344:
685 // setup tuner buffer
686 // ((Fif+((1000000/6)/2)) + Finput)/(1000000/6)
688 (((fe_params->frequency / 1000) * 6) + 217502) / 1000;
689 tuner_buf[0] = tuner_frequency >> 8;
690 tuner_buf[1] = tuner_frequency & 0xff;
692 if (fe_params->frequency < 550000000) {
699 tda1004x_enable_tuner_i2c(i2c, tda_state);
700 tuner_msg.addr = tda_state->tuner_address;
702 i2c->xfer(i2c, &tuner_msg, 1);
704 // wait for it to finish
706 tuner_msg.flags = I2C_M_RD;
709 while (counter++ < 100) {
710 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
711 if (tuner_buf[0] & 0x40) {
722 tda1004x_disable_tuner_i2c(i2c, tda_state);
725 case TUNER_TYPE_TD1316:
726 // determine charge pump
727 tuner_frequency = fe_params->frequency + 36130000;
728 if (tuner_frequency < 87000000) {
730 } else if (tuner_frequency < 130000000) {
732 } else if (tuner_frequency < 160000000) {
734 } else if (tuner_frequency < 200000000) {
736 } else if (tuner_frequency < 290000000) {
738 } else if (tuner_frequency < 420000000) {
740 } else if (tuner_frequency < 480000000) {
742 } else if (tuner_frequency < 620000000) {
744 } else if (tuner_frequency < 830000000) {
746 } else if (tuner_frequency < 895000000) {
753 if (fe_params->frequency < 49000000) {
755 } else if (fe_params->frequency < 159000000) {
757 } else if (fe_params->frequency < 444000000) {
759 } else if (fe_params->frequency < 861000000) {
766 switch (fe_params->u.ofdm.bandwidth) {
767 case BANDWIDTH_6_MHZ:
771 case BANDWIDTH_7_MHZ:
775 case BANDWIDTH_8_MHZ:
784 // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
786 (((fe_params->frequency / 1000) * 6) + 217280) / 1000;
788 // setup tuner buffer
789 tuner_buf[0] = tuner_frequency >> 8;
790 tuner_buf[1] = tuner_frequency & 0xff;
792 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
795 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
797 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10);
798 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x80, 0);
799 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0);
801 // disable agc_conf[2]
802 tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 0);
804 tda1004x_enable_tuner_i2c(i2c, tda_state);
805 tuner_msg.addr = tda_state->tuner_address;
807 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
811 tda1004x_disable_tuner_i2c(i2c, tda_state);
812 if (tda_state->fe_type == FE_TYPE_TDA10046H)
813 tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 4);
820 dprintk("%s: success\n", __FUNCTION__);
826 static int tda1004x_set_fe(struct dvb_i2c_bus *i2c,
827 struct tda1004x_state *tda_state,
828 struct dvb_frontend_parameters *fe_params)
833 dprintk("%s\n", __FUNCTION__);
836 if ((tmp = tda1004x_set_frequency(i2c, tda_state, fe_params)) < 0)
839 // hardcoded to use auto as much as possible
840 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
841 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
842 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
844 // Set standard params.. or put them to auto
845 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
846 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
847 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
848 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
849 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 1); // enable auto
850 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
851 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
852 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
854 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 0); // disable auto
857 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
858 if (tmp < 0) return tmp;
859 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 7, tmp);
862 if (fe_params->u.ofdm.code_rate_LP != FEC_NONE) {
863 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
864 if (tmp < 0) return tmp;
865 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
869 switch (fe_params->u.ofdm.constellation) {
871 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 0);
875 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 1);
879 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 2);
887 switch (fe_params->u.ofdm.hierarchy_information) {
889 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
893 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
897 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
901 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
910 switch(tda_state->fe_type) {
911 case FE_TYPE_TDA10045H:
912 tda10045h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
915 case FE_TYPE_TDA10046H:
916 tda10046h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
920 // need to invert the inversion for TT TDA10046H
921 inversion = fe_params->inversion;
922 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
923 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
929 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0);
933 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0x20);
940 // set guard interval
941 switch (fe_params->u.ofdm.guard_interval) {
942 case GUARD_INTERVAL_1_32:
943 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
944 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
947 case GUARD_INTERVAL_1_16:
948 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
949 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
952 case GUARD_INTERVAL_1_8:
953 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
954 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
957 case GUARD_INTERVAL_1_4:
958 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
959 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
962 case GUARD_INTERVAL_AUTO:
963 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 2);
964 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
971 // set transmission mode
972 switch (fe_params->u.ofdm.transmission_mode) {
973 case TRANSMISSION_MODE_2K:
974 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
975 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
978 case TRANSMISSION_MODE_8K:
979 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
980 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
983 case TRANSMISSION_MODE_AUTO:
984 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 4);
985 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0);
993 switch(tda_state->fe_type) {
994 case FE_TYPE_TDA10045H:
995 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
996 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
1000 case FE_TYPE_TDA10046H:
1001 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x40, 0x40);
1011 static int tda1004x_get_fe(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, struct dvb_frontend_parameters *fe_params)
1014 dprintk("%s\n", __FUNCTION__);
1017 fe_params->inversion = INVERSION_OFF;
1018 if (tda1004x_read_byte(i2c, tda_state, TDA1004X_CONFC1) & 0x20) {
1019 fe_params->inversion = INVERSION_ON;
1022 // need to invert the inversion for TT TDA10046H
1023 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
1024 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
1028 switch(tda_state->fe_type) {
1029 case FE_TYPE_TDA10045H:
1030 switch (tda1004x_read_byte(i2c, tda_state, TDA10045H_WREF_LSB)) {
1032 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1035 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1038 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1043 case FE_TYPE_TDA10046H:
1044 switch (tda1004x_read_byte(i2c, tda_state, TDA10046H_TIME_WREF1)) {
1046 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1049 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1052 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1059 fe_params->u.ofdm.code_rate_HP =
1060 tda1004x_decode_fec(tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) & 7);
1061 fe_params->u.ofdm.code_rate_LP =
1062 tda1004x_decode_fec((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) >> 3) & 7);
1065 switch (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 3) {
1067 fe_params->u.ofdm.constellation = QPSK;
1070 fe_params->u.ofdm.constellation = QAM_16;
1073 fe_params->u.ofdm.constellation = QAM_64;
1077 // transmission mode
1078 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1079 if (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x10) {
1080 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1084 switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
1086 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1089 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1092 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1095 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1100 switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
1102 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1105 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
1108 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
1111 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
1120 static int tda1004x_read_status(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, fe_status_t * fe_status)
1126 dprintk("%s\n", __FUNCTION__);
1129 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD);
1136 if (status & 4) *fe_status |= FE_HAS_SIGNAL;
1137 if (status & 2) *fe_status |= FE_HAS_CARRIER;
1138 if (status & 8) *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1140 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1141 // is getting anything valid
1142 if (!(*fe_status & FE_HAS_VITERBI)) {
1144 cber = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1145 if (cber == -1) return -EIO;
1146 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1147 if (status == -1) return -EIO;
1148 cber |= (status << 8);
1149 tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1151 if (cber != 65535) {
1152 *fe_status |= FE_HAS_VITERBI;
1156 // if we DO have some valid VITERBI output, but don't already have SYNC
1157 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1158 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1160 vber = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_LSB);
1161 if (vber == -1) return -EIO;
1162 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MID);
1163 if (status == -1) return -EIO;
1164 vber |= (status << 8);
1165 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MSB);
1166 if (status == -1) return -EIO;
1167 vber |= ((status << 16) & 0x0f);
1168 tda1004x_read_byte(i2c, tda_state, TDA1004X_CVBER_LUT);
1170 // if RS has passed some valid TS packets, then we must be
1171 // getting some SYNC bytes
1173 *fe_status |= FE_HAS_SYNC;
1178 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1182 static int tda1004x_read_signal_strength(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * signal)
1187 dprintk("%s\n", __FUNCTION__);
1189 // determine the register to use
1190 switch(tda_state->fe_type) {
1191 case FE_TYPE_TDA10045H:
1192 reg = TDA10045H_S_AGC;
1195 case FE_TYPE_TDA10046H:
1196 reg = TDA10046H_AGC_IF_LEVEL;
1201 tmp = tda1004x_read_byte(i2c, tda_state, reg);
1206 *signal = (tmp << 8) | tmp;
1207 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1212 static int tda1004x_read_snr(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * snr)
1216 dprintk("%s\n", __FUNCTION__);
1219 tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_SNR);
1227 *snr = ((tmp << 8) | tmp);
1228 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1232 static int tda1004x_read_ucblocks(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ucblocks)
1238 dprintk("%s\n", __FUNCTION__);
1240 // read the UCBLOCKS and reset
1242 tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1246 while (counter++ < 5) {
1247 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1248 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1249 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1251 tmp2 = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1255 if ((tmp2 < tmp) || (tmp2 == 0))
1263 *ucblocks = 0xffffffff;
1265 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1269 static int tda1004x_read_ber(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ber)
1273 dprintk("%s\n", __FUNCTION__);
1276 tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1277 if (tmp < 0) return -EIO;
1279 tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1280 if (tmp < 0) return -EIO;
1282 tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1285 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1289 static int tda1004x_sleep(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state)
1291 switch(tda_state->fe_type) {
1292 case FE_TYPE_TDA10045H:
1293 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0x10);
1296 case FE_TYPE_TDA10046H:
1297 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 1);
1305 static int tda1004x_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
1308 struct dvb_i2c_bus *i2c = fe->i2c;
1309 struct tda1004x_state *tda_state = (struct tda1004x_state *) fe->data;
1311 dprintk("%s: cmd=0x%x\n", __FUNCTION__, cmd);
1315 switch(tda_state->fe_type) {
1316 case FE_TYPE_TDA10045H:
1317 memcpy(arg, &tda10045h_info, sizeof(struct dvb_frontend_info));
1320 case FE_TYPE_TDA10046H:
1321 memcpy(arg, &tda10046h_info, sizeof(struct dvb_frontend_info));
1326 case FE_READ_STATUS:
1327 return tda1004x_read_status(i2c, tda_state, (fe_status_t *) arg);
1330 return tda1004x_read_ber(i2c, tda_state, (u32 *) arg);
1332 case FE_READ_SIGNAL_STRENGTH:
1333 return tda1004x_read_signal_strength(i2c, tda_state, (u16 *) arg);
1336 return tda1004x_read_snr(i2c, tda_state, (u16 *) arg);
1338 case FE_READ_UNCORRECTED_BLOCKS:
1339 return tda1004x_read_ucblocks(i2c, tda_state, (u32 *) arg);
1341 case FE_SET_FRONTEND:
1342 return tda1004x_set_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1344 case FE_GET_FRONTEND:
1345 return tda1004x_get_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1348 tda_state->initialised = 0;
1349 return tda1004x_sleep(i2c, tda_state);
1353 // don't bother reinitialising
1354 if (tda_state->initialised)
1357 // OK, perform initialisation
1358 switch(tda_state->fe_type) {
1359 case FE_TYPE_TDA10045H:
1360 status = tda10045h_init(i2c, tda_state);
1363 case FE_TYPE_TDA10046H:
1364 status = tda10046h_init(i2c, tda_state);
1368 tda_state->initialised = 1;
1371 case FE_GET_TUNE_SETTINGS:
1373 struct dvb_frontend_tune_settings* fesettings = (struct dvb_frontend_tune_settings*) arg;
1374 fesettings->min_delay_ms = 800;
1375 fesettings->step_size = 166667;
1376 fesettings->max_drift = 166667*2;
1388 static int tda1004x_attach(struct dvb_i2c_bus *i2c, void **data)
1390 int tda1004x_address = -1;
1391 int tuner_address = -1;
1393 int tuner_type = -1;
1394 struct tda1004x_state tda_state;
1395 struct tda1004x_state* ptda_state;
1396 struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=NULL, .len=0 };
1397 static u8 td1344_init[] = { 0x0b, 0xf5, 0x88, 0xab };
1398 static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
1399 static u8 td1316_init_tda10046h[] = { 0x0b, 0xf5, 0x80, 0xab };
1402 dprintk("%s\n", __FUNCTION__);
1404 // probe for tda10045h
1405 if (tda1004x_address == -1) {
1406 tda_state.tda1004x_address = 0x08;
1407 if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x25) {
1408 tda1004x_address = 0x08;
1409 fe_type = FE_TYPE_TDA10045H;
1410 printk("tda1004x: Detected Philips TDA10045H.\n");
1414 // probe for tda10046h
1415 if (tda1004x_address == -1) {
1416 tda_state.tda1004x_address = 0x08;
1417 if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x46) {
1418 tda1004x_address = 0x08;
1419 fe_type = FE_TYPE_TDA10046H;
1420 printk("tda1004x: Detected Philips TDA10046H.\n");
1424 // did we find a frontend?
1425 if (tda1004x_address == -1) {
1429 // enable access to the tuner
1430 tda1004x_enable_tuner_i2c(i2c, &tda_state);
1432 // check for a TD1344 first
1433 if (tuner_address == -1) {
1434 tuner_msg.addr = 0x61;
1435 tuner_msg.buf = td1344_init;
1436 tuner_msg.len = sizeof(td1344_init);
1437 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1439 tuner_address = 0x61;
1440 tuner_type = TUNER_TYPE_TD1344;
1441 printk("tda1004x: Detected Philips TD1344 tuner.\n");
1445 // OK, try a TD1316 on address 0x63
1446 if (tuner_address == -1) {
1447 tuner_msg.addr = 0x63;
1448 tuner_msg.buf = td1316_init;
1449 tuner_msg.len = sizeof(td1316_init);
1450 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1452 tuner_address = 0x63;
1453 tuner_type = TUNER_TYPE_TD1316;
1454 printk("tda1004x: Detected Philips TD1316 tuner.\n");
1458 // OK, TD1316 again, on address 0x60 (TDA10046H)
1459 if (tuner_address == -1) {
1460 tuner_msg.addr = 0x60;
1461 tuner_msg.buf = td1316_init_tda10046h;
1462 tuner_msg.len = sizeof(td1316_init_tda10046h);
1463 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1465 tuner_address = 0x60;
1466 tuner_type = TUNER_TYPE_TD1316;
1467 printk("tda1004x: Detected Philips TD1316 tuner.\n");
1470 tda1004x_disable_tuner_i2c(i2c, &tda_state);
1472 // did we find a tuner?
1473 if (tuner_address == -1) {
1474 printk("tda1004x: Detected, but with unknown tuner.\n");
1479 tda_state.tda1004x_address = tda1004x_address;
1480 tda_state.fe_type = fe_type;
1481 tda_state.tuner_address = tuner_address;
1482 tda_state.tuner_type = tuner_type;
1483 tda_state.initialised = 0;
1486 if ((status = tda1004x_fwupload(i2c, &tda_state)) != 0) return status;
1488 // create the real state we'll be passing about
1489 if ((ptda_state = (struct tda1004x_state*) kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL)) == NULL) {
1492 memcpy(ptda_state, &tda_state, sizeof(struct tda1004x_state));
1496 switch(tda_state.fe_type) {
1497 case FE_TYPE_TDA10045H:
1498 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10045h_info);
1500 case FE_TYPE_TDA10046H:
1501 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10046h_info);
1504 // should not get here
1510 void tda1004x_detach(struct dvb_i2c_bus *i2c, void *data)
1512 dprintk("%s\n", __FUNCTION__);
1515 dvb_unregister_frontend(tda1004x_ioctl, i2c);
1520 int __init init_tda1004x(void)
1522 return dvb_register_i2c_device(THIS_MODULE, tda1004x_attach, tda1004x_detach);
1527 void __exit exit_tda1004x(void)
1529 dvb_unregister_i2c_device(tda1004x_attach);
1532 module_init(init_tda1004x);
1533 module_exit(exit_tda1004x);
1535 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Frontend");
1536 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1537 MODULE_LICENSE("GPL");
1539 MODULE_PARM(tda1004x_debug, "i");
1540 MODULE_PARM_DESC(tda1004x_debug, "enable verbose debug messages");
1542 MODULE_PARM(tda1004x_firmware, "s");
1543 MODULE_PARM_DESC(tda1004x_firmware, "Where to find the firmware file");