2 Driver for Philips tda1004xh OFDM Frontend
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 This driver needs a copy of the DLL "ttlcdacc.dll" from the Haupauge or Technotrend
25 windows driver saved as '/usr/lib/hotplug/firmware/tda1004x.bin'.
26 You can also pass the complete file name with the module parameter 'tda1004x_firmware'.
28 Currently the DLL from v2.15a of the technotrend driver is supported. Other versions can
29 be added reasonably painlessly.
31 Windows driver URL: http://www.technotrend.de/
35 #define __KERNEL_SYSCALLS__
36 #include <linux/kernel.h>
37 #include <linux/vmalloc.h>
38 #include <linux/module.h>
39 #include <linux/init.h>
40 #include <linux/string.h>
41 #include <linux/slab.h>
43 #include <linux/unistd.h>
44 #include <linux/fcntl.h>
45 #include <linux/errno.h>
46 #include <linux/syscalls.h>
48 #include "dvb_frontend.h"
49 #include "dvb_functions.h"
51 #ifndef DVB_TDA1004X_FIRMWARE_FILE
52 #define DVB_TDA1004X_FIRMWARE_FILE "/usr/lib/hotplug/firmware/tda1004x.bin"
55 static int tda1004x_debug = 0;
56 static char *tda1004x_firmware = DVB_TDA1004X_FIRMWARE_FILE;
58 #define MC44BC374_ADDRESS 0x65
60 #define TDA1004X_CHIPID 0x00
61 #define TDA1004X_AUTO 0x01
62 #define TDA1004X_IN_CONF1 0x02
63 #define TDA1004X_IN_CONF2 0x03
64 #define TDA1004X_OUT_CONF1 0x04
65 #define TDA1004X_OUT_CONF2 0x05
66 #define TDA1004X_STATUS_CD 0x06
67 #define TDA1004X_CONFC4 0x07
68 #define TDA1004X_DSSPARE2 0x0C
69 #define TDA10045H_CODE_IN 0x0D
70 #define TDA10045H_FWPAGE 0x0E
71 #define TDA1004X_SCAN_CPT 0x10
72 #define TDA1004X_DSP_CMD 0x11
73 #define TDA1004X_DSP_ARG 0x12
74 #define TDA1004X_DSP_DATA1 0x13
75 #define TDA1004X_DSP_DATA2 0x14
76 #define TDA1004X_CONFADC1 0x15
77 #define TDA1004X_CONFC1 0x16
78 #define TDA10045H_S_AGC 0x1a
79 #define TDA10046H_AGC_TUN_LEVEL 0x1a
80 #define TDA1004X_SNR 0x1c
81 #define TDA1004X_CONF_TS1 0x1e
82 #define TDA1004X_CONF_TS2 0x1f
83 #define TDA1004X_CBER_RESET 0x20
84 #define TDA1004X_CBER_MSB 0x21
85 #define TDA1004X_CBER_LSB 0x22
86 #define TDA1004X_CVBER_LUT 0x23
87 #define TDA1004X_VBER_MSB 0x24
88 #define TDA1004X_VBER_MID 0x25
89 #define TDA1004X_VBER_LSB 0x26
90 #define TDA1004X_UNCOR 0x27
92 #define TDA10045H_CONFPLL_P 0x2D
93 #define TDA10045H_CONFPLL_M_MSB 0x2E
94 #define TDA10045H_CONFPLL_M_LSB 0x2F
95 #define TDA10045H_CONFPLL_N 0x30
97 #define TDA10046H_CONFPLL1 0x2D
98 #define TDA10046H_CONFPLL2 0x2F
99 #define TDA10046H_CONFPLL3 0x30
100 #define TDA10046H_TIME_WREF1 0x31
101 #define TDA10046H_TIME_WREF2 0x32
102 #define TDA10046H_TIME_WREF3 0x33
103 #define TDA10046H_TIME_WREF4 0x34
104 #define TDA10046H_TIME_WREF5 0x35
106 #define TDA10045H_UNSURW_MSB 0x31
107 #define TDA10045H_UNSURW_LSB 0x32
108 #define TDA10045H_WREF_MSB 0x33
109 #define TDA10045H_WREF_MID 0x34
110 #define TDA10045H_WREF_LSB 0x35
111 #define TDA10045H_MUXOUT 0x36
112 #define TDA1004X_CONFADC2 0x37
114 #define TDA10045H_IOFFSET 0x38
116 #define TDA10046H_CONF_TRISTATE1 0x3B
117 #define TDA10046H_CONF_TRISTATE2 0x3C
118 #define TDA10046H_CONF_POLARITY 0x3D
119 #define TDA10046H_FREQ_OFFSET 0x3E
120 #define TDA10046H_GPIO_OUT_SEL 0x41
121 #define TDA10046H_GPIO_SELECT 0x42
122 #define TDA10046H_AGC_CONF 0x43
123 #define TDA10046H_AGC_GAINS 0x46
124 #define TDA10046H_AGC_TUN_MIN 0x47
125 #define TDA10046H_AGC_TUN_MAX 0x48
126 #define TDA10046H_AGC_IF_MIN 0x49
127 #define TDA10046H_AGC_IF_MAX 0x4A
129 #define TDA10046H_FREQ_PHY2_MSB 0x4D
130 #define TDA10046H_FREQ_PHY2_LSB 0x4E
132 #define TDA10046H_CVBER_CTRL 0x4F
133 #define TDA10046H_AGC_IF_LEVEL 0x52
134 #define TDA10046H_CODE_CPT 0x57
135 #define TDA10046H_CODE_IN 0x58
138 #define FE_TYPE_TDA10045H 0
139 #define FE_TYPE_TDA10046H 1
141 #define TUNER_TYPE_TD1344 0
142 #define TUNER_TYPE_TD1316 1
144 #define dprintk if (tda1004x_debug) printk
146 static struct dvb_frontend_info tda10045h_info = {
147 .name = "Philips TDA10045H",
149 .frequency_min = 51000000,
150 .frequency_max = 858000000,
151 .frequency_stepsize = 166667,
153 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
154 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
155 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
156 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
159 static struct dvb_frontend_info tda10046h_info = {
160 .name = "Philips TDA10046H",
162 .frequency_min = 51000000,
163 .frequency_max = 858000000,
164 .frequency_stepsize = 166667,
166 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
167 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
168 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
169 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
173 struct tda1004x_state {
187 static struct fwinfo tda10045h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x34cc5,.fw_size = 30555} };
188 static int tda10045h_fwinfo_count = sizeof(tda10045h_fwinfo) / sizeof(struct fwinfo);
190 static struct fwinfo tda10046h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x3c4f9,.fw_size = 24479} };
191 static int tda10046h_fwinfo_count = sizeof(tda10046h_fwinfo) / sizeof(struct fwinfo);
195 static int tda1004x_write_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int data)
198 u8 buf[] = { reg, data };
199 struct i2c_msg msg = { .addr=0, .flags=0, .buf=buf, .len=2 };
201 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
203 msg.addr = tda_state->tda1004x_address;
204 ret = i2c->xfer(i2c, &msg, 1);
207 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
208 __FUNCTION__, reg, data, ret);
210 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
212 return (ret != 1) ? -1 : 0;
215 static int tda1004x_read_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg)
220 struct i2c_msg msg[] = {{ .addr=0, .flags=0, .buf=b0, .len=1},
221 { .addr=0, .flags=I2C_M_RD, .buf=b1, .len = 1}};
223 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
225 msg[0].addr = tda_state->tda1004x_address;
226 msg[1].addr = tda_state->tda1004x_address;
227 ret = i2c->xfer(i2c, msg, 2);
230 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
235 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
240 static int tda1004x_write_mask(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int mask, int data)
243 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
246 // read a byte and check
247 val = tda1004x_read_byte(i2c, tda_state, reg);
255 // write it out again
256 return tda1004x_write_byte(i2c, tda_state, reg, val);
259 static int tda1004x_write_buf(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, unsigned char *buf, int len)
264 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
267 for (i = 0; i < len; i++) {
268 result = tda1004x_write_byte(i2c, tda_state, reg + i, buf[i]);
276 static int tda1004x_enable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
279 dprintk("%s\n", __FUNCTION__);
281 result = tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 2);
286 static int tda1004x_disable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
289 dprintk("%s\n", __FUNCTION__);
291 return tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 0);
295 static int tda10045h_set_bandwidth(struct dvb_i2c_bus *i2c,
296 struct tda1004x_state *tda_state,
297 fe_bandwidth_t bandwidth)
299 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
300 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
301 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
304 case BANDWIDTH_6_MHZ:
305 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
306 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
309 case BANDWIDTH_7_MHZ:
310 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x80);
311 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
314 case BANDWIDTH_8_MHZ:
315 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
316 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
323 tda1004x_write_byte(i2c, tda_state, TDA10045H_IOFFSET, 0);
330 static int tda10046h_set_bandwidth(struct dvb_i2c_bus *i2c,
331 struct tda1004x_state *tda_state,
332 fe_bandwidth_t bandwidth)
334 static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
335 static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
336 static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
339 case BANDWIDTH_6_MHZ:
340 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
341 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
344 case BANDWIDTH_7_MHZ:
345 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
346 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
349 case BANDWIDTH_8_MHZ:
350 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
351 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0xFF);
363 static int tda1004x_fwupload(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
366 struct i2c_msg fw_msg = {.addr = 0,.flags = 0,.buf = fw_buf,.len = 0 };
367 unsigned char *firmware = NULL;
372 int fw_pos, fw_offset;
374 mm_segment_t fs = get_fs();
375 int dspCodeCounterReg=0, dspCodeInReg=0, dspVersion=0;
377 struct fwinfo* fwInfo = NULL;
378 unsigned long timeout;
381 switch(tda_state->fe_type) {
382 case FE_TYPE_TDA10045H:
383 dspCodeCounterReg = TDA10045H_FWPAGE;
384 dspCodeInReg = TDA10045H_CODE_IN;
386 fwInfoCount = tda10045h_fwinfo_count;
387 fwInfo = tda10045h_fwinfo;
390 case FE_TYPE_TDA10046H:
391 dspCodeCounterReg = TDA10046H_CODE_CPT;
392 dspCodeInReg = TDA10046H_CODE_IN;
394 fwInfoCount = tda10046h_fwinfo_count;
395 fwInfo = tda10046h_fwinfo;
401 fd = open(tda1004x_firmware, 0, 0);
403 printk("%s: Unable to open firmware %s\n", __FUNCTION__,
407 filesize = lseek(fd, 0L, 2);
409 printk("%s: Firmware %s is empty\n", __FUNCTION__,
415 // find extraction parameters for firmware
416 for (fwinfo_idx = 0; fwinfo_idx < fwInfoCount; fwinfo_idx++) {
417 if (fwInfo[fwinfo_idx].file_size == filesize)
420 if (fwinfo_idx >= fwInfoCount) {
421 printk("%s: Unsupported firmware %s\n", __FUNCTION__, tda1004x_firmware);
425 fw_size = fwInfo[fwinfo_idx].fw_size;
426 fw_offset = fwInfo[fwinfo_idx].fw_offset;
428 // allocate buffer for it
429 firmware = vmalloc(fw_size);
430 if (firmware == NULL) {
431 printk("%s: Out of memory loading firmware\n",
438 lseek(fd, fw_offset, 0);
439 if (read(fd, firmware, fw_size) != fw_size) {
440 printk("%s: Failed to read firmware\n", __FUNCTION__);
448 // set some valid bandwith parameters before uploading
449 switch(tda_state->fe_type) {
450 case FE_TYPE_TDA10045H:
452 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0);
453 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
454 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
458 tda10045h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ);
461 case FE_TYPE_TDA10046H:
463 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0);
464 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 1, 0);
468 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10);
469 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0);
470 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99);
471 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
472 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
473 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
477 // do the firmware upload
478 tda1004x_write_byte(i2c, tda_state, dspCodeCounterReg, 0); // clear code counter
479 fw_msg.addr = tda_state->tda1004x_address;
481 while (fw_pos != fw_size) {
483 // work out how much to send this time
484 tx_size = fw_size - fw_pos;
485 if (tx_size > 0x10) {
490 fw_buf[0] = dspCodeInReg;
491 memcpy(fw_buf + 1, firmware + fw_pos, tx_size);
492 fw_msg.len = tx_size + 1;
493 if (i2c->xfer(i2c, &fw_msg, 1) != 1) {
494 printk("tda1004x: Error during firmware upload\n");
500 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, fw_pos);
504 // wait for DSP to initialise
505 switch(tda_state->fe_type) {
506 case FE_TYPE_TDA10045H:
507 // DSPREADY doesn't seem to work on the TDA10045H
511 case FE_TYPE_TDA10046H:
512 timeout = jiffies + HZ;
513 while(!(tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD) & 0x20)) {
514 if (time_after(jiffies, timeout)) {
515 printk("tda1004x: DSP failed to initialised.\n");
524 // check upload was OK
525 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
526 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSP_CMD, 0x67);
527 if ((tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA1) != 0x67) ||
528 (tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA2) != dspVersion)) {
529 printk("%s: firmware upload failed!\n", __FUNCTION__);
538 static int tda10045h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
540 struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = 0,.len = 0 };
541 static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
543 dprintk("%s\n", __FUNCTION__);
545 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
547 // Disable the MC44BC374C
548 tda1004x_enable_tuner_i2c(i2c, tda_state);
549 tuner_msg.addr = MC44BC374_ADDRESS;
550 tuner_msg.buf = disable_mc44BC374c;
551 tuner_msg.len = sizeof(disable_mc44BC374c);
552 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
553 i2c->xfer(i2c, &tuner_msg, 1);
555 tda1004x_disable_tuner_i2c(i2c, tda_state);
558 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
559 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
560 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0); // no frequency inversion
561 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
562 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
563 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
564 tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
565 tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
566 tda1004x_write_mask(i2c, tda_state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
567 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
568 tda1004x_write_byte(i2c, tda_state, TDA1004X_CONFADC1, 0x2e);
576 static int tda10046h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
578 struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = 0,.len = 0 };
579 static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
581 dprintk("%s\n", __FUNCTION__);
583 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0); // wake up the chip
585 // Disable the MC44BC374C
586 tda1004x_enable_tuner_i2c(i2c, tda_state);
587 tuner_msg.addr = MC44BC374_ADDRESS;
588 tuner_msg.buf = disable_mc44BC374c;
589 tuner_msg.len = sizeof(disable_mc44BC374c);
590 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
591 i2c->xfer(i2c, &tuner_msg, 1);
593 tda1004x_disable_tuner_i2c(i2c, tda_state);
596 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
597 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0x40); // TT TDA10046H needs inversion ON
598 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
599 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
600 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10); // PLL M = 10
601 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
602 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
603 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
604 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
605 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_CONF, 0); // AGC setup
606 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
607 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MIN, 0); // }
608 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
609 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MIN, 0); // }
610 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MAX, 0xff); // }
611 tda1004x_write_mask(i2c, tda_state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
612 tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
613 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
614 tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
615 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
616 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
617 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
618 tda1004x_write_byte(i2c, tda_state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
619 tda1004x_write_mask(i2c, tda_state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
620 tda10046h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
628 static int tda1004x_encode_fec(int fec)
630 // convert known FEC values
648 static int tda1004x_decode_fec(int tdafec)
650 // convert known FEC values
668 static int tda1004x_set_frequency(struct dvb_i2c_bus *i2c,
669 struct tda1004x_state *tda_state,
670 struct dvb_frontend_parameters *fe_params)
673 struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=tuner_buf, .len=sizeof(tuner_buf) };
674 int tuner_frequency = 0;
676 int counter, counter2;
678 dprintk("%s\n", __FUNCTION__);
680 // setup the frequency buffer
681 switch (tda_state->tuner_type) {
682 case TUNER_TYPE_TD1344:
684 // setup tuner buffer
685 // ((Fif+((1000000/6)/2)) + Finput)/(1000000/6)
687 (((fe_params->frequency / 1000) * 6) + 217502) / 1000;
688 tuner_buf[0] = tuner_frequency >> 8;
689 tuner_buf[1] = tuner_frequency & 0xff;
691 if (fe_params->frequency < 550000000) {
698 tda1004x_enable_tuner_i2c(i2c, tda_state);
699 tuner_msg.addr = tda_state->tuner_address;
701 i2c->xfer(i2c, &tuner_msg, 1);
703 // wait for it to finish
705 tuner_msg.flags = I2C_M_RD;
708 while (counter++ < 100) {
709 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
710 if (tuner_buf[0] & 0x40) {
721 tda1004x_disable_tuner_i2c(i2c, tda_state);
724 case TUNER_TYPE_TD1316:
725 // determine charge pump
726 tuner_frequency = fe_params->frequency + 36130000;
727 if (tuner_frequency < 87000000) {
729 } else if (tuner_frequency < 130000000) {
731 } else if (tuner_frequency < 160000000) {
733 } else if (tuner_frequency < 200000000) {
735 } else if (tuner_frequency < 290000000) {
737 } else if (tuner_frequency < 420000000) {
739 } else if (tuner_frequency < 480000000) {
741 } else if (tuner_frequency < 620000000) {
743 } else if (tuner_frequency < 830000000) {
745 } else if (tuner_frequency < 895000000) {
752 if (fe_params->frequency < 49000000) {
754 } else if (fe_params->frequency < 159000000) {
756 } else if (fe_params->frequency < 444000000) {
758 } else if (fe_params->frequency < 861000000) {
765 switch (fe_params->u.ofdm.bandwidth) {
766 case BANDWIDTH_6_MHZ:
770 case BANDWIDTH_7_MHZ:
774 case BANDWIDTH_8_MHZ:
783 // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
785 (((fe_params->frequency / 1000) * 6) + 217280) / 1000;
787 // setup tuner buffer
788 tuner_buf[0] = tuner_frequency >> 8;
789 tuner_buf[1] = tuner_frequency & 0xff;
791 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
794 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
796 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10);
797 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x80, 0);
798 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0);
800 // disable agc_conf[2]
801 tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 0);
803 tda1004x_enable_tuner_i2c(i2c, tda_state);
804 tuner_msg.addr = tda_state->tuner_address;
806 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
810 tda1004x_disable_tuner_i2c(i2c, tda_state);
811 if (tda_state->fe_type == FE_TYPE_TDA10046H)
812 tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 4);
819 dprintk("%s: success\n", __FUNCTION__);
825 static int tda1004x_set_fe(struct dvb_i2c_bus *i2c,
826 struct tda1004x_state *tda_state,
827 struct dvb_frontend_parameters *fe_params)
832 dprintk("%s\n", __FUNCTION__);
835 if ((tmp = tda1004x_set_frequency(i2c, tda_state, fe_params)) < 0)
838 // hardcoded to use auto as much as possible
839 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
840 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
841 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
843 // Set standard params.. or put them to auto
844 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
845 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
846 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
847 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
848 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 1); // enable auto
849 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
850 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
851 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
853 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 0); // disable auto
856 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
857 if (tmp < 0) return tmp;
858 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 7, tmp);
861 if (fe_params->u.ofdm.code_rate_LP != FEC_NONE) {
862 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
863 if (tmp < 0) return tmp;
864 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
868 switch (fe_params->u.ofdm.constellation) {
870 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 0);
874 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 1);
878 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 2);
886 switch (fe_params->u.ofdm.hierarchy_information) {
888 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
892 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
896 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
900 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
909 switch(tda_state->fe_type) {
910 case FE_TYPE_TDA10045H:
911 tda10045h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
914 case FE_TYPE_TDA10046H:
915 tda10046h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
919 // need to invert the inversion for TT TDA10046H
920 inversion = fe_params->inversion;
921 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
922 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
928 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0);
932 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0x20);
939 // set guard interval
940 switch (fe_params->u.ofdm.guard_interval) {
941 case GUARD_INTERVAL_1_32:
942 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
943 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
946 case GUARD_INTERVAL_1_16:
947 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
948 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
951 case GUARD_INTERVAL_1_8:
952 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
953 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
956 case GUARD_INTERVAL_1_4:
957 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
958 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
961 case GUARD_INTERVAL_AUTO:
962 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 2);
963 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
970 // set transmission mode
971 switch (fe_params->u.ofdm.transmission_mode) {
972 case TRANSMISSION_MODE_2K:
973 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
974 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
977 case TRANSMISSION_MODE_8K:
978 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
979 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
982 case TRANSMISSION_MODE_AUTO:
983 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 4);
984 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0);
992 switch(tda_state->fe_type) {
993 case FE_TYPE_TDA10045H:
994 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
995 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
999 case FE_TYPE_TDA10046H:
1000 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x40, 0x40);
1010 static int tda1004x_get_fe(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, struct dvb_frontend_parameters *fe_params)
1013 dprintk("%s\n", __FUNCTION__);
1016 fe_params->inversion = INVERSION_OFF;
1017 if (tda1004x_read_byte(i2c, tda_state, TDA1004X_CONFC1) & 0x20) {
1018 fe_params->inversion = INVERSION_ON;
1021 // need to invert the inversion for TT TDA10046H
1022 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
1023 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
1027 switch(tda_state->fe_type) {
1028 case FE_TYPE_TDA10045H:
1029 switch (tda1004x_read_byte(i2c, tda_state, TDA10045H_WREF_LSB)) {
1031 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1034 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1037 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1042 case FE_TYPE_TDA10046H:
1043 switch (tda1004x_read_byte(i2c, tda_state, TDA10046H_TIME_WREF1)) {
1045 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1048 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1051 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1058 fe_params->u.ofdm.code_rate_HP =
1059 tda1004x_decode_fec(tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) & 7);
1060 fe_params->u.ofdm.code_rate_LP =
1061 tda1004x_decode_fec((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) >> 3) & 7);
1064 switch (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 3) {
1066 fe_params->u.ofdm.constellation = QPSK;
1069 fe_params->u.ofdm.constellation = QAM_16;
1072 fe_params->u.ofdm.constellation = QAM_64;
1076 // transmission mode
1077 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1078 if (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x10) {
1079 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1083 switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
1085 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1088 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1091 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1094 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1099 switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
1101 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1104 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
1107 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
1110 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
1119 static int tda1004x_read_status(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, fe_status_t * fe_status)
1125 dprintk("%s\n", __FUNCTION__);
1128 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD);
1135 if (status & 4) *fe_status |= FE_HAS_SIGNAL;
1136 if (status & 2) *fe_status |= FE_HAS_CARRIER;
1137 if (status & 8) *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1139 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1140 // is getting anything valid
1141 if (!(*fe_status & FE_HAS_VITERBI)) {
1143 cber = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1144 if (cber == -1) return -EIO;
1145 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1146 if (status == -1) return -EIO;
1147 cber |= (status << 8);
1148 tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1150 if (cber != 65535) {
1151 *fe_status |= FE_HAS_VITERBI;
1155 // if we DO have some valid VITERBI output, but don't already have SYNC
1156 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1157 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1159 vber = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_LSB);
1160 if (vber == -1) return -EIO;
1161 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MID);
1162 if (status == -1) return -EIO;
1163 vber |= (status << 8);
1164 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MSB);
1165 if (status == -1) return -EIO;
1166 vber |= ((status << 16) & 0x0f);
1167 tda1004x_read_byte(i2c, tda_state, TDA1004X_CVBER_LUT);
1169 // if RS has passed some valid TS packets, then we must be
1170 // getting some SYNC bytes
1172 *fe_status |= FE_HAS_SYNC;
1177 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1181 static int tda1004x_read_signal_strength(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * signal)
1186 dprintk("%s\n", __FUNCTION__);
1188 // determine the register to use
1189 switch(tda_state->fe_type) {
1190 case FE_TYPE_TDA10045H:
1191 reg = TDA10045H_S_AGC;
1194 case FE_TYPE_TDA10046H:
1195 reg = TDA10046H_AGC_IF_LEVEL;
1200 tmp = tda1004x_read_byte(i2c, tda_state, reg);
1205 *signal = (tmp << 8) | tmp;
1206 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1211 static int tda1004x_read_snr(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * snr)
1215 dprintk("%s\n", __FUNCTION__);
1218 tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_SNR);
1226 *snr = ((tmp << 8) | tmp);
1227 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1231 static int tda1004x_read_ucblocks(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ucblocks)
1237 dprintk("%s\n", __FUNCTION__);
1239 // read the UCBLOCKS and reset
1241 tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1245 while (counter++ < 5) {
1246 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1247 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1248 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1250 tmp2 = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1254 if ((tmp2 < tmp) || (tmp2 == 0))
1262 *ucblocks = 0xffffffff;
1264 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1268 static int tda1004x_read_ber(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ber)
1272 dprintk("%s\n", __FUNCTION__);
1275 tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1276 if (tmp < 0) return -EIO;
1278 tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1279 if (tmp < 0) return -EIO;
1281 tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1284 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1288 static int tda1004x_sleep(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state)
1290 switch(tda_state->fe_type) {
1291 case FE_TYPE_TDA10045H:
1292 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0x10);
1295 case FE_TYPE_TDA10046H:
1296 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 1);
1304 static int tda1004x_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
1307 struct dvb_i2c_bus *i2c = fe->i2c;
1308 struct tda1004x_state *tda_state = (struct tda1004x_state *) fe->data;
1310 dprintk("%s: cmd=0x%x\n", __FUNCTION__, cmd);
1314 switch(tda_state->fe_type) {
1315 case FE_TYPE_TDA10045H:
1316 memcpy(arg, &tda10045h_info, sizeof(struct dvb_frontend_info));
1319 case FE_TYPE_TDA10046H:
1320 memcpy(arg, &tda10046h_info, sizeof(struct dvb_frontend_info));
1325 case FE_READ_STATUS:
1326 return tda1004x_read_status(i2c, tda_state, (fe_status_t *) arg);
1329 return tda1004x_read_ber(i2c, tda_state, (u32 *) arg);
1331 case FE_READ_SIGNAL_STRENGTH:
1332 return tda1004x_read_signal_strength(i2c, tda_state, (u16 *) arg);
1335 return tda1004x_read_snr(i2c, tda_state, (u16 *) arg);
1337 case FE_READ_UNCORRECTED_BLOCKS:
1338 return tda1004x_read_ucblocks(i2c, tda_state, (u32 *) arg);
1340 case FE_SET_FRONTEND:
1341 return tda1004x_set_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1343 case FE_GET_FRONTEND:
1344 return tda1004x_get_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1347 tda_state->initialised = 0;
1348 return tda1004x_sleep(i2c, tda_state);
1352 // don't bother reinitialising
1353 if (tda_state->initialised)
1356 // OK, perform initialisation
1357 switch(tda_state->fe_type) {
1358 case FE_TYPE_TDA10045H:
1359 status = tda10045h_init(i2c, tda_state);
1362 case FE_TYPE_TDA10046H:
1363 status = tda10046h_init(i2c, tda_state);
1367 tda_state->initialised = 1;
1370 case FE_GET_TUNE_SETTINGS:
1372 struct dvb_frontend_tune_settings* fesettings = (struct dvb_frontend_tune_settings*) arg;
1373 fesettings->min_delay_ms = 800;
1374 fesettings->step_size = 166667;
1375 fesettings->max_drift = 166667*2;
1387 static int tda1004x_attach(struct dvb_i2c_bus *i2c, void **data)
1389 int tda1004x_address = -1;
1390 int tuner_address = -1;
1392 int tuner_type = -1;
1393 struct tda1004x_state tda_state;
1394 struct tda1004x_state* ptda_state;
1395 struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=0, .len=0 };
1396 static u8 td1344_init[] = { 0x0b, 0xf5, 0x88, 0xab };
1397 static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
1398 static u8 td1316_init_tda10046h[] = { 0x0b, 0xf5, 0x80, 0xab };
1401 dprintk("%s\n", __FUNCTION__);
1403 // probe for tda10045h
1404 if (tda1004x_address == -1) {
1405 tda_state.tda1004x_address = 0x08;
1406 if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x25) {
1407 tda1004x_address = 0x08;
1408 fe_type = FE_TYPE_TDA10045H;
1409 printk("tda1004x: Detected Philips TDA10045H.\n");
1413 // probe for tda10046h
1414 if (tda1004x_address == -1) {
1415 tda_state.tda1004x_address = 0x08;
1416 if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x46) {
1417 tda1004x_address = 0x08;
1418 fe_type = FE_TYPE_TDA10046H;
1419 printk("tda1004x: Detected Philips TDA10046H.\n");
1423 // did we find a frontend?
1424 if (tda1004x_address == -1) {
1428 // enable access to the tuner
1429 tda1004x_enable_tuner_i2c(i2c, &tda_state);
1431 // check for a TD1344 first
1432 if (tuner_address == -1) {
1433 tuner_msg.addr = 0x61;
1434 tuner_msg.buf = td1344_init;
1435 tuner_msg.len = sizeof(td1344_init);
1436 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1438 tuner_address = 0x61;
1439 tuner_type = TUNER_TYPE_TD1344;
1440 printk("tda1004x: Detected Philips TD1344 tuner.\n");
1444 // OK, try a TD1316 on address 0x63
1445 if (tuner_address == -1) {
1446 tuner_msg.addr = 0x63;
1447 tuner_msg.buf = td1316_init;
1448 tuner_msg.len = sizeof(td1316_init);
1449 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1451 tuner_address = 0x63;
1452 tuner_type = TUNER_TYPE_TD1316;
1453 printk("tda1004x: Detected Philips TD1316 tuner.\n");
1457 // OK, TD1316 again, on address 0x60 (TDA10046H)
1458 if (tuner_address == -1) {
1459 tuner_msg.addr = 0x60;
1460 tuner_msg.buf = td1316_init_tda10046h;
1461 tuner_msg.len = sizeof(td1316_init_tda10046h);
1462 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1464 tuner_address = 0x60;
1465 tuner_type = TUNER_TYPE_TD1316;
1466 printk("tda1004x: Detected Philips TD1316 tuner.\n");
1469 tda1004x_disable_tuner_i2c(i2c, &tda_state);
1471 // did we find a tuner?
1472 if (tuner_address == -1) {
1473 printk("tda1004x: Detected, but with unknown tuner.\n");
1478 tda_state.tda1004x_address = tda1004x_address;
1479 tda_state.fe_type = fe_type;
1480 tda_state.tuner_address = tuner_address;
1481 tda_state.tuner_type = tuner_type;
1482 tda_state.initialised = 0;
1485 if ((status = tda1004x_fwupload(i2c, &tda_state)) != 0) return status;
1487 // create the real state we'll be passing about
1488 if ((ptda_state = (struct tda1004x_state*) kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL)) == NULL) {
1491 memcpy(ptda_state, &tda_state, sizeof(struct tda1004x_state));
1495 switch(tda_state.fe_type) {
1496 case FE_TYPE_TDA10045H:
1497 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10045h_info);
1499 case FE_TYPE_TDA10046H:
1500 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10046h_info);
1503 // should not get here
1509 void tda1004x_detach(struct dvb_i2c_bus *i2c, void *data)
1511 dprintk("%s\n", __FUNCTION__);
1514 dvb_unregister_frontend(tda1004x_ioctl, i2c);
1519 int __init init_tda1004x(void)
1521 return dvb_register_i2c_device(THIS_MODULE, tda1004x_attach, tda1004x_detach);
1526 void __exit exit_tda1004x(void)
1528 dvb_unregister_i2c_device(tda1004x_attach);
1531 module_init(init_tda1004x);
1532 module_exit(exit_tda1004x);
1534 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Frontend");
1535 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1536 MODULE_LICENSE("GPL");
1538 MODULE_PARM(tda1004x_debug, "i");
1539 MODULE_PARM_DESC(tda1004x_debug, "enable verbose debug messages");
1541 MODULE_PARM(tda1004x_firmware, "s");
1542 MODULE_PARM_DESC(tda1004x_firmware, "Where to find the firmware file");