2 VES1820 - Single Chip Cable Channel Receiver driver module
4 Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/config.h>
22 #include <linux/delay.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/string.h>
28 #include <linux/slab.h>
29 #include <asm/div64.h>
31 #include "dvb_frontend.h"
36 struct ves1820_state {
38 struct i2c_adapter *i2c;
40 struct dvb_frontend_ops ops;
42 /* configuration settings */
43 const struct ves1820_config* config;
45 struct dvb_frontend frontend;
47 /* private demodulator data */
55 static u8 ves1820_inittab[] = {
56 0x69, 0x6A, 0x93, 0x12, 0x12, 0x46, 0x26, 0x1A,
57 0x43, 0x6A, 0xAA, 0xAA, 0x1E, 0x85, 0x43, 0x20,
58 0xE0, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00,
59 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
60 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
61 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
62 0x00, 0x00, 0x00, 0x00, 0x40
65 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
67 u8 buf[] = { 0x00, reg, data };
68 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
71 ret = i2c_transfer(state->i2c, &msg, 1);
74 printk("ves1820: %s(): writereg error (reg == 0x%02x,"
75 "val == 0x%02x, ret == %i)\n", __FUNCTION__, reg, data, ret);
78 return (ret != 1) ? -EREMOTEIO : 0;
81 static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
83 u8 b0 [] = { 0x00, reg };
85 struct i2c_msg msg[] = {
86 {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
87 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
91 ret = i2c_transfer(state->i2c, msg, 2);
94 printk("ves1820: %s(): readreg error (reg == 0x%02x,"
95 "ret == %i)\n", __FUNCTION__, reg, ret);
101 static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversion)
103 reg0 |= state->reg0 & 0x62;
105 if (INVERSION_ON == inversion) {
106 if (!state->config->invert) reg0 |= 0x20;
109 } else if (INVERSION_OFF == inversion) {
111 if (!state->config->invert) reg0 &= ~0x20;
115 ves1820_writereg(state, 0x00, reg0 & 0xfe);
116 ves1820_writereg(state, 0x00, reg0 | 0x01);
123 static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
135 if (symbolrate > state->config->xin / 2)
136 symbolrate = state->config->xin / 2;
138 if (symbolrate < 500000)
141 if (symbolrate < state->config->xin / 16)
143 if (symbolrate < state->config->xin / 32)
145 if (symbolrate < state->config->xin / 64)
149 fpxin = state->config->xin * 10;
150 fptmp = fpxin; do_div(fptmp, 123);
151 if (symbolrate < fptmp);
153 fptmp = fpxin; do_div(fptmp, 160);
154 if (symbolrate < fptmp);
156 fptmp = fpxin; do_div(fptmp, 246);
157 if (symbolrate < fptmp);
159 fptmp = fpxin; do_div(fptmp, 320);
160 if (symbolrate < fptmp);
162 fptmp = fpxin; do_div(fptmp, 492);
163 if (symbolrate < fptmp);
165 fptmp = fpxin; do_div(fptmp, 640);
166 if (symbolrate < fptmp);
168 fptmp = fpxin; do_div(fptmp, 984);
169 if (symbolrate < fptmp);
172 fin = state->config->xin >> 4;
174 ratio = (symbolrate << 4) / fin;
175 tmp = ((symbolrate << 4) % fin) << 8;
176 ratio = (ratio << 8) + tmp / fin;
177 tmp = (tmp % fin) << 8;
178 ratio = (ratio << 8) + (tmp + fin / 2) / fin;
181 BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
186 SFIL = (SFIL << 4) | ves1820_inittab[0x0E];
188 NDEC = (NDEC << 6) | ves1820_inittab[0x03];
190 ves1820_writereg(state, 0x03, NDEC);
191 ves1820_writereg(state, 0x0a, BDR & 0xff);
192 ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
193 ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
195 ves1820_writereg(state, 0x0d, BDRI);
196 ves1820_writereg(state, 0x0e, SFIL);
213 static int ves1820_init(struct dvb_frontend* fe)
215 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
219 ves1820_writereg(state, 0, 0);
221 for (i = 0; i < 53; i++) {
222 val = ves1820_inittab[i];
223 if ((i == 2) && (state->config->selagc)) val |= 0x08;
224 ves1820_writereg(state, i, val);
227 ves1820_writereg(state, 0x34, state->pwm);
229 if (state->config->pll_init) state->config->pll_init(fe);
234 static int ves1820_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
236 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
237 static const u8 reg0x00 [] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
238 static const u8 reg0x01 [] = { 140, 140, 106, 100, 92 };
239 static const u8 reg0x05 [] = { 135, 100, 70, 54, 38 };
240 static const u8 reg0x08 [] = { 162, 116, 67, 52, 35 };
241 static const u8 reg0x09 [] = { 145, 150, 106, 126, 107 };
242 int real_qam = p->u.qam.modulation - QAM_16;
244 if (real_qam < 0 || real_qam > 4)
247 state->config->pll_set(fe, p);
248 ves1820_set_symbolrate(state, p->u.qam.symbol_rate);
249 ves1820_writereg(state, 0x34, state->pwm);
251 ves1820_writereg(state, 0x01, reg0x01[real_qam]);
252 ves1820_writereg(state, 0x05, reg0x05[real_qam]);
253 ves1820_writereg(state, 0x08, reg0x08[real_qam]);
254 ves1820_writereg(state, 0x09, reg0x09[real_qam]);
256 ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
261 static int ves1820_read_status(struct dvb_frontend* fe, fe_status_t* status)
263 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
268 sync = ves1820_readreg(state, 0x11);
271 *status |= FE_HAS_SIGNAL;
274 *status |= FE_HAS_CARRIER;
276 if (sync & 2) /* XXX FIXME! */
277 *status |= FE_HAS_VITERBI;
280 *status |= FE_HAS_SYNC;
283 *status |= FE_HAS_LOCK;
288 static int ves1820_read_ber(struct dvb_frontend* fe, u32* ber)
290 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
292 u32 _ber = ves1820_readreg(state, 0x14) |
293 (ves1820_readreg(state, 0x15) << 8) |
294 ((ves1820_readreg(state, 0x16) & 0x0f) << 16);
300 static int ves1820_read_signal_strength(struct dvb_frontend* fe, u16* strength)
302 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
304 u8 gain = ves1820_readreg(state, 0x17);
305 *strength = (gain << 8) | gain;
310 static int ves1820_read_snr(struct dvb_frontend* fe, u16* snr)
312 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
314 u8 quality = ~ves1820_readreg(state, 0x18);
315 *snr = (quality << 8) | quality;
320 static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
322 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
324 *ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
325 if (*ucblocks == 0x7f)
326 *ucblocks = 0xffffffff;
328 /* reset uncorrected block counter */
329 ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
330 ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
335 static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
337 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
341 sync = ves1820_readreg(state, 0x11);
342 afc = ves1820_readreg(state, 0x19);
344 /* AFC only valid when carrier has been recovered */
345 printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
346 "ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->u.qam.symbol_rate * afc) >> 10);
349 if (!state->config->invert) {
350 p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
352 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
355 p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16;
357 p->u.qam.fec_inner = FEC_NONE;
359 p->frequency = ((p->frequency + 31250) / 62500) * 62500;
361 p->frequency -= ((s32)p->u.qam.symbol_rate * afc) >> 10;
366 static int ves1820_sleep(struct dvb_frontend* fe)
368 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
370 ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */
371 ves1820_writereg(state, 0x00, 0x80); /* standby */
376 static int ves1820_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
379 fesettings->min_delay_ms = 200;
380 fesettings->step_size = 0;
381 fesettings->max_drift = 0;
385 static void ves1820_release(struct dvb_frontend* fe)
387 struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
391 static struct dvb_frontend_ops ves1820_ops;
393 struct dvb_frontend* ves1820_attach(const struct ves1820_config* config,
394 struct i2c_adapter* i2c,
397 struct ves1820_state* state = NULL;
399 /* allocate memory for the internal state */
400 state = (struct ves1820_state*) kmalloc(sizeof(struct ves1820_state), GFP_KERNEL);
404 /* setup the state */
405 memcpy(&state->ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
406 state->reg0 = ves1820_inittab[0];
407 state->config = config;
411 /* check if the demod is there */
412 if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
416 printk("ves1820: pwm=0x%02x\n", state->pwm);
418 state->ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN/2)/64 */
419 state->ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */
421 /* create dvb_frontend */
422 state->frontend.ops = &state->ops;
423 state->frontend.demodulator_priv = state;
424 return &state->frontend;
427 if (state) kfree(state);
431 static struct dvb_frontend_ops ves1820_ops = {
434 .name = "VLSI VES1820 DVB-C",
436 .frequency_stepsize = 62500,
437 .frequency_min = 51000000,
438 .frequency_max = 858000000,
439 .caps = FE_CAN_QAM_16 |
447 .release = ves1820_release,
449 .init = ves1820_init,
450 .sleep = ves1820_sleep,
452 .set_frontend = ves1820_set_parameters,
453 .get_frontend = ves1820_get_frontend,
454 .get_tune_settings = ves1820_get_tune_settings,
456 .read_status = ves1820_read_status,
457 .read_ber = ves1820_read_ber,
458 .read_signal_strength = ves1820_read_signal_strength,
459 .read_snr = ves1820_read_snr,
460 .read_ucblocks = ves1820_read_ucblocks,
463 module_param(verbose, int, 0644);
464 MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
466 MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
467 MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
468 MODULE_LICENSE("GPL");
470 EXPORT_SYMBOL(ves1820_attach);