2 planb - PlanB frame grabber driver
4 PlanB is used in the 7x00/8x00 series of PowerMacintosh
5 Computers as video input DMA controller.
7 Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)
9 Based largely on the bttv driver by Ralph Metzler (rjkm@thp.uni-koeln.de)
11 Additional debugging and coding by Takashi Oe (toe@unlserve.unl.edu)
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the Free Software
25 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 /* $Id: planb.c,v 1.18 1999/05/02 17:36:34 mlan Exp $ */
30 #include <linux/init.h>
31 #include <linux/errno.h>
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/major.h>
35 #include <linux/slab.h>
36 #include <linux/types.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/vmalloc.h>
41 #include <linux/sched.h>
42 #include <linux/videodev.h>
43 #include <asm/uaccess.h>
46 #include <asm/dbdma.h>
47 #include <asm/pgtable.h>
50 #include <asm/semaphore.h>
55 /* Would you mind for some ugly debugging? */
57 #define DEBUG(x...) printk(KERN_DEBUG ## x) /* Debug driver */
59 #define DEBUG(x...) /* Don't debug driver */
63 #define IDEBUG(x...) printk(KERN_DEBUG ## x) /* Debug interrupt part */
65 #define IDEBUG(x...) /* Don't debug interrupt part */
68 /* Ever seen a Mac with more than 1 of these? */
72 static struct planb planbs[PLANB_MAX];
73 static volatile struct planb_registers *planb_regs;
75 static int def_norm = PLANB_DEF_NORM; /* default norm */
76 static int video_nr = -1;
78 MODULE_PARM(def_norm, "i");
79 MODULE_PARM_DESC(def_norm, "Default startup norm (0=PAL, 1=NTSC, 2=SECAM)");
80 MODULE_PARM(video_nr,"i");
81 MODULE_LICENSE("GPL");
84 /* ------------------ PlanB Exported Functions ------------------ */
85 static long planb_write(struct video_device *, const char *, unsigned long, int);
86 static long planb_read(struct video_device *, char *, unsigned long, int);
87 static int planb_open(struct video_device *, int);
88 static void planb_close(struct video_device *);
89 static int planb_ioctl(struct video_device *, unsigned int, void *);
90 static int planb_init_done(struct video_device *);
91 static int planb_mmap(struct video_device *, const char *, unsigned long);
92 static void planb_irq(int, void *, struct pt_regs *);
93 static void release_planb(void);
94 int init_planbs(struct video_init *);
96 /* ------------------ PlanB Internal Functions ------------------ */
97 static int planb_prepare_open(struct planb *);
98 static void planb_prepare_close(struct planb *);
99 static void saa_write_reg(unsigned char, unsigned char);
100 static unsigned char saa_status(int, struct planb *);
101 static void saa_set(unsigned char, unsigned char, struct planb *);
102 static void saa_init_regs(struct planb *);
103 static int grabbuf_alloc(struct planb *);
104 static int vgrab(struct planb *, struct video_mmap *);
105 static void add_clip(struct planb *, struct video_clip *);
106 static void fill_cmd_buff(struct planb *);
107 static void cmd_buff(struct planb *);
108 static volatile struct dbdma_cmd *setup_grab_cmd(int, struct planb *);
109 static void overlay_start(struct planb *);
110 static void overlay_stop(struct planb *);
111 static inline void tab_cmd_dbdma(volatile struct dbdma_cmd *, unsigned short,
113 static inline void tab_cmd_store(volatile struct dbdma_cmd *, unsigned int,
115 static inline void tab_cmd_gen(volatile struct dbdma_cmd *, unsigned short,
116 unsigned short, unsigned int, unsigned int);
117 static int init_planb(struct planb *);
118 static int find_planb(void);
119 static void planb_pre_capture(int, int, struct planb *);
120 static volatile struct dbdma_cmd *cmd_geo_setup(volatile struct dbdma_cmd *,
121 int, int, int, int, int, struct planb *);
122 static inline void planb_dbdma_stop(volatile struct dbdma_regs *);
123 static unsigned int saa_geo_setup(int, int, int, int, struct planb *);
124 static inline int overlay_is_active(struct planb *);
126 /*******************************/
127 /* Memory management functions */
128 /*******************************/
130 static int grabbuf_alloc(struct planb *pb)
134 npage = MAX_GBUFFERS * ((PLANB_MAX_FBUF / PAGE_SIZE + 1)
135 #ifndef PLANB_GSCANLINE
137 #endif /* PLANB_GSCANLINE */
139 if ((pb->rawbuf = (unsigned char**) kmalloc (npage
140 * sizeof(unsigned long), GFP_KERNEL)) == 0)
142 for (i = 0; i < npage; i++) {
143 pb->rawbuf[i] = (unsigned char *)__get_free_pages(GFP_KERNEL
147 SetPageReserved(virt_to_page(pb->rawbuf[i]));
150 printk(KERN_DEBUG "PlanB: init_grab: grab buffer not allocated\n");
152 ClearPageReserved(virt_to_page(pb->rawbuf[i]));
153 free_pages((unsigned long)pb->rawbuf[i], 0);
158 pb->rawbuf_size = npage;
162 /*****************************/
163 /* Hardware access functions */
164 /*****************************/
166 static void saa_write_reg(unsigned char addr, unsigned char val)
168 planb_regs->saa_addr = addr; eieio();
169 planb_regs->saa_regval = val; eieio();
173 /* return status byte 0 or 1: */
174 static unsigned char saa_status(int byte, struct planb *pb)
176 saa_regs[pb->win.norm][SAA7196_STDC] =
177 (saa_regs[pb->win.norm][SAA7196_STDC] & ~2) | ((byte & 1) << 1);
178 saa_write_reg (SAA7196_STDC, saa_regs[pb->win.norm][SAA7196_STDC]);
180 /* Let's wait 30msec for this one */
181 msleep_interruptible(30);
183 return (unsigned char)in_8 (&planb_regs->saa_status);
186 static void saa_set(unsigned char addr, unsigned char val, struct planb *pb)
188 if(saa_regs[pb->win.norm][addr] != val) {
189 saa_regs[pb->win.norm][addr] = val;
190 saa_write_reg (addr, val);
195 static void saa_init_regs(struct planb *pb)
199 for (i = 0; i < SAA7196_NUMREGS; i++)
200 saa_write_reg (i, saa_regs[pb->win.norm][i]);
203 static unsigned int saa_geo_setup(int width, int height, int interlace, int bpp,
206 int ht, norm = pb->win.norm;
210 /* RGB555+a 1x16-bit + 16-bit transparent */
211 saa_regs[norm][SAA7196_FMTS] &= ~0x3;
215 /* RGB888 1x24-bit + 8-bit transparent */
216 saa_regs[norm][SAA7196_FMTS] &= ~0x1;
217 saa_regs[norm][SAA7196_FMTS] |= 0x2;
222 ht = (interlace ? height / 2 : height);
223 saa_regs[norm][SAA7196_OUTPIX] = (unsigned char) (width & 0x00ff);
224 saa_regs[norm][SAA7196_HFILT] = (saa_regs[norm][SAA7196_HFILT] & ~0x3)
225 | (width >> 8 & 0x3);
226 saa_regs[norm][SAA7196_OUTLINE] = (unsigned char) (ht & 0xff);
227 saa_regs[norm][SAA7196_VYP] = (saa_regs[norm][SAA7196_VYP] & ~0x3)
229 /* feed both fields if interlaced, or else feed only even fields */
230 saa_regs[norm][SAA7196_FMTS] = (interlace) ?
231 (saa_regs[norm][SAA7196_FMTS] & ~0x60)
232 : (saa_regs[norm][SAA7196_FMTS] | 0x60);
233 /* transparent mode; extended format enabled */
234 saa_regs[norm][SAA7196_DPATH] |= 0x3;
239 /***************************/
240 /* DBDMA support functions */
241 /***************************/
243 static inline void planb_dbdma_restart(volatile struct dbdma_regs *ch)
245 out_le32(&ch->control, PLANB_CLR(RUN));
246 out_le32(&ch->control, PLANB_SET(RUN|WAKE) | PLANB_CLR(PAUSE));
249 static inline void planb_dbdma_stop(volatile struct dbdma_regs *ch)
253 out_le32(&ch->control, PLANB_CLR(RUN) | PLANB_SET(FLUSH));
254 while((in_le32(&ch->status) == (ACTIVE | FLUSH)) && (i < 999)) {
255 IDEBUG("PlanB: waiting for DMA to stop\n");
260 static inline void tab_cmd_dbdma(volatile struct dbdma_cmd *ch,
261 unsigned short command, unsigned int cmd_dep)
263 st_le16(&ch->command, command);
264 st_le32(&ch->cmd_dep, cmd_dep);
267 static inline void tab_cmd_store(volatile struct dbdma_cmd *ch,
268 unsigned int phy_addr, unsigned int cmd_dep)
270 st_le16(&ch->command, STORE_WORD | KEY_SYSTEM);
271 st_le16(&ch->req_count, 4);
272 st_le32(&ch->phy_addr, phy_addr);
273 st_le32(&ch->cmd_dep, cmd_dep);
276 static inline void tab_cmd_gen(volatile struct dbdma_cmd *ch,
277 unsigned short command, unsigned short req_count,
278 unsigned int phy_addr, unsigned int cmd_dep)
280 st_le16(&ch->command, command);
281 st_le16(&ch->req_count, req_count);
282 st_le32(&ch->phy_addr, phy_addr);
283 st_le32(&ch->cmd_dep, cmd_dep);
286 static volatile struct dbdma_cmd *cmd_geo_setup(
287 volatile struct dbdma_cmd *c1, int width, int height, int interlace,
288 int bpp, int clip, struct planb *pb)
290 int norm = pb->win.norm;
292 if((saa_geo_setup(width, height, interlace, bpp, pb)) != 0)
293 return (volatile struct dbdma_cmd *)NULL;
294 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
296 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
297 saa_regs[norm][SAA7196_FMTS]);
298 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
300 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
301 saa_regs[norm][SAA7196_DPATH]);
302 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->even),
303 bpp | ((clip)? PLANB_CLIPMASK: 0));
304 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->odd),
305 bpp | ((clip)? PLANB_CLIPMASK: 0));
306 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
308 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
309 saa_regs[norm][SAA7196_OUTPIX]);
310 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
312 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
313 saa_regs[norm][SAA7196_HFILT]);
314 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
316 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
317 saa_regs[norm][SAA7196_OUTLINE]);
318 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
320 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
321 saa_regs[norm][SAA7196_VYP]);
325 /******************************/
326 /* misc. supporting functions */
327 /******************************/
329 static inline void planb_lock(struct planb *pb)
334 static inline void planb_unlock(struct planb *pb)
343 static int planb_prepare_open(struct planb *pb)
347 /* allocate memory for two plus alpha command buffers (size: max lines,
348 plus 40 commands handling, plus 1 alignment), plus dummy command buf,
349 plus clipmask buffer, plus frame grabbing status */
350 size = (pb->tab_size*(2+MAX_GBUFFERS*TAB_FACTOR)+1+MAX_GBUFFERS
351 * PLANB_DUMMY)*sizeof(struct dbdma_cmd)
352 +(PLANB_MAXLINES*((PLANB_MAXPIXELS+7)& ~7))/8
353 +MAX_GBUFFERS*sizeof(unsigned int);
354 if ((pb->priv_space = kmalloc (size, GFP_KERNEL)) == 0)
356 memset ((void *) pb->priv_space, 0, size);
357 pb->overlay_last1 = pb->ch1_cmd = (volatile struct dbdma_cmd *)
358 DBDMA_ALIGN (pb->priv_space);
359 pb->overlay_last2 = pb->ch2_cmd = pb->ch1_cmd + pb->tab_size;
360 pb->ch1_cmd_phys = virt_to_bus(pb->ch1_cmd);
361 pb->cap_cmd[0] = pb->ch2_cmd + pb->tab_size;
362 pb->pre_cmd[0] = pb->cap_cmd[0] + pb->tab_size * TAB_FACTOR;
363 for (i = 1; i < MAX_GBUFFERS; i++) {
364 pb->cap_cmd[i] = pb->pre_cmd[i-1] + PLANB_DUMMY;
365 pb->pre_cmd[i] = pb->cap_cmd[i] + pb->tab_size * TAB_FACTOR;
367 pb->frame_stat=(volatile unsigned int *)(pb->pre_cmd[MAX_GBUFFERS-1]
369 pb->mask = (unsigned char *)(pb->frame_stat+MAX_GBUFFERS);
374 for (i = 0; i < MAX_GBUFFERS; i++) {
375 pb->frame_stat[i] = GBUFFER_UNUSED;
379 pb->gnorm_switch[i] = 0;
380 #ifndef PLANB_GSCANLINE
383 #endif /* PLANB_GSCANLINE */
388 pb->prev_last_fr = -999;
390 /* Reset DMA controllers */
391 planb_dbdma_stop(&pb->planb_base->ch2);
392 planb_dbdma_stop(&pb->planb_base->ch1);
397 static void planb_prepare_close(struct planb *pb)
401 /* make sure the dma's are idle */
402 planb_dbdma_stop(&pb->planb_base->ch2);
403 planb_dbdma_stop(&pb->planb_base->ch1);
404 /* free kernel memory of command buffers */
405 if(pb->priv_space != 0) {
406 kfree (pb->priv_space);
408 pb->cmd_buff_inited = 0;
411 for (i = 0; i < pb->rawbuf_size; i++) {
412 ClearPageReserved(virt_to_page(pb->rawbuf[i]));
413 free_pages((unsigned long)pb->rawbuf[i], 0);
420 /*****************************/
421 /* overlay support functions */
422 /*****************************/
424 static void overlay_start(struct planb *pb)
427 DEBUG("PlanB: overlay_start()\n");
429 if(ACTIVE & in_le32(&pb->planb_base->ch1.status)) {
431 DEBUG("PlanB: presumably, grabbing is in progress...\n");
433 planb_dbdma_stop(&pb->planb_base->ch2);
434 out_le32 (&pb->planb_base->ch2.cmdptr,
435 virt_to_bus(pb->ch2_cmd));
436 planb_dbdma_restart(&pb->planb_base->ch2);
437 st_le16 (&pb->ch1_cmd->command, DBDMA_NOP);
438 tab_cmd_dbdma(pb->last_cmd[pb->last_fr],
439 DBDMA_NOP | BR_ALWAYS,
440 virt_to_bus(pb->ch1_cmd));
442 pb->prev_last_fr = pb->last_fr;
444 if(!(ACTIVE & in_le32(&pb->planb_base->ch1.status))) {
445 IDEBUG("PlanB: became inactive "
446 "in the mean time... reactivating\n");
447 planb_dbdma_stop(&pb->planb_base->ch1);
448 out_le32 (&pb->planb_base->ch1.cmdptr,
449 virt_to_bus(pb->ch1_cmd));
450 planb_dbdma_restart(&pb->planb_base->ch1);
454 DEBUG("PlanB: currently idle, so can do whatever\n");
456 planb_dbdma_stop(&pb->planb_base->ch2);
457 planb_dbdma_stop(&pb->planb_base->ch1);
458 st_le32 (&pb->planb_base->ch2.cmdptr,
459 virt_to_bus(pb->ch2_cmd));
460 st_le32 (&pb->planb_base->ch1.cmdptr,
461 virt_to_bus(pb->ch1_cmd));
462 out_le16 (&pb->ch1_cmd->command, DBDMA_NOP);
463 planb_dbdma_restart(&pb->planb_base->ch2);
464 planb_dbdma_restart(&pb->planb_base->ch1);
470 static void overlay_stop(struct planb *pb)
472 DEBUG("PlanB: overlay_stop()\n");
474 if(pb->last_fr == -1) {
476 DEBUG("PlanB: no grabbing, it seems...\n");
478 planb_dbdma_stop(&pb->planb_base->ch2);
479 planb_dbdma_stop(&pb->planb_base->ch1);
481 } else if(pb->last_fr == -2) {
482 unsigned int cmd_dep;
483 tab_cmd_dbdma(pb->cap_cmd[pb->prev_last_fr], DBDMA_STOP, 0);
485 cmd_dep = (unsigned int)in_le32(&pb->overlay_last1->cmd_dep);
486 if(overlay_is_active(pb)) {
488 DEBUG("PlanB: overlay is currently active\n");
490 planb_dbdma_stop(&pb->planb_base->ch2);
491 planb_dbdma_stop(&pb->planb_base->ch1);
492 if(cmd_dep != pb->ch1_cmd_phys) {
493 out_le32(&pb->planb_base->ch1.cmdptr,
494 virt_to_bus(pb->overlay_last1));
495 planb_dbdma_restart(&pb->planb_base->ch1);
498 pb->last_fr = pb->prev_last_fr;
499 pb->prev_last_fr = -999;
504 static void suspend_overlay(struct planb *pb)
507 struct dbdma_cmd last;
509 DEBUG("PlanB: suspend_overlay: %d\n", pb->suspend);
513 if(ACTIVE & in_le32(&pb->planb_base->ch1.status)) {
514 if(pb->last_fr == -2) {
515 fr = pb->prev_last_fr;
516 memcpy(&last, (void*)pb->last_cmd[fr], sizeof(last));
517 tab_cmd_dbdma(pb->last_cmd[fr], DBDMA_STOP, 0);
519 if(overlay_is_active(pb)) {
520 planb_dbdma_stop(&pb->planb_base->ch2);
521 planb_dbdma_stop(&pb->planb_base->ch1);
522 pb->suspended.overlay = 1;
523 pb->suspended.frame = fr;
524 memcpy(&pb->suspended.cmd, &last, sizeof(last));
528 pb->suspended.overlay = 0;
529 pb->suspended.frame = fr;
530 memcpy(&pb->suspended.cmd, &last, sizeof(last));
534 static void resume_overlay(struct planb *pb)
537 DEBUG("PlanB: resume_overlay: %d\n", pb->suspend);
541 if(pb->suspended.frame != -1) {
542 memcpy((void*)pb->last_cmd[pb->suspended.frame],
543 &pb->suspended.cmd, sizeof(pb->suspended.cmd));
545 if(ACTIVE & in_le32(&pb->planb_base->ch1.status)) {
548 if(pb->suspended.overlay) {
550 DEBUG("PlanB: overlay being resumed\n");
552 st_le16 (&pb->ch1_cmd->command, DBDMA_NOP);
553 st_le16 (&pb->ch2_cmd->command, DBDMA_NOP);
554 /* Set command buffer addresses */
555 st_le32(&pb->planb_base->ch1.cmdptr,
556 virt_to_bus(pb->overlay_last1));
557 out_le32(&pb->planb_base->ch2.cmdptr,
558 virt_to_bus(pb->overlay_last2));
559 /* Start the DMA controller */
560 out_le32 (&pb->planb_base->ch2.control,
561 PLANB_CLR(PAUSE) | PLANB_SET(RUN|WAKE));
562 out_le32 (&pb->planb_base->ch1.control,
563 PLANB_CLR(PAUSE) | PLANB_SET(RUN|WAKE));
564 } else if(pb->suspended.frame != -1) {
565 out_le32(&pb->planb_base->ch1.cmdptr,
566 virt_to_bus(pb->last_cmd[pb->suspended.frame]));
567 out_le32 (&pb->planb_base->ch1.control,
568 PLANB_CLR(PAUSE) | PLANB_SET(RUN|WAKE));
573 wake_up_interruptible(&pb->suspendq);
576 static void add_clip(struct planb *pb, struct video_clip *clip)
578 volatile unsigned char *base;
579 int xc = clip->x, yc = clip->y;
580 int wc = clip->width, hc = clip->height;
581 int ww = pb->win.width, hw = pb->win.height;
582 int x, y, xtmp1, xtmp2;
584 DEBUG("PlanB: clip %dx%d+%d+%d\n", wc, hc, xc, yc);
596 if(wc <= 0) /* Nothing to do */
601 for (y = yc; y < yc+hc; y++) {
604 base = pb->mask + y*96;
605 if(xc != 0 || wc >= 8)
606 *(base + xtmp1) &= (unsigned char)(0x00ff &
608 for (x = xtmp1 + 1; x < xtmp2; x++) {
612 *(base + xtmp2) &= (unsigned char)(0x00ff >>
619 static void fill_cmd_buff(struct planb *pb)
622 volatile struct dbdma_cmd last;
624 DEBUG("PlanB: fill_cmd_buff()\n");
626 if(pb->overlay_last1 != pb->ch1_cmd) {
628 last = *(pb->overlay_last1);
630 memset ((void *) pb->ch1_cmd, 0, 2 * pb->tab_size
631 * sizeof(struct dbdma_cmd));
634 *(pb->overlay_last1) = last;
635 if(pb->suspended.overlay) {
636 unsigned long jump_addr = in_le32(&pb->overlay_last1->cmd_dep);
637 if(jump_addr != pb->ch1_cmd_phys) {
640 DEBUG("PlanB: adjusting ch1's jump address\n");
642 for(i = 0; i < MAX_GBUFFERS; i++) {
643 if(pb->need_pre_capture[i]) {
644 if(jump_addr == virt_to_bus(pb->pre_cmd[i]))
647 if(jump_addr == virt_to_bus(pb->cap_cmd[i]))
652 DEBUG("PlanB: not found...\n");
656 if(pb->need_pre_capture[i])
657 out_le32(&pb->pre_cmd[i]->phy_addr,
658 virt_to_bus(pb->overlay_last1));
660 out_le32(&pb->cap_cmd[i]->phy_addr,
661 virt_to_bus(pb->overlay_last1));
665 pb->cmd_buff_inited = 1;
670 static void cmd_buff(struct planb *pb)
672 int i, bpp, count, nlines, stepsize, interlace;
673 unsigned long base, jump, addr_com, addr_dep;
674 volatile struct dbdma_cmd *c1 = pb->ch1_cmd;
675 volatile struct dbdma_cmd *c2 = pb->ch2_cmd;
677 interlace = pb->win.interlace;
679 count = (bpp * ((pb->win.x + pb->win.width > pb->win.swidth) ?
680 (pb->win.swidth - pb->win.x) : pb->win.width));
681 nlines = ((pb->win.y + pb->win.height > pb->win.sheight) ?
682 (pb->win.sheight - pb->win.y) : pb->win.height);
686 /* Preamble commands: */
687 addr_com = virt_to_bus(c1);
688 addr_dep = virt_to_bus(&c1->cmd_dep);
689 tab_cmd_dbdma(c1++, DBDMA_NOP, 0);
690 jump = virt_to_bus(c1+16); /* 14 by cmd_geo_setup() and 2 for padding */
691 if((c1 = cmd_geo_setup(c1, pb->win.width, pb->win.height, interlace,
692 bpp, 1, pb)) == NULL) {
693 printk(KERN_WARNING "PlanB: encountered serious problems\n");
694 tab_cmd_dbdma(pb->ch1_cmd + 1, DBDMA_STOP, 0);
695 tab_cmd_dbdma(pb->ch2_cmd + 1, DBDMA_STOP, 0);
698 tab_cmd_store(c1++, addr_com, (unsigned)(DBDMA_NOP | BR_ALWAYS) << 16);
699 tab_cmd_store(c1++, addr_dep, jump);
700 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.wait_sel),
701 PLANB_SET(FIELD_SYNC));
702 /* (1) wait for field sync to be set */
703 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
704 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
705 PLANB_SET(ODD_FIELD));
706 /* wait for field sync to be cleared */
707 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
708 /* if not odd field, wait until field sync is set again */
709 tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFSET, virt_to_bus(c1-3)); c1++;
710 /* assert ch_sync to ch2 */
711 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch2.control),
713 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
714 PLANB_SET(DMA_ABORT));
716 base = (pb->frame_buffer_phys + pb->offset + pb->win.y * (pb->win.bpl
717 + pb->win.pad) + pb->win.x * bpp);
721 jump = virt_to_bus(c1 + (nlines + 1) / 2);
724 jump = virt_to_bus(c1 + nlines);
727 /* even field data: */
728 for (i=0; i < nlines; i += stepsize, c1++)
729 tab_cmd_gen(c1, INPUT_MORE | KEY_STREAM0 | BR_IFSET,
730 count, base + i * (pb->win.bpl + pb->win.pad), jump);
732 /* For non-interlaced, we use even fields only */
734 goto cmd_tab_data_end;
736 /* Resync to odd field */
737 /* (2) wait for field sync to be set */
738 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
739 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
740 PLANB_SET(ODD_FIELD));
741 /* wait for field sync to be cleared */
742 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
743 /* if not odd field, wait until field sync is set again */
744 tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFCLR, virt_to_bus(c1-3)); c1++;
745 /* assert ch_sync to ch2 */
746 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch2.control),
748 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
749 PLANB_SET(DMA_ABORT));
751 /* odd field data: */
752 jump = virt_to_bus(c1 + nlines / 2);
753 for (i=1; i < nlines; i += stepsize, c1++)
754 tab_cmd_gen(c1, INPUT_MORE | KEY_STREAM0 | BR_IFSET, count,
755 base + i * (pb->win.bpl + pb->win.pad), jump);
757 /* And jump back to the start */
759 pb->overlay_last1 = c1; /* keep a pointer to the last command */
760 tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, virt_to_bus(pb->ch1_cmd));
762 /* Clipmask command buffer */
764 /* Preamble commands: */
765 tab_cmd_dbdma(c2++, DBDMA_NOP, 0);
766 tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.wait_sel),
768 /* wait until ch1 asserts ch_sync */
769 tab_cmd_dbdma(c2++, DBDMA_NOP | WAIT_IFCLR, 0);
770 /* clear ch_sync asserted by ch1 */
771 tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.control),
773 tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.wait_sel),
774 PLANB_SET(FIELD_SYNC));
775 tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.br_sel),
776 PLANB_SET(ODD_FIELD));
778 /* jump to end of even field if appropriate */
779 /* this points to (interlace)? pos. C: pos. B */
780 jump = (interlace) ? virt_to_bus(c2 + (nlines + 1) / 2 + 2):
781 virt_to_bus(c2 + nlines + 2);
782 /* if odd field, skip over to odd field clipmasking */
783 tab_cmd_dbdma(c2++, DBDMA_NOP | BR_IFSET, jump);
785 /* even field mask: */
786 tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.br_sel),
787 PLANB_SET(DMA_ABORT));
788 /* this points to pos. B */
789 jump = (interlace) ? virt_to_bus(c2 + nlines + 1):
790 virt_to_bus(c2 + nlines);
791 base = virt_to_bus(pb->mask);
792 for (i=0; i < nlines; i += stepsize, c2++)
793 tab_cmd_gen(c2, OUTPUT_MORE | KEY_STREAM0 | BR_IFSET, 96,
794 base + i * 96, jump);
796 /* For non-interlaced, we use only even fields */
798 goto cmd_tab_mask_end;
800 /* odd field mask: */
801 /* C */ tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.br_sel),
802 PLANB_SET(DMA_ABORT));
803 /* this points to pos. B */
804 jump = virt_to_bus(c2 + nlines / 2);
805 base = virt_to_bus(pb->mask);
806 for (i=1; i < nlines; i += 2, c2++) /* abort if set */
807 tab_cmd_gen(c2, OUTPUT_MORE | KEY_STREAM0 | BR_IFSET, 96,
808 base + i * 96, jump);
810 /* Inform channel 1 and jump back to start */
812 /* ok, I just realized this is kind of flawed. */
813 /* this part is reached only after odd field clipmasking. */
814 /* wanna clean up? */
815 /* wait for field sync to be set */
816 /* corresponds to fsync (1) of ch1 */
817 /* B */ tab_cmd_dbdma(c2++, DBDMA_NOP | WAIT_IFCLR, 0);
818 /* restart ch1, meant to clear any dead bit or something */
819 tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch1.control),
821 tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch1.control),
823 pb->overlay_last2 = c2; /* keep a pointer to the last command */
824 /* start over even field clipmasking */
825 tab_cmd_dbdma(c2, DBDMA_NOP | BR_ALWAYS, virt_to_bus(pb->ch2_cmd));
831 /*********************************/
832 /* grabdisplay support functions */
833 /*********************************/
835 static int palette2fmt[] = {
853 #define PLANB_PALETTE_MAX 15
855 static inline int overlay_is_active(struct planb *pb)
857 unsigned int size = pb->tab_size * sizeof(struct dbdma_cmd);
858 unsigned int caddr = (unsigned)in_le32(&pb->planb_base->ch1.cmdptr);
860 return (in_le32(&pb->overlay_last1->cmd_dep) == pb->ch1_cmd_phys)
861 && (caddr < (pb->ch1_cmd_phys + size))
862 && (caddr >= (unsigned)pb->ch1_cmd_phys);
865 static int vgrab(struct planb *pb, struct video_mmap *mp)
867 unsigned int fr = mp->frame;
870 if(pb->rawbuf==NULL) {
872 if((err=grabbuf_alloc(pb)))
876 IDEBUG("PlanB: grab %d: %dx%d(%u)\n", pb->grabbing,
877 mp->width, mp->height, fr);
879 if(pb->grabbing >= MAX_GBUFFERS)
881 if(fr > (MAX_GBUFFERS - 1) || fr < 0)
883 if(mp->height <= 0 || mp->width <= 0)
885 if(mp->format < 0 || mp->format >= PLANB_PALETTE_MAX)
887 if((format = palette2fmt[mp->format]) == 0)
889 if (mp->height * mp->width * format > PLANB_MAX_FBUF) /* format = bpp */
893 if(mp->width != pb->gwidth[fr] || mp->height != pb->gheight[fr] ||
894 format != pb->gfmt[fr] || (pb->gnorm_switch[fr])) {
896 #ifndef PLANB_GSCANLINE
897 unsigned int osize = pb->gwidth[fr] * pb->gheight[fr]
899 unsigned int nsize = mp->width * mp->height * format;
902 IDEBUG("PlanB: gwidth = %d, gheight = %d, mp->format = %u\n",
903 mp->width, mp->height, mp->format);
905 #ifndef PLANB_GSCANLINE
906 if(pb->gnorm_switch[fr])
909 for(i = pb->gbuf_idx[fr]; osize > 0; i++) {
910 memset((void *)pb->rawbuf[i], 0, PAGE_SIZE);
914 for(i = pb->l_fr_addr_idx[fr]; i < pb->l_fr_addr_idx[fr]
916 memset((void *)pb->rawbuf[i], 0, PAGE_SIZE);
920 if(pb->gnorm_switch[fr])
921 memset((void *)pb->gbuffer[fr], 0,
922 pb->gbytes_per_line * pb->gheight[fr]);
925 for(i = 0; i < pb->gheight[fr]; i++) {
926 memset((void *)(pb->gbuffer[fr]
927 + pb->gbytes_per_line * i
932 pb->gwidth[fr] = mp->width;
933 pb->gheight[fr] = mp->height;
934 pb->gfmt[fr] = format;
935 pb->last_cmd[fr] = setup_grab_cmd(fr, pb);
936 planb_pre_capture(fr, pb->gfmt[fr], pb); /* gfmt = bpp */
937 pb->need_pre_capture[fr] = 1;
938 pb->gnorm_switch[fr] = 0;
940 pb->need_pre_capture[fr] = 0;
941 pb->frame_stat[fr] = GBUFFER_GRABBING;
942 if(!(ACTIVE & in_le32(&pb->planb_base->ch1.status))) {
944 IDEBUG("PlanB: ch1 inactive, initiating grabbing\n");
946 planb_dbdma_stop(&pb->planb_base->ch1);
947 if(pb->need_pre_capture[fr]) {
949 IDEBUG("PlanB: padding pre-capture sequence\n");
951 out_le32 (&pb->planb_base->ch1.cmdptr,
952 virt_to_bus(pb->pre_cmd[fr]));
954 tab_cmd_dbdma(pb->last_cmd[fr], DBDMA_STOP, 0);
955 tab_cmd_dbdma(pb->cap_cmd[fr], DBDMA_NOP, 0);
956 /* let's be on the safe side. here is not timing critical. */
957 tab_cmd_dbdma((pb->cap_cmd[fr] + 1), DBDMA_NOP, 0);
958 out_le32 (&pb->planb_base->ch1.cmdptr,
959 virt_to_bus(pb->cap_cmd[fr]));
961 planb_dbdma_restart(&pb->planb_base->ch1);
966 IDEBUG("PlanB: ch1 active, grabbing being queued\n");
968 if((pb->last_fr == -1) || ((pb->last_fr == -2) &&
969 overlay_is_active(pb))) {
971 IDEBUG("PlanB: overlay is active, grabbing defered\n");
973 tab_cmd_dbdma(pb->last_cmd[fr],
974 DBDMA_NOP | BR_ALWAYS,
975 virt_to_bus(pb->ch1_cmd));
976 if(pb->need_pre_capture[fr]) {
978 IDEBUG("PlanB: padding pre-capture sequence\n");
980 tab_cmd_store(pb->pre_cmd[fr],
981 virt_to_bus(&pb->overlay_last1->cmd_dep),
982 virt_to_bus(pb->ch1_cmd));
984 out_le32 (&pb->overlay_last1->cmd_dep,
985 virt_to_bus(pb->pre_cmd[fr]));
987 tab_cmd_store(pb->cap_cmd[fr],
988 virt_to_bus(&pb->overlay_last1->cmd_dep),
989 virt_to_bus(pb->ch1_cmd));
990 tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
993 out_le32 (&pb->overlay_last1->cmd_dep,
994 virt_to_bus(pb->cap_cmd[fr]));
996 for(i = 0; overlay_is_active(pb) && i < 999; i++)
997 IDEBUG("PlanB: waiting for overlay done\n");
998 tab_cmd_dbdma(pb->ch1_cmd, DBDMA_NOP, 0);
999 pb->prev_last_fr = fr;
1001 } else if(pb->last_fr == -2) {
1003 IDEBUG("PlanB: mixed mode detected, grabbing"
1004 " will be done before activating overlay\n");
1006 tab_cmd_dbdma(pb->ch1_cmd, DBDMA_NOP, 0);
1007 if(pb->need_pre_capture[fr]) {
1009 IDEBUG("PlanB: padding pre-capture sequence\n");
1011 tab_cmd_dbdma(pb->last_cmd[pb->prev_last_fr],
1012 DBDMA_NOP | BR_ALWAYS,
1013 virt_to_bus(pb->pre_cmd[fr]));
1016 tab_cmd_dbdma(pb->cap_cmd[fr], DBDMA_NOP, 0);
1017 if(pb->gwidth[pb->prev_last_fr] !=
1019 || pb->gheight[pb->prev_last_fr] !=
1021 || pb->gfmt[pb->prev_last_fr] !=
1023 tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
1026 tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
1027 DBDMA_NOP | BR_ALWAYS,
1028 virt_to_bus(pb->cap_cmd[fr] + 16));
1029 tab_cmd_dbdma(pb->last_cmd[pb->prev_last_fr],
1030 DBDMA_NOP | BR_ALWAYS,
1031 virt_to_bus(pb->cap_cmd[fr]));
1034 tab_cmd_dbdma(pb->last_cmd[fr],
1035 DBDMA_NOP | BR_ALWAYS,
1036 virt_to_bus(pb->ch1_cmd));
1038 pb->prev_last_fr = fr;
1042 IDEBUG("PlanB: active grabbing session detected\n");
1044 if(pb->need_pre_capture[fr]) {
1046 IDEBUG("PlanB: padding pre-capture sequence\n");
1048 tab_cmd_dbdma(pb->last_cmd[pb->last_fr],
1049 DBDMA_NOP | BR_ALWAYS,
1050 virt_to_bus(pb->pre_cmd[fr]));
1053 tab_cmd_dbdma(pb->last_cmd[fr], DBDMA_STOP, 0);
1054 tab_cmd_dbdma(pb->cap_cmd[fr], DBDMA_NOP, 0);
1055 if(pb->gwidth[pb->last_fr] != pb->gwidth[fr]
1056 || pb->gheight[pb->last_fr] !=
1058 || pb->gfmt[pb->last_fr] !=
1060 tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
1063 tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
1064 DBDMA_NOP | BR_ALWAYS,
1065 virt_to_bus(pb->cap_cmd[fr] + 16));
1066 tab_cmd_dbdma(pb->last_cmd[pb->last_fr],
1067 DBDMA_NOP | BR_ALWAYS,
1068 virt_to_bus(pb->cap_cmd[fr]));
1073 if(!(ACTIVE & in_le32(&pb->planb_base->ch1.status))) {
1075 IDEBUG("PlanB: became inactive in the mean time..."
1078 planb_dbdma_stop(&pb->planb_base->ch1);
1079 out_le32 (&pb->planb_base->ch1.cmdptr,
1080 virt_to_bus(pb->cap_cmd[fr]));
1081 planb_dbdma_restart(&pb->planb_base->ch1);
1090 static void planb_pre_capture(int fr, int bpp, struct planb *pb)
1092 volatile struct dbdma_cmd *c1 = pb->pre_cmd[fr];
1093 int interlace = (pb->gheight[fr] > pb->maxlines/2)? 1: 0;
1095 tab_cmd_dbdma(c1++, DBDMA_NOP, 0);
1096 if((c1 = cmd_geo_setup(c1, pb->gwidth[fr], pb->gheight[fr], interlace,
1097 bpp, 0, pb)) == NULL) {
1098 printk(KERN_WARNING "PlanB: encountered some problems\n");
1099 tab_cmd_dbdma(pb->pre_cmd[fr] + 1, DBDMA_STOP, 0);
1102 /* Sync to even field */
1103 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.wait_sel),
1104 PLANB_SET(FIELD_SYNC));
1105 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
1106 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
1107 PLANB_SET(ODD_FIELD));
1108 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
1109 tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFSET, virt_to_bus(c1-3)); c1++;
1110 tab_cmd_dbdma(c1++, DBDMA_NOP | INTR_ALWAYS, 0);
1111 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
1112 PLANB_SET(DMA_ABORT));
1113 /* For non-interlaced, we use even fields only */
1114 if (pb->gheight[fr] <= pb->maxlines/2)
1115 goto cmd_tab_data_end;
1116 /* Sync to odd field */
1117 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
1118 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
1119 PLANB_SET(ODD_FIELD));
1120 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
1121 tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFCLR, virt_to_bus(c1-3)); c1++;
1122 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
1123 PLANB_SET(DMA_ABORT));
1125 tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, virt_to_bus(pb->cap_cmd[fr]));
1130 static volatile struct dbdma_cmd *setup_grab_cmd(int fr, struct planb *pb)
1132 int i, bpp, count, nlines, stepsize, interlace;
1133 #ifdef PLANB_GSCANLINE
1136 int nlpp, leftover1;
1141 volatile struct dbdma_cmd *c1;
1142 volatile struct dbdma_cmd *jump_addr;
1144 c1 = pb->cap_cmd[fr];
1145 interlace = (pb->gheight[fr] > pb->maxlines/2)? 1: 0;
1146 bpp = pb->gfmt[fr]; /* gfmt = bpp */
1147 count = bpp * pb->gwidth[fr];
1148 nlines = pb->gheight[fr];
1149 #ifdef PLANB_GSCANLINE
1150 scanline = pb->gbytes_per_line;
1152 pb->lsize[fr] = count;
1158 /* Preamble commands: */
1159 tab_cmd_dbdma(c1++, DBDMA_NOP, 0);
1160 tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, virt_to_bus(c1 + 16)); c1++;
1161 if((c1 = cmd_geo_setup(c1, pb->gwidth[fr], pb->gheight[fr], interlace,
1162 bpp, 0, pb)) == NULL) {
1163 printk(KERN_WARNING "PlanB: encountered serious problems\n");
1164 tab_cmd_dbdma(pb->cap_cmd[fr] + 1, DBDMA_STOP, 0);
1165 return (pb->cap_cmd[fr] + 2);
1167 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.wait_sel),
1168 PLANB_SET(FIELD_SYNC));
1169 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
1170 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
1171 PLANB_SET(ODD_FIELD));
1172 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
1173 tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFSET, virt_to_bus(c1-3)); c1++;
1174 tab_cmd_dbdma(c1++, DBDMA_NOP | INTR_ALWAYS, 0);
1175 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
1176 PLANB_SET(DMA_ABORT));
1180 jump_addr = c1 + TAB_FACTOR * (nlines + 1) / 2;
1183 jump_addr = c1 + TAB_FACTOR * nlines;
1185 jump = virt_to_bus(jump_addr);
1187 /* even field data: */
1189 pagei = pb->gbuf_idx[fr];
1190 #ifdef PLANB_GSCANLINE
1191 for (i = 0; i < nlines; i += stepsize) {
1192 tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count,
1193 virt_to_bus(pb->rawbuf[pagei
1194 + i * scanline / PAGE_SIZE]), jump);
1202 base = virt_to_bus(pb->rawbuf[pagei]);
1203 nlpp = (PAGE_SIZE - leftover1) / count / stepsize;
1204 for(j = 0; j < nlpp && i < nlines; j++, i += stepsize, c1++)
1205 tab_cmd_gen(c1, INPUT_MORE | KEY_STREAM0 | BR_IFSET,
1206 count, base + count * j * stepsize + leftover1, jump);
1208 int lov0 = PAGE_SIZE - count * nlpp * stepsize - leftover1;
1214 tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count, base
1215 + count * nlpp * stepsize + leftover1, jump);
1217 pb->l_to_addr[fr][pb->lnum[fr]] = pb->rawbuf[pagei]
1218 + count * nlpp * stepsize + leftover1;
1219 pb->l_to_next_idx[fr][pb->lnum[fr]] = pagei + 1;
1220 pb->l_to_next_size[fr][pb->lnum[fr]] = count - lov0;
1221 tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count,
1222 virt_to_bus(pb->rawbuf[pb->l_fr_addr_idx[fr]
1223 + pb->lnum[fr]]), jump);
1224 if(++pb->lnum[fr] > MAX_LNUM)
1227 leftover1 = count * stepsize - lov0;
1232 } while(i < nlines);
1233 tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, jump);
1235 #endif /* PLANB_GSCANLINE */
1237 /* For non-interlaced, we use even fields only */
1239 goto cmd_tab_data_end;
1241 /* Sync to odd field */
1242 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
1243 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
1244 PLANB_SET(ODD_FIELD));
1245 tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
1246 tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFCLR, virt_to_bus(c1-3)); c1++;
1247 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
1248 PLANB_SET(DMA_ABORT));
1250 /* odd field data: */
1251 jump_addr = c1 + TAB_FACTOR * nlines / 2;
1252 jump = virt_to_bus(jump_addr);
1253 #ifdef PLANB_GSCANLINE
1254 for (i = 1; i < nlines; i += stepsize) {
1255 tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count,
1256 virt_to_bus(pb->rawbuf[pagei
1257 + i * scanline / PAGE_SIZE]), jump);
1262 pagei = pb->gbuf_idx[fr];
1268 base = virt_to_bus(pb->rawbuf[pagei]);
1269 nlpp = (PAGE_SIZE - leftover1) / count / stepsize;
1270 if(leftover1 >= count) {
1271 tab_cmd_gen(c1++, INPUT_MORE | KEY_STREAM0 | BR_IFSET, count,
1272 base + leftover1 - count, jump);
1275 for(j = 0; j < nlpp && i < nlines; j++, i += stepsize, c1++)
1276 tab_cmd_gen(c1, INPUT_MORE | KEY_STREAM0 | BR_IFSET, count,
1277 base + count * (j * stepsize + 1) + leftover1, jump);
1279 int lov0 = PAGE_SIZE - count * nlpp * stepsize - leftover1;
1285 pb->l_to_addr[fr][pb->lnum[fr]] = pb->rawbuf[pagei]
1286 + count * (nlpp * stepsize + 1) + leftover1;
1287 pb->l_to_next_idx[fr][pb->lnum[fr]] = pagei + 1;
1288 pb->l_to_next_size[fr][pb->lnum[fr]] = count * stepsize
1290 tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count,
1291 virt_to_bus(pb->rawbuf[pb->l_fr_addr_idx[fr]
1292 + pb->lnum[fr]]), jump);
1293 if(++pb->lnum[fr] > MAX_LNUM)
1297 leftover1 = count * stepsize - lov0;
1301 } while(i < nlines);
1303 tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, jump);
1305 #endif /* PLANB_GSCANLINE */
1308 tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->intr_stat),
1309 (fr << 9) | PLANB_FRM_IRQ | PLANB_GEN_IRQ);
1311 tab_cmd_dbdma(c1, DBDMA_STOP, 0);
1317 static void planb_irq(int irq, void *dev_id, struct pt_regs * regs)
1319 unsigned int stat, astat;
1320 struct planb *pb = (struct planb *)dev_id;
1322 IDEBUG("PlanB: planb_irq()\n");
1324 /* get/clear interrupt status bits */
1326 stat = in_le32(&pb->planb_base->intr_stat);
1327 astat = stat & pb->intr_mask;
1328 out_le32(&pb->planb_base->intr_stat, PLANB_FRM_IRQ
1329 & ~astat & stat & ~PLANB_GEN_IRQ);
1330 IDEBUG("PlanB: stat = %X, astat = %X\n", stat, astat);
1332 if(astat & PLANB_FRM_IRQ) {
1333 unsigned int fr = stat >> 9;
1334 #ifndef PLANB_GSCANLINE
1337 IDEBUG("PlanB: PLANB_FRM_IRQ\n");
1341 IDEBUG("PlanB: grab %d: fr = %d, gcount = %d\n",
1342 pb->grabbing, fr, pb->gcount);
1343 #ifndef PLANB_GSCANLINE
1344 IDEBUG("PlanB: %d * %d bytes are being copied over\n",
1345 pb->lnum[fr], pb->lsize[fr]);
1346 for(i = 0; i < pb->lnum[fr]; i++) {
1347 int first = pb->lsize[fr] - pb->l_to_next_size[fr][i];
1349 memcpy(pb->l_to_addr[fr][i],
1350 pb->rawbuf[pb->l_fr_addr_idx[fr] + i],
1352 memcpy(pb->rawbuf[pb->l_to_next_idx[fr][i]],
1353 pb->rawbuf[pb->l_fr_addr_idx[fr] + i] + first,
1354 pb->l_to_next_size[fr][i]);
1357 pb->frame_stat[fr] = GBUFFER_DONE;
1359 wake_up_interruptible(&pb->capq);
1362 /* incorrect interrupts? */
1363 pb->intr_mask = PLANB_CLR_IRQ;
1364 out_le32(&pb->planb_base->intr_stat, PLANB_CLR_IRQ);
1365 printk(KERN_ERR "PlanB: IRQ lockup, cleared intrrupts"
1366 " unconditionally\n");
1369 /*******************************
1370 * Device Operations functions *
1371 *******************************/
1373 static int planb_open(struct video_device *dev, int mode)
1375 struct planb *pb = (struct planb *)dev;
1377 if (pb->user == 0) {
1379 if((err = planb_prepare_open(pb)) != 0)
1384 DEBUG("PlanB: device opened\n");
1388 static void planb_close(struct video_device *dev)
1390 struct planb *pb = (struct planb *)dev;
1392 if(pb->user < 1) /* ??? */
1395 if (pb->user == 1) {
1397 planb_dbdma_stop(&pb->planb_base->ch2);
1398 planb_dbdma_stop(&pb->planb_base->ch1);
1401 planb_prepare_close(pb);
1406 DEBUG("PlanB: device closed\n");
1409 static long planb_read(struct video_device *v, char *buf, unsigned long count,
1412 DEBUG("planb: read request\n");
1416 static long planb_write(struct video_device *v, const char *buf,
1417 unsigned long count, int nonblock)
1419 DEBUG("planb: write request\n");
1423 static int planb_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
1425 struct planb *pb=(struct planb *)dev;
1431 struct video_capability b;
1433 DEBUG("PlanB: IOCTL VIDIOCGCAP\n");
1435 strcpy (b.name, pb->video_dev.name);
1436 b.type = VID_TYPE_OVERLAY | VID_TYPE_CLIPPING |
1437 VID_TYPE_FRAMERAM | VID_TYPE_SCALES |
1439 b.channels = 2; /* composite & svhs */
1441 b.maxwidth = PLANB_MAXPIXELS;
1442 b.maxheight = PLANB_MAXLINES;
1443 b.minwidth = 32; /* wild guess */
1445 if (copy_to_user(arg,&b,sizeof(b)))
1451 struct video_buffer v;
1455 DEBUG("PlanB: IOCTL VIDIOCSFBUF\n");
1457 if (!capable(CAP_SYS_ADMIN)
1458 || !capable(CAP_SYS_RAWIO))
1460 if (copy_from_user(&v, arg,sizeof(v)))
1471 fmt = PLANB_COLOUR15;
1476 fmt = PLANB_COLOUR32;
1482 if (bpp * v.width > v.bytesperline) {
1487 pb->win.color_fmt = fmt;
1488 pb->frame_buffer_phys = (unsigned long) v.base;
1489 pb->win.sheight = v.height;
1490 pb->win.swidth = v.width;
1491 pb->picture.depth = pb->win.depth = v.depth;
1492 pb->win.bpl = pb->win.bpp * pb->win.swidth;
1493 pb->win.pad = v.bytesperline - pb->win.bpl;
1495 DEBUG("PlanB: Display at %p is %d by %d, bytedepth %d,"
1496 " bpl %d (+ %d)\n", v.base, v.width,v.height,
1497 pb->win.bpp, pb->win.bpl, pb->win.pad);
1499 pb->cmd_buff_inited = 0;
1501 suspend_overlay(pb);
1510 struct video_buffer v;
1512 DEBUG("PlanB: IOCTL VIDIOCGFBUF\n");
1514 v.base = (void *)pb->frame_buffer_phys;
1515 v.height = pb->win.sheight;
1516 v.width = pb->win.swidth;
1517 v.depth = pb->win.depth;
1518 v.bytesperline = pb->win.bpl + pb->win.pad;
1519 if (copy_to_user(arg, &v, sizeof(v)))
1527 if(copy_from_user(&i, arg, sizeof(i)))
1530 DEBUG("PlanB: IOCTL VIDIOCCAPTURE Stop\n");
1539 DEBUG("PlanB: IOCTL VIDIOCCAPTURE Start\n");
1541 if (pb->frame_buffer_phys == 0 ||
1542 pb->win.width == 0 ||
1543 pb->win.height == 0)
1549 if(!(pb->cmd_buff_inited))
1558 struct video_channel v;
1560 DEBUG("PlanB: IOCTL VIDIOCGCHAN\n");
1562 if(copy_from_user(&v, arg,sizeof(v)))
1566 v.type = VIDEO_TYPE_CAMERA;
1567 v.norm = pb->win.norm;
1571 strcpy(v.name,"Composite");
1574 strcpy(v.name,"SVHS");
1580 if(copy_to_user(arg,&v,sizeof(v)))
1587 struct video_channel v;
1589 DEBUG("PlanB: IOCTL VIDIOCSCHAN\n");
1591 if(copy_from_user(&v, arg, sizeof(v)))
1594 if (v.norm != pb->win.norm) {
1599 case VIDEO_MODE_PAL:
1600 case VIDEO_MODE_SECAM:
1601 maxlines = PLANB_MAXLINES;
1603 case VIDEO_MODE_NTSC:
1604 maxlines = PLANB_NTSC_MAXLINES;
1611 /* empty the grabbing queue */
1613 interruptible_sleep_on(&pb->capq);
1614 pb->maxlines = maxlines;
1615 pb->win.norm = v.norm;
1616 /* Stop overlay if running */
1617 suspend_overlay(pb);
1618 for(i = 0; i < MAX_GBUFFERS; i++)
1619 pb->gnorm_switch[i] = 1;
1620 /* I know it's an overkill, but.... */
1622 /* ok, now init it accordingly */
1624 /* restart overlay if it was running */
1631 case 0: /* Composite */
1632 saa_set (SAA7196_IOCC,
1633 ((saa_regs[pb->win.norm][SAA7196_IOCC] &
1637 saa_set (SAA7196_IOCC,
1638 ((saa_regs[pb->win.norm][SAA7196_IOCC] &
1650 struct video_picture vp = pb->picture;
1652 DEBUG("PlanB: IOCTL VIDIOCGPICT\n");
1654 switch(pb->win.color_fmt) {
1656 vp.palette = VIDEO_PALETTE_GREY;
1657 case PLANB_COLOUR15:
1658 vp.palette = VIDEO_PALETTE_RGB555;
1660 case PLANB_COLOUR32:
1661 vp.palette = VIDEO_PALETTE_RGB32;
1668 if(copy_to_user(arg,&vp,sizeof(vp)))
1674 struct video_picture vp;
1676 DEBUG("PlanB: IOCTL VIDIOCSPICT\n");
1678 if(copy_from_user(&vp,arg,sizeof(vp)))
1681 /* Should we do sanity checks here? */
1682 saa_set (SAA7196_BRIG, (unsigned char)
1683 ((pb->picture.brightness) >> 8), pb);
1684 saa_set (SAA7196_HUEC, (unsigned char)
1685 ((pb->picture.hue) >> 8) ^ 0x80, pb);
1686 saa_set (SAA7196_CSAT, (unsigned char)
1687 ((pb->picture.colour) >> 9), pb);
1688 saa_set (SAA7196_CONT, (unsigned char)
1689 ((pb->picture.contrast) >> 9), pb);
1695 struct video_window vw;
1696 struct video_clip clip;
1699 DEBUG("PlanB: IOCTL VIDIOCSWIN\n");
1701 if(copy_from_user(&vw,arg,sizeof(vw)))
1705 /* Stop overlay if running */
1706 suspend_overlay(pb);
1707 pb->win.interlace = (vw.height > pb->maxlines/2)? 1: 0;
1708 if (pb->win.x != vw.x ||
1709 pb->win.y != vw.y ||
1710 pb->win.width != vw.width ||
1711 pb->win.height != vw.height ||
1712 !pb->cmd_buff_inited) {
1715 pb->win.width = vw.width;
1716 pb->win.height = vw.height;
1719 /* Reset clip mask */
1720 memset ((void *) pb->mask, 0xff, (pb->maxlines
1721 * ((PLANB_MAXPIXELS + 7) & ~7)) / 8);
1722 /* Add any clip rects */
1723 for (i = 0; i < vw.clipcount; i++) {
1724 if (copy_from_user(&clip, vw.clips + i,
1725 sizeof(struct video_clip)))
1727 add_clip(pb, &clip);
1729 /* restart overlay if it was running */
1736 struct video_window vw;
1738 DEBUG("PlanB: IOCTL VIDIOCGWIN\n");
1742 vw.width=pb->win.width;
1743 vw.height=pb->win.height;
1746 if(pb->win.interlace)
1747 vw.flags|=VIDEO_WINDOW_INTERLACE;
1748 if(copy_to_user(arg,&vw,sizeof(vw)))
1755 IDEBUG("PlanB: IOCTL VIDIOCSYNC\n");
1757 if(copy_from_user((void *)&i,arg,sizeof(int)))
1760 IDEBUG("PlanB: sync to frame %d\n", i);
1762 if(i > (MAX_GBUFFERS - 1) || i < 0)
1765 switch (pb->frame_stat[i]) {
1766 case GBUFFER_UNUSED:
1768 case GBUFFER_GRABBING:
1769 IDEBUG("PlanB: waiting for grab"
1771 interruptible_sleep_on(&pb->capq);
1772 if(signal_pending(current))
1776 pb->frame_stat[i] = GBUFFER_UNUSED;
1782 case VIDIOCMCAPTURE:
1784 struct video_mmap vm;
1785 volatile unsigned int status;
1787 IDEBUG("PlanB: IOCTL VIDIOCMCAPTURE\n");
1789 if(copy_from_user((void *) &vm,(void *)arg,sizeof(vm)))
1791 status = pb->frame_stat[vm.frame];
1792 if (status != GBUFFER_UNUSED)
1795 return vgrab(pb, &vm);
1801 struct video_mbuf vm;
1803 DEBUG("PlanB: IOCTL VIDIOCGMBUF\n");
1805 memset(&vm, 0 , sizeof(vm));
1806 vm.size = PLANB_MAX_FBUF * MAX_GBUFFERS;
1807 vm.frames = MAX_GBUFFERS;
1808 for(i = 0; i<MAX_GBUFFERS; i++)
1809 vm.offsets[i] = PLANB_MAX_FBUF * i;
1810 if(copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
1815 case PLANBIOCGSAAREGS:
1817 struct planb_saa_regs preg;
1819 DEBUG("PlanB: IOCTL PLANBIOCGSAAREGS\n");
1821 if(copy_from_user(&preg, arg, sizeof(preg)))
1823 if(preg.addr >= SAA7196_NUMREGS)
1825 preg.val = saa_regs[pb->win.norm][preg.addr];
1826 if(copy_to_user((void *)arg, (void *)&preg,
1832 case PLANBIOCSSAAREGS:
1834 struct planb_saa_regs preg;
1836 DEBUG("PlanB: IOCTL PLANBIOCSSAAREGS\n");
1838 if(copy_from_user(&preg, arg, sizeof(preg)))
1840 if(preg.addr >= SAA7196_NUMREGS)
1842 saa_set (preg.addr, preg.val, pb);
1848 struct planb_stat_regs pstat;
1850 DEBUG("PlanB: IOCTL PLANBIOCGSTAT\n");
1852 pstat.ch1_stat = in_le32(&pb->planb_base->ch1.status);
1853 pstat.ch2_stat = in_le32(&pb->planb_base->ch2.status);
1854 pstat.saa_stat0 = saa_status(0, pb);
1855 pstat.saa_stat1 = saa_status(1, pb);
1857 if(copy_to_user((void *)arg, (void *)&pstat,
1863 case PLANBIOCSMODE: {
1866 DEBUG("PlanB: IOCTL PLANBIOCSMODE\n");
1868 if(copy_from_user(&v, arg, sizeof(v)))
1874 saa_set (SAA7196_STDC,
1875 (saa_regs[pb->win.norm][SAA7196_STDC] &
1878 case PLANB_VTR_MODE:
1879 saa_set (SAA7196_STDC,
1880 (saa_regs[pb->win.norm][SAA7196_STDC] |
1890 case PLANBIOCGMODE: {
1893 DEBUG("PlanB: IOCTL PLANBIOCGMODE\n");
1895 if(copy_to_user(arg,&v,sizeof(v)))
1899 #ifdef PLANB_GSCANLINE
1900 case PLANBG_GRAB_BPL: {
1901 int v=pb->gbytes_per_line;
1903 DEBUG("PlanB: IOCTL PLANBG_GRAB_BPL\n");
1905 if(copy_to_user(arg,&v,sizeof(v)))
1909 #endif /* PLANB_GSCANLINE */
1910 case PLANB_INTR_DEBUG: {
1913 DEBUG("PlanB: IOCTL PLANB_INTR_DEBUG\n");
1915 if(copy_from_user(&i, arg, sizeof(i)))
1918 /* avoid hang ups all together */
1919 for (i = 0; i < MAX_GBUFFERS; i++) {
1920 if(pb->frame_stat[i] == GBUFFER_GRABBING) {
1921 pb->frame_stat[i] = GBUFFER_DONE;
1926 wake_up_interruptible(&pb->capq);
1929 case PLANB_INV_REGS: {
1931 struct planb_any_regs any;
1933 DEBUG("PlanB: IOCTL PLANB_INV_REGS\n");
1935 if(copy_from_user(&any, arg, sizeof(any)))
1937 if(any.offset < 0 || any.offset + any.bytes > 0x400)
1941 for (i = 0; i < any.bytes; i++) {
1943 in_8((unsigned char *)pb->planb_base
1946 if(copy_to_user(arg,&any,sizeof(any)))
1952 DEBUG("PlanB: Unimplemented IOCTL\n");
1953 return -ENOIOCTLCMD;
1955 /* Some IOCTLs are currently unsupported on PlanB */
1956 case VIDIOCGTUNER: {
1957 DEBUG("PlanB: IOCTL VIDIOCGTUNER\n");
1958 goto unimplemented; }
1959 case VIDIOCSTUNER: {
1960 DEBUG("PlanB: IOCTL VIDIOCSTUNER\n");
1961 goto unimplemented; }
1963 DEBUG("PlanB: IOCTL VIDIOCSFREQ\n");
1964 goto unimplemented; }
1966 DEBUG("PlanB: IOCTL VIDIOCGFREQ\n");
1967 goto unimplemented; }
1969 DEBUG("PlanB: IOCTL VIDIOCKEY\n");
1970 goto unimplemented; }
1971 case VIDIOCSAUDIO: {
1972 DEBUG("PlanB: IOCTL VIDIOCSAUDIO\n");
1973 goto unimplemented; }
1974 case VIDIOCGAUDIO: {
1975 DEBUG("PlanB: IOCTL VIDIOCGAUDIO\n");
1976 goto unimplemented; }
1978 DEBUG(" Unimplemented\n");
1979 return -ENOIOCTLCMD;
1984 static int planb_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr, unsigned long size)
1987 struct planb *pb = (struct planb *)dev;
1988 unsigned long start = (unsigned long)adr;
1990 if (size > MAX_GBUFFERS * PLANB_MAX_FBUF)
1994 if((err=grabbuf_alloc(pb)))
1997 for (i = 0; i < pb->rawbuf_size; i++) {
2000 pfn = virt_to_phys((void *)pb->rawbuf[i]) >> PAGE_SHIFT;
2001 if (remap_pfn_range(vma, start, pfn, PAGE_SIZE, PAGE_SHARED))
2004 if (size <= PAGE_SIZE)
2011 static struct video_device planb_template=
2013 .owner = THIS_MODULE,
2014 .name = PLANB_DEVICE_NAME,
2015 .type = VID_TYPE_OVERLAY,
2016 .hardware = VID_HARDWARE_PLANB,
2018 .close = planb_close,
2020 .write = planb_write,
2021 .ioctl = planb_ioctl,
2022 .mmap = planb_mmap, /* mmap? */
2025 static int init_planb(struct planb *pb)
2027 unsigned char saa_rev;
2030 memset ((void *) &pb->win, 0, sizeof (struct planb_window));
2031 /* Simple sanity check */
2032 if(def_norm >= NUM_SUPPORTED_NORM || def_norm < 0) {
2033 printk(KERN_ERR "PlanB: Option(s) invalid\n");
2036 pb->win.norm = def_norm;
2037 pb->win.mode = PLANB_TV_MODE; /* TV mode */
2038 pb->win.interlace=1;
2041 pb->win.width=768; /* 640 */
2042 pb->win.height=576; /* 480 */
2045 btv->win.cropwidth=768; /* 640 */
2046 btv->win.cropheight=576; /* 480 */
2053 pb->win.color_fmt=PLANB_COLOUR32;
2054 pb->win.bpl=1024*pb->win.bpp;
2055 pb->win.swidth=1024;
2056 pb->win.sheight=768;
2057 #ifdef PLANB_GSCANLINE
2058 if((pb->gbytes_per_line = PLANB_MAXPIXELS * 4) > PAGE_SIZE
2059 || (pb->gbytes_per_line <= 0))
2062 /* page align pb->gbytes_per_line for DMA purpose */
2063 for(i = PAGE_SIZE; pb->gbytes_per_line < (i>>1);)
2065 pb->gbytes_per_line = i;
2068 pb->tab_size = PLANB_MAXLINES + 40;
2070 init_MUTEX(&pb->lock);
2078 init_waitqueue_head(&pb->suspendq);
2079 pb->cmd_buff_inited = 0;
2080 pb->frame_buffer_phys = 0;
2082 /* Reset DMA controllers */
2083 planb_dbdma_stop(&pb->planb_base->ch2);
2084 planb_dbdma_stop(&pb->planb_base->ch1);
2086 saa_rev = (saa_status(0, pb) & 0xf0) >> 4;
2087 printk(KERN_INFO "PlanB: SAA7196 video processor rev. %d\n", saa_rev);
2088 /* Initialize the SAA registers in memory and on chip */
2091 /* clear interrupt mask */
2092 pb->intr_mask = PLANB_CLR_IRQ;
2094 result = request_irq(pb->irq, planb_irq, 0, "PlanB", (void *)pb);
2096 if (result==-EINVAL)
2097 printk(KERN_ERR "PlanB: Bad irq number (%d) "
2098 "or handler\n", (int)pb->irq);
2099 else if (result==-EBUSY)
2100 printk(KERN_ERR "PlanB: I don't know why, "
2101 "but IRQ %d is busy\n", (int)pb->irq);
2104 disable_irq(pb->irq);
2106 /* Now add the template and register the device unit. */
2107 memcpy(&pb->video_dev,&planb_template,sizeof(planb_template));
2109 pb->picture.brightness=0x90<<8;
2110 pb->picture.contrast = 0x70 << 8;
2111 pb->picture.colour = 0x70<<8;
2112 pb->picture.hue = 0x8000;
2113 pb->picture.whiteness = 0;
2114 pb->picture.depth = pb->win.depth;
2116 pb->frame_stat=NULL;
2117 init_waitqueue_head(&pb->capq);
2118 for(i=0; i<MAX_GBUFFERS; i++) {
2119 pb->gbuf_idx[i] = PLANB_MAX_FBUF * i / PAGE_SIZE;
2123 pb->cap_cmd[i]=NULL;
2124 #ifndef PLANB_GSCANLINE
2125 pb->l_fr_addr_idx[i] = MAX_GBUFFERS * (PLANB_MAX_FBUF
2126 / PAGE_SIZE + 1) + MAX_LNUM * i;
2134 /* enable interrupts */
2135 out_le32(&pb->planb_base->intr_stat, PLANB_CLR_IRQ);
2136 pb->intr_mask = PLANB_FRM_IRQ;
2137 enable_irq(pb->irq);
2139 if(video_register_device(&pb->video_dev, VFL_TYPE_GRABBER, video_nr)<0)
2146 * Scan for a PlanB controller, request the irq and map the io memory
2149 static int find_planb(void)
2152 struct device_node *planb_devices;
2153 unsigned char dev_fn, confreg, bus;
2154 unsigned int old_base, new_base;
2156 struct pci_dev *pdev;
2159 if (_machine != _MACH_Pmac)
2162 planb_devices = find_devices("planb");
2163 if (planb_devices == 0) {
2165 printk(KERN_WARNING "PlanB: no device found!\n");
2169 if (planb_devices->next != NULL)
2170 printk(KERN_ERR "Warning: only using first PlanB device!\n");
2174 if (planb_devices->n_addrs != 1) {
2175 printk (KERN_WARNING "PlanB: expecting 1 address for planb "
2176 "(got %d)", planb_devices->n_addrs);
2180 if (planb_devices->n_intrs == 0) {
2181 printk(KERN_WARNING "PlanB: no intrs for device %s\n",
2182 planb_devices->full_name);
2185 irq = planb_devices->intrs[0].line;
2188 /* Initialize PlanB's PCI registers */
2190 /* There is a bug with the way OF assigns addresses
2191 to the devices behind the chaos bridge.
2192 control needs only 0x1000 of space, but decodes only
2193 the upper 16 bits. It therefore occupies a full 64K.
2194 OF assigns the planb controller memory within this space;
2195 so we need to change that here in order to access planb. */
2197 /* We remap to 0xf1000000 in hope that nobody uses it ! */
2199 bus = (planb_devices->addrs[0].space >> 16) & 0xff;
2200 dev_fn = (planb_devices->addrs[0].space >> 8) & 0xff;
2201 confreg = planb_devices->addrs[0].space & 0xff;
2202 old_base = planb_devices->addrs[0].address;
2203 new_base = 0xf1000000;
2205 DEBUG("PlanB: Found on bus %d, dev %d, func %d, "
2206 "membase 0x%x (base reg. 0x%x)\n",
2207 bus, PCI_SLOT(dev_fn), PCI_FUNC(dev_fn), old_base, confreg);
2209 pdev = pci_find_slot (bus, dev_fn);
2211 printk(KERN_ERR "planb: cannot find slot\n");
2215 /* Enable response in memory space, bus mastering,
2216 use memory write and invalidate */
2217 rc = pci_enable_device(pdev);
2219 printk(KERN_ERR "planb: cannot enable PCI device %s\n",
2223 rc = pci_set_mwi(pdev);
2225 printk(KERN_ERR "planb: cannot enable MWI on PCI device %s\n",
2227 goto err_out_disable;
2229 pci_set_master(pdev);
2231 /* Set the new base address */
2232 pci_write_config_dword (pdev, confreg, new_base);
2234 planb_regs = (volatile struct planb_registers *)
2235 ioremap (new_base, 0x400);
2236 pb->planb_base = planb_regs;
2237 pb->planb_base_phys = (struct planb_registers *)new_base;
2243 pci_disable_device(pdev);
2245 /* FIXME handle error */ /* comment moved from pci_find_slot, above */
2249 static void release_planb(void)
2254 for (i=0;i<planb_num; i++)
2258 /* stop and flash DMAs unconditionally */
2259 planb_dbdma_stop(&pb->planb_base->ch2);
2260 planb_dbdma_stop(&pb->planb_base->ch1);
2262 /* clear and free interrupts */
2263 pb->intr_mask = PLANB_CLR_IRQ;
2264 out_le32 (&pb->planb_base->intr_stat, PLANB_CLR_IRQ);
2265 free_irq(pb->irq, pb);
2267 /* make sure all allocated memory are freed */
2268 planb_prepare_close(pb);
2270 printk(KERN_INFO "PlanB: unregistering with v4l\n");
2271 video_unregister_device(&pb->video_dev);
2273 /* note that iounmap() does nothing on the PPC right now */
2274 iounmap ((void *)pb->planb_base);
2278 static int __init init_planbs(void)
2282 if (find_planb()<=0)
2285 for (i=0; i<planb_num; i++) {
2286 if (init_planb(&planbs[i])<0) {
2287 printk(KERN_ERR "PlanB: error registering device %d"
2292 printk(KERN_INFO "PlanB: registered device %d with v4l\n", i);
2297 static void __exit exit_planbs(void)
2302 module_init(init_planbs);
2303 module_exit(exit_planbs);