2 * Zoran ZR36050 basic configuration functions - header file
4 * Copyright (C) 2001 Wolfgang Scherr <scherr@net4you.at>
6 * $Id: zr36050.h,v 1.1.2.2 2003/01/14 21:18:22 rbultje Exp $
8 * ------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * ------------------------------------------------------------------------
30 /* data stored for each zoran jpeg codec chip */
34 /* io datastructure */
35 struct videocodec *codec;
56 /* zr36050 register addresses */
57 #define ZR050_GO 0x000
58 #define ZR050_HARDWARE 0x002
59 #define ZR050_MODE 0x003
60 #define ZR050_OPTIONS 0x004
61 #define ZR050_MBCV 0x005
62 #define ZR050_MARKERS_EN 0x006
63 #define ZR050_INT_REQ_0 0x007
64 #define ZR050_INT_REQ_1 0x008
65 #define ZR050_TCV_NET_HI 0x009
66 #define ZR050_TCV_NET_MH 0x00a
67 #define ZR050_TCV_NET_ML 0x00b
68 #define ZR050_TCV_NET_LO 0x00c
69 #define ZR050_TCV_DATA_HI 0x00d
70 #define ZR050_TCV_DATA_MH 0x00e
71 #define ZR050_TCV_DATA_ML 0x00f
72 #define ZR050_TCV_DATA_LO 0x010
73 #define ZR050_SF_HI 0x011
74 #define ZR050_SF_LO 0x012
75 #define ZR050_AF_HI 0x013
76 #define ZR050_AF_M 0x014
77 #define ZR050_AF_LO 0x015
78 #define ZR050_ACV_HI 0x016
79 #define ZR050_ACV_MH 0x017
80 #define ZR050_ACV_ML 0x018
81 #define ZR050_ACV_LO 0x019
82 #define ZR050_ACT_HI 0x01a
83 #define ZR050_ACT_MH 0x01b
84 #define ZR050_ACT_ML 0x01c
85 #define ZR050_ACT_LO 0x01d
86 #define ZR050_ACV_TRUN_HI 0x01e
87 #define ZR050_ACV_TRUN_MH 0x01f
88 #define ZR050_ACV_TRUN_ML 0x020
89 #define ZR050_ACV_TRUN_LO 0x021
90 #define ZR050_STATUS_0 0x02e
91 #define ZR050_STATUS_1 0x02f
93 #define ZR050_SOF_IDX 0x040
94 #define ZR050_SOS1_IDX 0x07a
95 #define ZR050_SOS2_IDX 0x08a
96 #define ZR050_SOS3_IDX 0x09a
97 #define ZR050_SOS4_IDX 0x0aa
98 #define ZR050_DRI_IDX 0x0c0
99 #define ZR050_DNL_IDX 0x0c6
100 #define ZR050_DQT_IDX 0x0cc
101 #define ZR050_DHT_IDX 0x1d4
102 #define ZR050_APP_IDX 0x380
103 #define ZR050_COM_IDX 0x3c0
105 /* zr36050 hardware register bits */
107 #define ZR050_HW_BSWD 0x80
108 #define ZR050_HW_MSTR 0x40
109 #define ZR050_HW_DMA 0x20
110 #define ZR050_HW_CFIS_1_CLK 0x00
111 #define ZR050_HW_CFIS_2_CLK 0x04
112 #define ZR050_HW_CFIS_3_CLK 0x08
113 #define ZR050_HW_CFIS_4_CLK 0x0C
114 #define ZR050_HW_CFIS_5_CLK 0x10
115 #define ZR050_HW_CFIS_6_CLK 0x14
116 #define ZR050_HW_CFIS_7_CLK 0x18
117 #define ZR050_HW_CFIS_8_CLK 0x1C
118 #define ZR050_HW_BELE 0x01
120 /* zr36050 mode register bits */
122 #define ZR050_MO_COMP 0x80
123 #define ZR050_MO_COMP 0x80
124 #define ZR050_MO_ATP 0x40
125 #define ZR050_MO_PASS2 0x20
126 #define ZR050_MO_TLM 0x10
127 #define ZR050_MO_DCONLY 0x08
128 #define ZR050_MO_BRC 0x04
130 #define ZR050_MO_ATP 0x40
131 #define ZR050_MO_PASS2 0x20
132 #define ZR050_MO_TLM 0x10
133 #define ZR050_MO_DCONLY 0x08
135 /* zr36050 option register bits */
137 #define ZR050_OP_NSCN_1 0x00
138 #define ZR050_OP_NSCN_2 0x20
139 #define ZR050_OP_NSCN_3 0x40
140 #define ZR050_OP_NSCN_4 0x60
141 #define ZR050_OP_NSCN_5 0x80
142 #define ZR050_OP_NSCN_6 0xA0
143 #define ZR050_OP_NSCN_7 0xC0
144 #define ZR050_OP_NSCN_8 0xE0
145 #define ZR050_OP_OVF 0x10
148 /* zr36050 markers-enable register bits */
150 #define ZR050_ME_APP 0x80
151 #define ZR050_ME_COM 0x40
152 #define ZR050_ME_DRI 0x20
153 #define ZR050_ME_DQT 0x10
154 #define ZR050_ME_DHT 0x08
155 #define ZR050_ME_DNL 0x04
156 #define ZR050_ME_DQTI 0x02
157 #define ZR050_ME_DHTI 0x01
159 /* zr36050 status0/1 register bit masks */
161 #define ZR050_ST_RST_MASK 0x20
162 #define ZR050_ST_SOF_MASK 0x02
163 #define ZR050_ST_SOS_MASK 0x02
164 #define ZR050_ST_DATRDY_MASK 0x80
165 #define ZR050_ST_MRKDET_MASK 0x40
166 #define ZR050_ST_RFM_MASK 0x10
167 #define ZR050_ST_RFD_MASK 0x08
168 #define ZR050_ST_END_MASK 0x04
169 #define ZR050_ST_TCVOVF_MASK 0x02
170 #define ZR050_ST_DATOVF_MASK 0x01
172 /* pixel component idx */
174 #define ZR050_Y_COMPONENT 0
175 #define ZR050_U_COMPONENT 1
176 #define ZR050_V_COMPONENT 2
178 #endif /*fndef ZR36050_H */