2 Common Flash Interface probe code.
3 (C) 2000 Red Hat. GPL'd.
4 $Id: jedec_probe.c,v 1.51 2004/07/14 14:44:30 thayne Exp $
5 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5)
6 for the standard this probe goes back to.
8 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
11 #include <linux/config.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
17 #include <asm/byteorder.h>
18 #include <linux/errno.h>
19 #include <linux/slab.h>
20 #include <linux/interrupt.h>
21 #include <linux/init.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/map.h>
25 #include <linux/mtd/cfi.h>
26 #include <linux/mtd/gen_probe.h>
29 #define MANUFACTURER_AMD 0x0001
30 #define MANUFACTURER_ATMEL 0x001f
31 #define MANUFACTURER_FUJITSU 0x0004
32 #define MANUFACTURER_HYUNDAI 0x00AD
33 #define MANUFACTURER_INTEL 0x0089
34 #define MANUFACTURER_MACRONIX 0x00C2
35 #define MANUFACTURER_PMC 0x009D
36 #define MANUFACTURER_SST 0x00BF
37 #define MANUFACTURER_ST 0x0020
38 #define MANUFACTURER_TOSHIBA 0x0098
39 #define MANUFACTURER_WINBOND 0x00da
43 #define AM29DL800BB 0x22C8
44 #define AM29DL800BT 0x224A
46 #define AM29F800BB 0x2258
47 #define AM29F800BT 0x22D6
48 #define AM29LV400BB 0x22BA
49 #define AM29LV400BT 0x22B9
50 #define AM29LV800BB 0x225B
51 #define AM29LV800BT 0x22DA
52 #define AM29LV160DT 0x22C4
53 #define AM29LV160DB 0x2249
54 #define AM29F017D 0x003D
55 #define AM29F016D 0x00AD
56 #define AM29F080 0x00D5
57 #define AM29F040 0x00A4
58 #define AM29LV040B 0x004F
59 #define AM29F032B 0x0041
60 #define AM29F002T 0x00B0
63 #define AT49BV512 0x0003
64 #define AT29LV512 0x003d
65 #define AT49BV16X 0x00C0
66 #define AT49BV16XT 0x00C2
67 #define AT49BV32X 0x00C8
68 #define AT49BV32XT 0x00C9
71 #define MBM29F040C 0x00A4
72 #define MBM29LV650UE 0x22D7
73 #define MBM29LV320TE 0x22F6
74 #define MBM29LV320BE 0x22F9
75 #define MBM29LV160TE 0x22C4
76 #define MBM29LV160BE 0x2249
77 #define MBM29LV800BA 0x225B
78 #define MBM29LV800TA 0x22DA
79 #define MBM29LV400TC 0x22B9
80 #define MBM29LV400BC 0x22BA
83 #define HY29F002T 0x00B0
86 #define I28F004B3T 0x00d4
87 #define I28F004B3B 0x00d5
88 #define I28F400B3T 0x8894
89 #define I28F400B3B 0x8895
90 #define I28F008S5 0x00a6
91 #define I28F016S5 0x00a0
92 #define I28F008SA 0x00a2
93 #define I28F008B3T 0x00d2
94 #define I28F008B3B 0x00d3
95 #define I28F800B3T 0x8892
96 #define I28F800B3B 0x8893
97 #define I28F016S3 0x00aa
98 #define I28F016B3T 0x00d0
99 #define I28F016B3B 0x00d1
100 #define I28F160B3T 0x8890
101 #define I28F160B3B 0x8891
102 #define I28F320B3T 0x8896
103 #define I28F320B3B 0x8897
104 #define I28F640B3T 0x8898
105 #define I28F640B3B 0x8899
106 #define I82802AB 0x00ad
107 #define I82802AC 0x00ac
110 #define MX29LV160T 0x22C4
111 #define MX29LV160B 0x2249
112 #define MX29F016 0x00AD
113 #define MX29F002T 0x00B0
114 #define MX29F004T 0x0045
115 #define MX29F004B 0x0046
118 #define PM49FL002 0x006D
119 #define PM49FL004 0x006E
120 #define PM49FL008 0x006A
122 /* ST - www.st.com */
123 #define M29W800DT 0x00D7
124 #define M29W800DB 0x005B
125 #define M29W160DT 0x22C4
126 #define M29W160DB 0x2249
127 #define M29W040B 0x00E3
128 #define M50FW040 0x002C
129 #define M50FW080 0x002D
130 #define M50FW016 0x002E
133 #define SST29EE020 0x0010
134 #define SST29LE020 0x0012
135 #define SST29EE512 0x005d
136 #define SST29LE512 0x003d
137 #define SST39LF800 0x2781
138 #define SST39LF160 0x2782
139 #define SST39LF512 0x00D4
140 #define SST39LF010 0x00D5
141 #define SST39LF020 0x00D6
142 #define SST39LF040 0x00D7
143 #define SST39SF010A 0x00B5
144 #define SST39SF020A 0x00B6
145 #define SST49LF004B 0x0060
146 #define SST49LF008A 0x005a
147 #define SST49LF030A 0x001C
148 #define SST49LF040A 0x0051
149 #define SST49LF080A 0x005B
152 #define TC58FVT160 0x00C2
153 #define TC58FVB160 0x0043
154 #define TC58FVT321 0x009A
155 #define TC58FVB321 0x009C
156 #define TC58FVT641 0x0093
157 #define TC58FVB641 0x0095
160 #define W49V002A 0x00b0
164 * Unlock address sets for AMD command sets.
165 * Intel command sets use the MTD_UADDR_UNNECESSARY.
166 * Each identifier, except MTD_UADDR_UNNECESSARY, and
167 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
168 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
169 * initialization need not require initializing all of the
170 * unlock addresses for all bit widths.
173 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
174 MTD_UADDR_0x0555_0x02AA,
175 MTD_UADDR_0x0555_0x0AAA,
176 MTD_UADDR_0x5555_0x2AAA,
177 MTD_UADDR_0x0AAA_0x0555,
178 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
179 MTD_UADDR_UNNECESSARY, /* Does not require any address */
190 * I don't like the fact that the first entry in unlock_addrs[]
191 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
192 * should not be used. The problem is that structures with
193 * initializers have extra fields initialized to 0. It is _very_
194 * desireable to have the unlock address entries for unsupported
195 * data widths automatically initialized - that means that
196 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
199 static const struct unlock_addr unlock_addrs[] = {
200 [MTD_UADDR_NOT_SUPPORTED] = {
205 [MTD_UADDR_0x0555_0x02AA] = {
210 [MTD_UADDR_0x0555_0x0AAA] = {
215 [MTD_UADDR_0x5555_0x2AAA] = {
220 [MTD_UADDR_0x0AAA_0x0555] = {
225 [MTD_UADDR_DONT_CARE] = {
226 .addr1 = 0x0000, /* Doesn't matter which address */
227 .addr2 = 0x0000 /* is used - must be last entry */
232 struct amd_flash_info {
237 const int NumEraseRegions;
239 const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
240 const ulong regions[6];
243 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
245 #define SIZE_64KiB 16
246 #define SIZE_128KiB 17
247 #define SIZE_256KiB 18
248 #define SIZE_512KiB 19
256 * Please keep this list ordered by manufacturer!
257 * Fortunately, the list isn't searched often and so a
258 * slow, linear search isn't so bad.
260 static const struct amd_flash_info jedec_table[] = {
262 .mfr_id = MANUFACTURER_AMD,
264 .name = "AMD AM29F032B",
266 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
268 .DevSize = SIZE_4MiB,
269 .CmdSet = P_ID_AMD_STD,
272 ERASEINFO(0x10000,64)
275 .mfr_id = MANUFACTURER_AMD,
276 .dev_id = AM29LV160DT,
277 .name = "AMD AM29LV160DT",
279 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
280 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
282 .DevSize = SIZE_2MiB,
283 .CmdSet = P_ID_AMD_STD,
286 ERASEINFO(0x10000,31),
287 ERASEINFO(0x08000,1),
288 ERASEINFO(0x02000,2),
292 .mfr_id = MANUFACTURER_AMD,
293 .dev_id = AM29LV160DB,
294 .name = "AMD AM29LV160DB",
296 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
297 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
299 .DevSize = SIZE_2MiB,
300 .CmdSet = P_ID_AMD_STD,
303 ERASEINFO(0x04000,1),
304 ERASEINFO(0x02000,2),
305 ERASEINFO(0x08000,1),
306 ERASEINFO(0x10000,31)
309 .mfr_id = MANUFACTURER_AMD,
310 .dev_id = AM29LV400BB,
311 .name = "AMD AM29LV400BB",
313 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
314 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
316 .DevSize = SIZE_512KiB,
317 .CmdSet = P_ID_AMD_STD,
320 ERASEINFO(0x04000,1),
321 ERASEINFO(0x02000,2),
322 ERASEINFO(0x08000,1),
326 .mfr_id = MANUFACTURER_AMD,
327 .dev_id = AM29LV400BT,
328 .name = "AMD AM29LV400BT",
330 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
331 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
333 .DevSize = SIZE_512KiB,
334 .CmdSet = P_ID_AMD_STD,
337 ERASEINFO(0x10000,7),
338 ERASEINFO(0x08000,1),
339 ERASEINFO(0x02000,2),
343 .mfr_id = MANUFACTURER_AMD,
344 .dev_id = AM29LV800BB,
345 .name = "AMD AM29LV800BB",
347 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
348 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
350 .DevSize = SIZE_1MiB,
351 .CmdSet = P_ID_AMD_STD,
354 ERASEINFO(0x04000,1),
355 ERASEINFO(0x02000,2),
356 ERASEINFO(0x08000,1),
357 ERASEINFO(0x10000,15),
361 .mfr_id = MANUFACTURER_AMD,
362 .dev_id = AM29DL800BB,
363 .name = "AMD AM29DL800BB",
365 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
366 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
368 .DevSize = SIZE_1MiB,
369 .CmdSet = P_ID_AMD_STD,
372 ERASEINFO(0x04000,1),
373 ERASEINFO(0x08000,1),
374 ERASEINFO(0x02000,4),
375 ERASEINFO(0x08000,1),
376 ERASEINFO(0x04000,1),
377 ERASEINFO(0x10000,14)
380 .mfr_id = MANUFACTURER_AMD,
381 .dev_id = AM29DL800BT,
382 .name = "AMD AM29DL800BT",
384 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
385 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
387 .DevSize = SIZE_1MiB,
388 .CmdSet = P_ID_AMD_STD,
391 ERASEINFO(0x10000,14),
392 ERASEINFO(0x04000,1),
393 ERASEINFO(0x08000,1),
394 ERASEINFO(0x02000,4),
395 ERASEINFO(0x08000,1),
399 .mfr_id = MANUFACTURER_AMD,
400 .dev_id = AM29F800BB,
401 .name = "AMD AM29F800BB",
403 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
404 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
406 .DevSize = SIZE_1MiB,
407 .CmdSet = P_ID_AMD_STD,
410 ERASEINFO(0x04000,1),
411 ERASEINFO(0x02000,2),
412 ERASEINFO(0x08000,1),
413 ERASEINFO(0x10000,15),
416 .mfr_id = MANUFACTURER_AMD,
417 .dev_id = AM29LV800BT,
418 .name = "AMD AM29LV800BT",
420 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
421 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
423 .DevSize = SIZE_1MiB,
424 .CmdSet = P_ID_AMD_STD,
427 ERASEINFO(0x10000,15),
428 ERASEINFO(0x08000,1),
429 ERASEINFO(0x02000,2),
433 .mfr_id = MANUFACTURER_AMD,
434 .dev_id = AM29F800BT,
435 .name = "AMD AM29F800BT",
437 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
438 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
440 .DevSize = SIZE_1MiB,
441 .CmdSet = P_ID_AMD_STD,
444 ERASEINFO(0x10000,15),
445 ERASEINFO(0x08000,1),
446 ERASEINFO(0x02000,2),
450 .mfr_id = MANUFACTURER_AMD,
452 .name = "AMD AM29F017D",
454 [0] = MTD_UADDR_DONT_CARE /* x8 */
456 .DevSize = SIZE_2MiB,
457 .CmdSet = P_ID_AMD_STD,
460 ERASEINFO(0x10000,32),
463 .mfr_id = MANUFACTURER_AMD,
465 .name = "AMD AM29F016D",
467 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
469 .DevSize = SIZE_2MiB,
470 .CmdSet = P_ID_AMD_STD,
473 ERASEINFO(0x10000,32),
476 .mfr_id = MANUFACTURER_AMD,
478 .name = "AMD AM29F080",
480 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
482 .DevSize = SIZE_1MiB,
483 .CmdSet = P_ID_AMD_STD,
486 ERASEINFO(0x10000,16),
489 .mfr_id = MANUFACTURER_AMD,
491 .name = "AMD AM29F040",
493 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
495 .DevSize = SIZE_512KiB,
496 .CmdSet = P_ID_AMD_STD,
499 ERASEINFO(0x10000,8),
502 .mfr_id = MANUFACTURER_AMD,
503 .dev_id = AM29LV040B,
504 .name = "AMD AM29LV040B",
506 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
508 .DevSize = SIZE_512KiB,
509 .CmdSet = P_ID_AMD_STD,
512 ERASEINFO(0x10000,8),
515 .mfr_id = MANUFACTURER_AMD,
517 .name = "AMD AM29F002T",
518 .DevSize = SIZE_256KiB,
519 .NumEraseRegions = 4,
520 .regions = {ERASEINFO(0x10000,3),
521 ERASEINFO(0x08000,1),
522 ERASEINFO(0x02000,2),
526 .mfr_id = MANUFACTURER_ATMEL,
528 .name = "Atmel AT49BV512",
530 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
532 .DevSize = SIZE_64KiB,
533 .CmdSet = P_ID_AMD_STD,
539 .mfr_id = MANUFACTURER_ATMEL,
541 .name = "Atmel AT29LV512",
543 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
545 .DevSize = SIZE_64KiB,
546 .CmdSet = P_ID_AMD_STD,
553 .mfr_id = MANUFACTURER_ATMEL,
555 .name = "Atmel AT49BV16X",
557 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
558 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
560 .DevSize = SIZE_2MiB,
561 .CmdSet = P_ID_AMD_STD,
564 ERASEINFO(0x02000,8),
565 ERASEINFO(0x10000,31)
568 .mfr_id = MANUFACTURER_ATMEL,
569 .dev_id = AT49BV16XT,
570 .name = "Atmel AT49BV16XT",
572 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
573 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
575 .DevSize = SIZE_2MiB,
576 .CmdSet = P_ID_AMD_STD,
579 ERASEINFO(0x10000,31),
583 .mfr_id = MANUFACTURER_ATMEL,
585 .name = "Atmel AT49BV32X",
587 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
588 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
590 .DevSize = SIZE_4MiB,
591 .CmdSet = P_ID_AMD_STD,
594 ERASEINFO(0x02000,8),
595 ERASEINFO(0x10000,63)
598 .mfr_id = MANUFACTURER_ATMEL,
599 .dev_id = AT49BV32XT,
600 .name = "Atmel AT49BV32XT",
602 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
603 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
605 .DevSize = SIZE_4MiB,
606 .CmdSet = P_ID_AMD_STD,
609 ERASEINFO(0x10000,63),
613 .mfr_id = MANUFACTURER_FUJITSU,
614 .dev_id = MBM29F040C,
615 .name = "Fujitsu MBM29F040C",
617 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
619 .DevSize = SIZE_512KiB,
620 .CmdSet = P_ID_AMD_STD,
626 .mfr_id = MANUFACTURER_FUJITSU,
627 .dev_id = MBM29LV650UE,
628 .name = "Fujitsu MBM29LV650UE",
630 [0] = MTD_UADDR_DONT_CARE /* x16 */
632 .DevSize = SIZE_8MiB,
633 .CmdSet = P_ID_AMD_STD,
636 ERASEINFO(0x10000,128)
639 .mfr_id = MANUFACTURER_FUJITSU,
640 .dev_id = MBM29LV320TE,
641 .name = "Fujitsu MBM29LV320TE",
643 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
644 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
646 .DevSize = SIZE_4MiB,
647 .CmdSet = P_ID_AMD_STD,
650 ERASEINFO(0x10000,63),
654 .mfr_id = MANUFACTURER_FUJITSU,
655 .dev_id = MBM29LV320BE,
656 .name = "Fujitsu MBM29LV320BE",
658 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
659 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
661 .DevSize = SIZE_4MiB,
662 .CmdSet = P_ID_AMD_STD,
665 ERASEINFO(0x02000,8),
666 ERASEINFO(0x10000,63)
669 .mfr_id = MANUFACTURER_FUJITSU,
670 .dev_id = MBM29LV160TE,
671 .name = "Fujitsu MBM29LV160TE",
673 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
674 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
676 .DevSize = SIZE_2MiB,
677 .CmdSet = P_ID_AMD_STD,
680 ERASEINFO(0x10000,31),
681 ERASEINFO(0x08000,1),
682 ERASEINFO(0x02000,2),
686 .mfr_id = MANUFACTURER_FUJITSU,
687 .dev_id = MBM29LV160BE,
688 .name = "Fujitsu MBM29LV160BE",
690 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
691 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
693 .DevSize = SIZE_2MiB,
694 .CmdSet = P_ID_AMD_STD,
697 ERASEINFO(0x04000,1),
698 ERASEINFO(0x02000,2),
699 ERASEINFO(0x08000,1),
700 ERASEINFO(0x10000,31)
703 .mfr_id = MANUFACTURER_FUJITSU,
704 .dev_id = MBM29LV800BA,
705 .name = "Fujitsu MBM29LV800BA",
707 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
708 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
710 .DevSize = SIZE_1MiB,
711 .CmdSet = P_ID_AMD_STD,
714 ERASEINFO(0x04000,1),
715 ERASEINFO(0x02000,2),
716 ERASEINFO(0x08000,1),
717 ERASEINFO(0x10000,15)
720 .mfr_id = MANUFACTURER_FUJITSU,
721 .dev_id = MBM29LV800TA,
722 .name = "Fujitsu MBM29LV800TA",
724 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
725 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
727 .DevSize = SIZE_1MiB,
728 .CmdSet = P_ID_AMD_STD,
731 ERASEINFO(0x10000,15),
732 ERASEINFO(0x08000,1),
733 ERASEINFO(0x02000,2),
737 .mfr_id = MANUFACTURER_FUJITSU,
738 .dev_id = MBM29LV400BC,
739 .name = "Fujitsu MBM29LV400BC",
741 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
742 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
744 .DevSize = SIZE_512KiB,
745 .CmdSet = P_ID_AMD_STD,
748 ERASEINFO(0x04000,1),
749 ERASEINFO(0x02000,2),
750 ERASEINFO(0x08000,1),
754 .mfr_id = MANUFACTURER_FUJITSU,
755 .dev_id = MBM29LV400TC,
756 .name = "Fujitsu MBM29LV400TC",
758 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
759 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
761 .DevSize = SIZE_512KiB,
762 .CmdSet = P_ID_AMD_STD,
765 ERASEINFO(0x10000,7),
766 ERASEINFO(0x08000,1),
767 ERASEINFO(0x02000,2),
771 .mfr_id = MANUFACTURER_HYUNDAI,
773 .name = "Hyundai HY29F002T",
774 .DevSize = SIZE_256KiB,
775 .NumEraseRegions = 4,
776 .regions = {ERASEINFO(0x10000,3),
777 ERASEINFO(0x08000,1),
778 ERASEINFO(0x02000,2),
782 .mfr_id = MANUFACTURER_INTEL,
783 .dev_id = I28F004B3B,
784 .name = "Intel 28F004B3B",
786 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
788 .DevSize = SIZE_512KiB,
789 .CmdSet = P_ID_INTEL_STD,
792 ERASEINFO(0x02000, 8),
793 ERASEINFO(0x10000, 7),
796 .mfr_id = MANUFACTURER_INTEL,
797 .dev_id = I28F004B3T,
798 .name = "Intel 28F004B3T",
800 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
802 .DevSize = SIZE_512KiB,
803 .CmdSet = P_ID_INTEL_STD,
806 ERASEINFO(0x10000, 7),
807 ERASEINFO(0x02000, 8),
810 .mfr_id = MANUFACTURER_INTEL,
811 .dev_id = I28F400B3B,
812 .name = "Intel 28F400B3B",
814 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
815 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
817 .DevSize = SIZE_512KiB,
818 .CmdSet = P_ID_INTEL_STD,
821 ERASEINFO(0x02000, 8),
822 ERASEINFO(0x10000, 7),
825 .mfr_id = MANUFACTURER_INTEL,
826 .dev_id = I28F400B3T,
827 .name = "Intel 28F400B3T",
829 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
830 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
832 .DevSize = SIZE_512KiB,
833 .CmdSet = P_ID_INTEL_STD,
836 ERASEINFO(0x10000, 7),
837 ERASEINFO(0x02000, 8),
840 .mfr_id = MANUFACTURER_INTEL,
841 .dev_id = I28F008B3B,
842 .name = "Intel 28F008B3B",
844 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
846 .DevSize = SIZE_1MiB,
847 .CmdSet = P_ID_INTEL_STD,
850 ERASEINFO(0x02000, 8),
851 ERASEINFO(0x10000, 15),
854 .mfr_id = MANUFACTURER_INTEL,
855 .dev_id = I28F008B3T,
856 .name = "Intel 28F008B3T",
858 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
860 .DevSize = SIZE_1MiB,
861 .CmdSet = P_ID_INTEL_STD,
864 ERASEINFO(0x10000, 15),
865 ERASEINFO(0x02000, 8),
868 .mfr_id = MANUFACTURER_INTEL,
870 .name = "Intel 28F008S5",
872 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
874 .DevSize = SIZE_1MiB,
875 .CmdSet = P_ID_INTEL_EXT,
878 ERASEINFO(0x10000,16),
881 .mfr_id = MANUFACTURER_INTEL,
883 .name = "Intel 28F016S5",
885 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
887 .DevSize = SIZE_2MiB,
888 .CmdSet = P_ID_INTEL_EXT,
891 ERASEINFO(0x10000,32),
894 .mfr_id = MANUFACTURER_INTEL,
896 .name = "Intel 28F008SA",
898 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
900 .DevSize = SIZE_1MiB,
901 .CmdSet = P_ID_INTEL_STD,
904 ERASEINFO(0x10000, 16),
907 .mfr_id = MANUFACTURER_INTEL,
908 .dev_id = I28F800B3B,
909 .name = "Intel 28F800B3B",
911 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
913 .DevSize = SIZE_1MiB,
914 .CmdSet = P_ID_INTEL_STD,
917 ERASEINFO(0x02000, 8),
918 ERASEINFO(0x10000, 15),
921 .mfr_id = MANUFACTURER_INTEL,
922 .dev_id = I28F800B3T,
923 .name = "Intel 28F800B3T",
925 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
927 .DevSize = SIZE_1MiB,
928 .CmdSet = P_ID_INTEL_STD,
931 ERASEINFO(0x10000, 15),
932 ERASEINFO(0x02000, 8),
935 .mfr_id = MANUFACTURER_INTEL,
936 .dev_id = I28F016B3B,
937 .name = "Intel 28F016B3B",
939 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
941 .DevSize = SIZE_2MiB,
942 .CmdSet = P_ID_INTEL_STD,
945 ERASEINFO(0x02000, 8),
946 ERASEINFO(0x10000, 31),
949 .mfr_id = MANUFACTURER_INTEL,
951 .name = "Intel I28F016S3",
953 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
955 .DevSize = SIZE_2MiB,
956 .CmdSet = P_ID_INTEL_STD,
959 ERASEINFO(0x10000, 32),
962 .mfr_id = MANUFACTURER_INTEL,
963 .dev_id = I28F016B3T,
964 .name = "Intel 28F016B3T",
966 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
968 .DevSize = SIZE_2MiB,
969 .CmdSet = P_ID_INTEL_STD,
972 ERASEINFO(0x10000, 31),
973 ERASEINFO(0x02000, 8),
976 .mfr_id = MANUFACTURER_INTEL,
977 .dev_id = I28F160B3B,
978 .name = "Intel 28F160B3B",
980 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
982 .DevSize = SIZE_2MiB,
983 .CmdSet = P_ID_INTEL_STD,
986 ERASEINFO(0x02000, 8),
987 ERASEINFO(0x10000, 31),
990 .mfr_id = MANUFACTURER_INTEL,
991 .dev_id = I28F160B3T,
992 .name = "Intel 28F160B3T",
994 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
996 .DevSize = SIZE_2MiB,
997 .CmdSet = P_ID_INTEL_STD,
1000 ERASEINFO(0x10000, 31),
1001 ERASEINFO(0x02000, 8),
1004 .mfr_id = MANUFACTURER_INTEL,
1005 .dev_id = I28F320B3B,
1006 .name = "Intel 28F320B3B",
1008 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1010 .DevSize = SIZE_4MiB,
1011 .CmdSet = P_ID_INTEL_STD,
1012 .NumEraseRegions= 2,
1014 ERASEINFO(0x02000, 8),
1015 ERASEINFO(0x10000, 63),
1018 .mfr_id = MANUFACTURER_INTEL,
1019 .dev_id = I28F320B3T,
1020 .name = "Intel 28F320B3T",
1022 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1024 .DevSize = SIZE_4MiB,
1025 .CmdSet = P_ID_INTEL_STD,
1026 .NumEraseRegions= 2,
1028 ERASEINFO(0x10000, 63),
1029 ERASEINFO(0x02000, 8),
1032 .mfr_id = MANUFACTURER_INTEL,
1033 .dev_id = I28F640B3B,
1034 .name = "Intel 28F640B3B",
1036 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1038 .DevSize = SIZE_8MiB,
1039 .CmdSet = P_ID_INTEL_STD,
1040 .NumEraseRegions= 2,
1042 ERASEINFO(0x02000, 8),
1043 ERASEINFO(0x10000, 127),
1046 .mfr_id = MANUFACTURER_INTEL,
1047 .dev_id = I28F640B3T,
1048 .name = "Intel 28F640B3T",
1050 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1052 .DevSize = SIZE_8MiB,
1053 .CmdSet = P_ID_INTEL_STD,
1054 .NumEraseRegions= 2,
1056 ERASEINFO(0x10000, 127),
1057 ERASEINFO(0x02000, 8),
1060 .mfr_id = MANUFACTURER_INTEL,
1062 .name = "Intel 82802AB",
1064 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1066 .DevSize = SIZE_512KiB,
1067 .CmdSet = P_ID_INTEL_EXT,
1068 .NumEraseRegions= 1,
1070 ERASEINFO(0x10000,8),
1073 .mfr_id = MANUFACTURER_INTEL,
1075 .name = "Intel 82802AC",
1077 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1079 .DevSize = SIZE_1MiB,
1080 .CmdSet = P_ID_INTEL_EXT,
1081 .NumEraseRegions= 1,
1083 ERASEINFO(0x10000,16),
1086 .mfr_id = MANUFACTURER_MACRONIX,
1087 .dev_id = MX29LV160T,
1088 .name = "MXIC MX29LV160T",
1090 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1091 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1093 .DevSize = SIZE_2MiB,
1094 .CmdSet = P_ID_AMD_STD,
1095 .NumEraseRegions= 4,
1097 ERASEINFO(0x10000,31),
1098 ERASEINFO(0x08000,1),
1099 ERASEINFO(0x02000,2),
1100 ERASEINFO(0x04000,1)
1103 .mfr_id = MANUFACTURER_MACRONIX,
1104 .dev_id = MX29LV160B,
1105 .name = "MXIC MX29LV160B",
1107 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1108 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1110 .DevSize = SIZE_2MiB,
1111 .CmdSet = P_ID_AMD_STD,
1112 .NumEraseRegions= 4,
1114 ERASEINFO(0x04000,1),
1115 ERASEINFO(0x02000,2),
1116 ERASEINFO(0x08000,1),
1117 ERASEINFO(0x10000,31)
1120 .mfr_id = MANUFACTURER_MACRONIX,
1122 .name = "Macronix MX29F016",
1124 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1126 .DevSize = SIZE_2MiB,
1127 .CmdSet = P_ID_AMD_STD,
1128 .NumEraseRegions= 1,
1130 ERASEINFO(0x10000,32),
1133 .mfr_id = MANUFACTURER_MACRONIX,
1134 .dev_id = MX29F004T,
1135 .name = "Macronix MX29F004T",
1137 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1139 .DevSize = SIZE_512KiB,
1140 .CmdSet = P_ID_AMD_STD,
1141 .NumEraseRegions= 4,
1143 ERASEINFO(0x10000,7),
1144 ERASEINFO(0x08000,1),
1145 ERASEINFO(0x02000,2),
1146 ERASEINFO(0x04000,1),
1149 .mfr_id = MANUFACTURER_MACRONIX,
1150 .dev_id = MX29F004B,
1151 .name = "Macronix MX29F004B",
1153 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1155 .DevSize = SIZE_512KiB,
1156 .CmdSet = P_ID_AMD_STD,
1157 .NumEraseRegions= 4,
1159 ERASEINFO(0x04000,1),
1160 ERASEINFO(0x02000,2),
1161 ERASEINFO(0x08000,1),
1162 ERASEINFO(0x10000,7),
1165 .mfr_id = MANUFACTURER_MACRONIX,
1166 .dev_id = MX29F002T,
1167 .name = "Macronix MX29F002T",
1168 .DevSize = SIZE_256KiB,
1169 .NumEraseRegions = 4,
1170 .regions = {ERASEINFO(0x10000,3),
1171 ERASEINFO(0x08000,1),
1172 ERASEINFO(0x02000,2),
1173 ERASEINFO(0x04000,1)
1176 .mfr_id = MANUFACTURER_PMC,
1177 .dev_id = PM49FL002,
1178 .name = "PMC Pm49FL002",
1180 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1182 .DevSize = SIZE_256KiB,
1183 .CmdSet = P_ID_AMD_STD,
1184 .NumEraseRegions= 1,
1186 ERASEINFO( 0x01000, 64 )
1189 .mfr_id = MANUFACTURER_PMC,
1190 .dev_id = PM49FL004,
1191 .name = "PMC Pm49FL004",
1193 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1195 .DevSize = SIZE_512KiB,
1196 .CmdSet = P_ID_AMD_STD,
1197 .NumEraseRegions= 1,
1199 ERASEINFO( 0x01000, 128 )
1202 .mfr_id = MANUFACTURER_PMC,
1203 .dev_id = PM49FL008,
1204 .name = "PMC Pm49FL008",
1206 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1208 .DevSize = SIZE_1MiB,
1209 .CmdSet = P_ID_AMD_STD,
1210 .NumEraseRegions= 1,
1212 ERASEINFO( 0x01000, 256 )
1215 .mfr_id = MANUFACTURER_SST,
1216 .dev_id = SST39LF512,
1217 .name = "SST 39LF512",
1219 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1221 .DevSize = SIZE_64KiB,
1222 .CmdSet = P_ID_AMD_STD,
1223 .NumEraseRegions= 1,
1225 ERASEINFO(0x01000,16),
1228 .mfr_id = MANUFACTURER_SST,
1229 .dev_id = SST39LF010,
1230 .name = "SST 39LF010",
1232 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1234 .DevSize = SIZE_128KiB,
1235 .CmdSet = P_ID_AMD_STD,
1236 .NumEraseRegions= 1,
1238 ERASEINFO(0x01000,32),
1241 .mfr_id = MANUFACTURER_SST,
1242 .dev_id = SST29EE020,
1243 .name = "SST 29EE020",
1245 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1247 .DevSize = SIZE_256KiB,
1248 .CmdSet = P_ID_SST_PAGE,
1249 .NumEraseRegions= 1,
1250 .regions = {ERASEINFO(0x01000,64),
1253 .mfr_id = MANUFACTURER_SST,
1254 .dev_id = SST29LE020,
1255 .name = "SST 29LE020",
1257 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1259 .DevSize = SIZE_256KiB,
1260 .CmdSet = P_ID_SST_PAGE,
1261 .NumEraseRegions= 1,
1262 .regions = {ERASEINFO(0x01000,64),
1265 .mfr_id = MANUFACTURER_SST,
1266 .dev_id = SST39LF020,
1267 .name = "SST 39LF020",
1269 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1271 .DevSize = SIZE_256KiB,
1272 .CmdSet = P_ID_AMD_STD,
1273 .NumEraseRegions= 1,
1275 ERASEINFO(0x01000,64),
1278 .mfr_id = MANUFACTURER_SST,
1279 .dev_id = SST39LF040,
1280 .name = "SST 39LF040",
1282 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1284 .DevSize = SIZE_512KiB,
1285 .CmdSet = P_ID_AMD_STD,
1286 .NumEraseRegions= 1,
1288 ERASEINFO(0x01000,128),
1291 .mfr_id = MANUFACTURER_SST,
1292 .dev_id = SST39SF010A,
1293 .name = "SST 39SF010A",
1295 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1297 .DevSize = SIZE_128KiB,
1298 .CmdSet = P_ID_AMD_STD,
1299 .NumEraseRegions= 1,
1301 ERASEINFO(0x01000,32),
1304 .mfr_id = MANUFACTURER_SST,
1305 .dev_id = SST39SF020A,
1306 .name = "SST 39SF020A",
1308 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1310 .DevSize = SIZE_256KiB,
1311 .CmdSet = P_ID_AMD_STD,
1312 .NumEraseRegions= 1,
1314 ERASEINFO(0x01000,64),
1317 .mfr_id = MANUFACTURER_SST,
1318 .dev_id = SST49LF004B,
1319 .name = "SST 49LF004B",
1321 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1323 .DevSize = SIZE_512KiB,
1324 .CmdSet = P_ID_AMD_STD,
1325 .NumEraseRegions= 1,
1327 ERASEINFO(0x01000,128),
1330 .mfr_id = MANUFACTURER_SST,
1331 .dev_id = SST49LF008A,
1332 .name = "SST 49LF008A",
1334 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1336 .DevSize = SIZE_1MiB,
1337 .CmdSet = P_ID_AMD_STD,
1338 .NumEraseRegions= 1,
1340 ERASEINFO(0x01000,256),
1343 .mfr_id = MANUFACTURER_SST,
1344 .dev_id = SST49LF030A,
1345 .name = "SST 49LF030A",
1347 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1349 .DevSize = SIZE_512KiB,
1350 .CmdSet = P_ID_AMD_STD,
1351 .NumEraseRegions= 1,
1353 ERASEINFO(0x01000,96),
1356 .mfr_id = MANUFACTURER_SST,
1357 .dev_id = SST49LF040A,
1358 .name = "SST 49LF040A",
1360 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1362 .DevSize = SIZE_512KiB,
1363 .CmdSet = P_ID_AMD_STD,
1364 .NumEraseRegions= 1,
1366 ERASEINFO(0x01000,128),
1369 .mfr_id = MANUFACTURER_SST,
1370 .dev_id = SST49LF080A,
1371 .name = "SST 49LF080A",
1373 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1375 .DevSize = SIZE_1MiB,
1376 .CmdSet = P_ID_AMD_STD,
1377 .NumEraseRegions= 1,
1379 ERASEINFO(0x01000,256),
1382 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1383 .dev_id = M29W800DT,
1384 .name = "ST M29W800DT",
1386 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
1387 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
1389 .DevSize = SIZE_1MiB,
1390 .CmdSet = P_ID_AMD_STD,
1391 .NumEraseRegions= 4,
1393 ERASEINFO(0x10000,15),
1394 ERASEINFO(0x08000,1),
1395 ERASEINFO(0x02000,2),
1396 ERASEINFO(0x04000,1)
1399 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1400 .dev_id = M29W800DB,
1401 .name = "ST M29W800DB",
1403 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
1404 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
1406 .DevSize = SIZE_1MiB,
1407 .CmdSet = P_ID_AMD_STD,
1408 .NumEraseRegions= 4,
1410 ERASEINFO(0x04000,1),
1411 ERASEINFO(0x02000,2),
1412 ERASEINFO(0x08000,1),
1413 ERASEINFO(0x10000,15)
1416 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1417 .dev_id = M29W160DT,
1418 .name = "ST M29W160DT",
1420 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
1421 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1423 .DevSize = SIZE_2MiB,
1424 .CmdSet = P_ID_AMD_STD,
1425 .NumEraseRegions= 4,
1427 ERASEINFO(0x10000,31),
1428 ERASEINFO(0x08000,1),
1429 ERASEINFO(0x02000,2),
1430 ERASEINFO(0x04000,1)
1433 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1434 .dev_id = M29W160DB,
1435 .name = "ST M29W160DB",
1437 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
1438 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1440 .DevSize = SIZE_2MiB,
1441 .CmdSet = P_ID_AMD_STD,
1442 .NumEraseRegions= 4,
1444 ERASEINFO(0x04000,1),
1445 ERASEINFO(0x02000,2),
1446 ERASEINFO(0x08000,1),
1447 ERASEINFO(0x10000,31)
1450 .mfr_id = MANUFACTURER_ST,
1452 .name = "ST M29W040B",
1454 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1456 .DevSize = SIZE_512KiB,
1457 .CmdSet = P_ID_AMD_STD,
1458 .NumEraseRegions= 1,
1460 ERASEINFO(0x10000,8),
1463 .mfr_id = MANUFACTURER_ST,
1465 .name = "ST M50FW040",
1467 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1469 .DevSize = SIZE_512KiB,
1470 .CmdSet = P_ID_INTEL_EXT,
1471 .NumEraseRegions= 1,
1473 ERASEINFO(0x10000,8),
1476 .mfr_id = MANUFACTURER_ST,
1478 .name = "ST M50FW080",
1480 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1482 .DevSize = SIZE_1MiB,
1483 .CmdSet = P_ID_INTEL_EXT,
1484 .NumEraseRegions= 1,
1486 ERASEINFO(0x10000,16),
1489 .mfr_id = MANUFACTURER_ST,
1491 .name = "ST M50FW016",
1493 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1495 .DevSize = SIZE_2MiB,
1496 .CmdSet = P_ID_INTEL_EXT,
1497 .NumEraseRegions= 1,
1499 ERASEINFO(0x10000,32),
1502 .mfr_id = MANUFACTURER_TOSHIBA,
1503 .dev_id = TC58FVT160,
1504 .name = "Toshiba TC58FVT160",
1506 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1507 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1509 .DevSize = SIZE_2MiB,
1510 .CmdSet = P_ID_AMD_STD,
1511 .NumEraseRegions= 4,
1513 ERASEINFO(0x10000,31),
1514 ERASEINFO(0x08000,1),
1515 ERASEINFO(0x02000,2),
1516 ERASEINFO(0x04000,1)
1519 .mfr_id = MANUFACTURER_TOSHIBA,
1520 .dev_id = TC58FVB160,
1521 .name = "Toshiba TC58FVB160",
1523 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1524 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1526 .DevSize = SIZE_2MiB,
1527 .CmdSet = P_ID_AMD_STD,
1528 .NumEraseRegions= 4,
1530 ERASEINFO(0x04000,1),
1531 ERASEINFO(0x02000,2),
1532 ERASEINFO(0x08000,1),
1533 ERASEINFO(0x10000,31)
1536 .mfr_id = MANUFACTURER_TOSHIBA,
1537 .dev_id = TC58FVB321,
1538 .name = "Toshiba TC58FVB321",
1540 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1541 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1543 .DevSize = SIZE_4MiB,
1544 .CmdSet = P_ID_AMD_STD,
1545 .NumEraseRegions= 2,
1547 ERASEINFO(0x02000,8),
1548 ERASEINFO(0x10000,63)
1551 .mfr_id = MANUFACTURER_TOSHIBA,
1552 .dev_id = TC58FVT321,
1553 .name = "Toshiba TC58FVT321",
1555 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1556 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1558 .DevSize = SIZE_4MiB,
1559 .CmdSet = P_ID_AMD_STD,
1560 .NumEraseRegions= 2,
1562 ERASEINFO(0x10000,63),
1563 ERASEINFO(0x02000,8)
1566 .mfr_id = MANUFACTURER_TOSHIBA,
1567 .dev_id = TC58FVB641,
1568 .name = "Toshiba TC58FVB641",
1570 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1571 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1573 .DevSize = SIZE_8MiB,
1574 .CmdSet = P_ID_AMD_STD,
1575 .NumEraseRegions= 2,
1577 ERASEINFO(0x02000,8),
1578 ERASEINFO(0x10000,127)
1581 .mfr_id = MANUFACTURER_TOSHIBA,
1582 .dev_id = TC58FVT641,
1583 .name = "Toshiba TC58FVT641",
1585 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1586 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1588 .DevSize = SIZE_8MiB,
1589 .CmdSet = P_ID_AMD_STD,
1590 .NumEraseRegions= 2,
1592 ERASEINFO(0x10000,127),
1593 ERASEINFO(0x02000,8)
1596 .mfr_id = MANUFACTURER_WINBOND,
1598 .name = "Winbond W49V002A",
1600 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1602 .DevSize = SIZE_256KiB,
1603 .CmdSet = P_ID_AMD_STD,
1604 .NumEraseRegions= 4,
1606 ERASEINFO(0x10000, 3),
1607 ERASEINFO(0x08000, 1),
1608 ERASEINFO(0x02000, 2),
1609 ERASEINFO(0x04000, 1),
1615 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index);
1617 static int jedec_probe_chip(struct map_info *map, __u32 base,
1618 unsigned long *chip_map, struct cfi_private *cfi);
1620 struct mtd_info *jedec_probe(struct map_info *map);
1622 static inline u32 jedec_read_mfr(struct map_info *map, __u32 base,
1623 struct cfi_private *cfi)
1627 mask = (1 << (cfi->device_type * 8)) -1;
1628 result = map_read(map, base);
1629 return result.x[0] & mask;
1632 static inline u32 jedec_read_id(struct map_info *map, __u32 base,
1633 struct cfi_private *cfi)
1638 osf = cfi->interleave *cfi->device_type;
1639 mask = (1 << (cfi->device_type * 8)) -1;
1640 result = map_read(map, base + osf);
1641 return result.x[0] & mask;
1644 static inline void jedec_reset(u32 base, struct map_info *map,
1645 struct cfi_private *cfi)
1649 /* after checking the datasheets for SST, MACRONIX and ATMEL
1650 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset
1651 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at
1652 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
1653 * as they will ignore the writes and dont care what address
1654 * the F0 is written to */
1655 if(cfi->addr_unlock1) {
1656 /*printk("reset unlock called %x %x \n",cfi->addr_unlock1,cfi->addr_unlock2);*/
1657 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1658 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1661 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1662 /* Some misdesigned intel chips do not respond for 0xF0 for a reset,
1663 * so ensure we're in read mode. Send both the Intel and the AMD command
1664 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so
1665 * this should be safe.
1667 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
1668 /* FIXME - should have reset delay before continuing */
1672 static inline __u8 finfo_uaddr(const struct amd_flash_info *finfo, int device_type)
1675 __u8 uaddr = MTD_UADDR_NOT_SUPPORTED;
1677 switch ( device_type ) {
1678 case CFI_DEVICETYPE_X8: uaddr_idx = 0; break;
1679 case CFI_DEVICETYPE_X16: uaddr_idx = 1; break;
1680 case CFI_DEVICETYPE_X32: uaddr_idx = 2; break;
1682 printk(KERN_NOTICE "MTD: %s(): unknown device_type %d\n",
1683 __func__, device_type);
1687 uaddr = finfo->uaddr[uaddr_idx];
1689 if (uaddr != MTD_UADDR_NOT_SUPPORTED ) {
1690 /* ASSERT("The unlock addresses for non-8-bit mode
1691 are bollocks. We don't really need an array."); */
1692 uaddr = finfo->uaddr[0];
1700 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
1702 int i,num_erase_regions;
1706 printk("Found: %s\n",jedec_table[index].name);
1708 num_erase_regions = jedec_table[index].NumEraseRegions;
1710 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
1712 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name);
1716 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident));
1718 p_cfi->cfiq->P_ID = jedec_table[index].CmdSet;
1719 p_cfi->cfiq->NumEraseRegions = jedec_table[index].NumEraseRegions;
1720 p_cfi->cfiq->DevSize = jedec_table[index].DevSize;
1721 p_cfi->cfi_mode = CFI_MODE_JEDEC;
1723 for (i=0; i<num_erase_regions; i++){
1724 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i];
1726 p_cfi->cmdset_priv = NULL;
1728 /* This may be redundant for some cases, but it doesn't hurt */
1729 p_cfi->mfr = jedec_table[index].mfr_id;
1730 p_cfi->id = jedec_table[index].dev_id;
1732 uaddr = finfo_uaddr(&jedec_table[index], p_cfi->device_type);
1733 if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
1734 kfree( p_cfi->cfiq );
1738 /* Mask out address bits which are smaller than the device type */
1739 mask = ~(p_cfi->device_type-1);
1740 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 & mask;
1741 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 & mask;
1748 * There is a BIG problem properly ID'ing the JEDEC devic and guaranteeing
1749 * the mapped address, unlock addresses, and proper chip ID. This function
1750 * attempts to minimize errors. It is doubtfull that this probe will ever
1751 * be perfect - consequently there should be some module parameters that
1752 * could be manually specified to force the chip info.
1754 static inline int jedec_match( __u32 base,
1755 struct map_info *map,
1756 struct cfi_private *cfi,
1757 const struct amd_flash_info *finfo )
1759 int rc = 0; /* failure until all tests pass */
1765 * The IDs must match. For X16 and X32 devices operating in
1766 * a lower width ( X8 or X16 ), the device ID's are usually just
1767 * the lower byte(s) of the larger device ID for wider mode. If
1768 * a part is found that doesn't fit this assumption (device id for
1769 * smaller width mode is completely unrealated to full-width mode)
1770 * then the jedec_table[] will have to be augmented with the IDs
1771 * for different widths.
1773 switch (cfi->device_type) {
1774 case CFI_DEVICETYPE_X8:
1775 mfr = (__u8)finfo->mfr_id;
1776 id = (__u8)finfo->dev_id;
1778 case CFI_DEVICETYPE_X16:
1779 mfr = (__u16)finfo->mfr_id;
1780 id = (__u16)finfo->dev_id;
1782 case CFI_DEVICETYPE_X32:
1783 mfr = (__u16)finfo->mfr_id;
1784 id = (__u32)finfo->dev_id;
1788 "MTD %s(): Unsupported device type %d\n",
1789 __func__, cfi->device_type);
1792 if ( cfi->mfr != mfr || cfi->id != id ) {
1796 /* the part size must fit in the memory window */
1797 DEBUG( MTD_DEBUG_LEVEL3,
1798 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
1799 __func__, base, 1 << finfo->DevSize, base + (1 << finfo->DevSize) );
1800 if ( base + cfi->interleave * ( 1 << finfo->DevSize ) > map->size ) {
1801 DEBUG( MTD_DEBUG_LEVEL3,
1802 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
1803 __func__, finfo->mfr_id, finfo->dev_id,
1804 1 << finfo->DevSize );
1808 uaddr = finfo_uaddr(finfo, cfi->device_type);
1809 if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
1813 mask = ~(cfi->device_type-1);
1815 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
1816 __func__, cfi->addr_unlock1, cfi->addr_unlock2 );
1817 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
1818 && ( (unlock_addrs[uaddr].addr1 & mask) != cfi->addr_unlock1 ||
1819 (unlock_addrs[uaddr].addr2 & mask) != cfi->addr_unlock2 ) ) {
1820 DEBUG( MTD_DEBUG_LEVEL3,
1821 "MTD %s(): 0x%.4lx 0x%.4lx did not match\n",
1823 unlock_addrs[uaddr].addr1 & mask,
1824 unlock_addrs[uaddr].addr2 & mask);
1829 * Make sure the ID's dissappear when the device is taken out of
1830 * ID mode. The only time this should fail when it should succeed
1831 * is when the ID's are written as data to the same
1832 * addresses. For this rare and unfortunate case the chip
1833 * cannot be probed correctly.
1834 * FIXME - write a driver that takes all of the chip info as
1835 * module parameters, doesn't probe but forces a load.
1837 DEBUG( MTD_DEBUG_LEVEL3,
1838 "MTD %s(): check ID's disappear when not in ID mode\n",
1840 jedec_reset( base, map, cfi );
1841 mfr = jedec_read_mfr( map, base, cfi );
1842 id = jedec_read_id( map, base, cfi );
1843 if ( mfr == cfi->mfr && id == cfi->id ) {
1844 DEBUG( MTD_DEBUG_LEVEL3,
1845 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n"
1846 "You might need to manually specify JEDEC parameters.\n",
1847 __func__, cfi->mfr, cfi->id );
1851 /* all tests passed - mark as success */
1855 * Put the device back in ID mode - only need to do this if we
1856 * were truly frobbing a real device.
1858 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ );
1859 if(cfi->addr_unlock1) {
1860 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1861 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1863 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1864 /* FIXME - should have a delay before continuing */
1871 static int jedec_probe_chip(struct map_info *map, __u32 base,
1872 unsigned long *chip_map, struct cfi_private *cfi)
1875 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
1878 if (!cfi->numchips) {
1879 unsigned long mask = ~(cfi->device_type-1);
1883 if (MTD_UADDR_UNNECESSARY == uaddr_idx)
1886 /* Mask out address bits which are smaller than the device type */
1887 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 & mask;
1888 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 & mask;
1891 /* Make certain we aren't probing past the end of map */
1892 if (base >= map->size) {
1894 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n",
1895 base, map->size -1);
1899 if ((base + cfi->addr_unlock1) >= map->size) {
1901 "Probe at addr_unlock1(0x%08x + 0x%08x) past the end of the map(0x%08lx)\n",
1902 base, cfi->addr_unlock1, map->size -1);
1906 if ((base + cfi->addr_unlock2) >= map->size) {
1908 "Probe at addr_unlock2(0x%08x + 0x%08x) past the end of the map(0x%08lx)\n",
1909 base, cfi->addr_unlock2, map->size -1);
1915 jedec_reset(base, map, cfi);
1917 /* Autoselect Mode */
1918 if(cfi->addr_unlock1) {
1919 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1920 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1922 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1923 /* FIXME - should have a delay before continuing */
1925 if (!cfi->numchips) {
1926 /* This is the first time we're called. Set up the CFI
1927 stuff accordingly and return */
1929 cfi->mfr = jedec_read_mfr(map, base, cfi);
1930 cfi->id = jedec_read_id(map, base, cfi);
1931 DEBUG(MTD_DEBUG_LEVEL3,
1932 "Search for id:(%02x %02x) interleave(%d) type(%d)\n",
1933 cfi->mfr, cfi->id, cfi->interleave, cfi->device_type);
1934 for (i=0; i<sizeof(jedec_table)/sizeof(jedec_table[0]); i++) {
1935 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) {
1936 DEBUG( MTD_DEBUG_LEVEL3,
1937 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n",
1938 __func__, cfi->mfr, cfi->id,
1939 cfi->addr_unlock1, cfi->addr_unlock2 );
1940 if (!cfi_jedec_setup(cfi, i))
1950 /* Make sure it is a chip of the same manufacturer and id */
1951 mfr = jedec_read_mfr(map, base, cfi);
1952 id = jedec_read_id(map, base, cfi);
1954 if ((mfr != cfi->mfr) || (id != cfi->id)) {
1955 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n",
1956 map->name, mfr, id, base);
1957 jedec_reset(base, map, cfi);
1962 /* Check each previous chip locations to see if it's an alias */
1963 for (i=0; i < (base >> cfi->chipshift); i++) {
1964 unsigned long start;
1965 if(!test_bit(i, chip_map)) {
1966 continue; /* Skip location; no valid chip at this address */
1968 start = i << cfi->chipshift;
1969 if (jedec_read_mfr(map, start, cfi) == cfi->mfr &&
1970 jedec_read_id(map, start, cfi) == cfi->id) {
1971 /* Eep. This chip also looks like it's in autoselect mode.
1972 Is it an alias for the new one? */
1973 jedec_reset(start, map, cfi);
1975 /* If the device IDs go away, it's an alias */
1976 if (jedec_read_mfr(map, base, cfi) != cfi->mfr ||
1977 jedec_read_id(map, base, cfi) != cfi->id) {
1978 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
1979 map->name, base, start);
1983 /* Yes, it's actually got the device IDs as data. Most
1984 * unfortunate. Stick the new chip in read mode
1985 * too and if it's the same, assume it's an alias. */
1986 /* FIXME: Use other modes to do a proper check */
1987 jedec_reset(base, map, cfi);
1988 if (jedec_read_mfr(map, base, cfi) == cfi->mfr &&
1989 jedec_read_id(map, base, cfi) == cfi->id) {
1990 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
1991 map->name, base, start);
1997 /* OK, if we got to here, then none of the previous chips appear to
1998 be aliases for the current one. */
1999 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
2003 /* Put it back into Read Mode */
2004 jedec_reset(base, map, cfi);
2006 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
2007 map->name, cfi->interleave, cfi->device_type*8, base,
2013 static struct chip_probe jedec_chip_probe = {
2015 .probe_chip = jedec_probe_chip
2018 struct mtd_info *jedec_probe(struct map_info *map)
2021 * Just use the generic probe stuff to call our CFI-specific
2022 * chip_probe routine in all the possible permutations, etc.
2024 return mtd_do_chip_probe(map, &jedec_chip_probe);
2027 static struct mtd_chip_driver jedec_chipdrv = {
2028 .probe = jedec_probe,
2029 .name = "jedec_probe",
2030 .module = THIS_MODULE
2033 int __init jedec_probe_init(void)
2035 register_mtd_chip_driver(&jedec_chipdrv);
2039 static void __exit jedec_probe_exit(void)
2041 unregister_mtd_chip_driver(&jedec_chipdrv);
2044 module_init(jedec_probe_init);
2045 module_exit(jedec_probe_exit);
2047 MODULE_LICENSE("GPL");
2048 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al.");
2049 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips");