2 * drivers/mtd/nand/au1550nd.c
4 * Copyright (C) 2004 Embedded Edge, LLC
6 * $Id: au1550nd.c,v 1.5 2004/05/17 07:19:35 ppopov Exp $
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/partitions.h>
21 #include <asm/au1000.h>
22 #ifdef CONFIG_MIPS_PB1550
23 #include <asm/pb1550.h>
25 #ifdef CONFIG_MIPS_DB1550
26 #include <asm/db1x00.h>
31 * MTD structure for NAND controller
33 static struct mtd_info *au1550_mtd = NULL;
34 static volatile u32 p_nand;
35 static int nand_width = 1; /* default, only x8 supported for now */
37 /* Internal buffers. Page buffer and oob buffer for one block*/
38 static u_char data_buf[512 + 16];
39 static u_char oob_buf[16 * 32];
42 * Define partitions for flash device
44 const static struct mtd_partition partition_info[] = {
45 #ifdef CONFIG_MIPS_PB1550
46 #define NUM_PARTITIONS 2
48 .name = "Pb1550 NAND FS 0",
53 .name = "Pb1550 NAND FS 1",
54 .offset = MTDPART_OFS_APPEND,
55 .size = MTDPART_SIZ_FULL
58 #ifdef CONFIG_MIPS_DB1550
59 #define NUM_PARTITIONS 2
61 .name = "Db1550 NAND FS 0",
66 .name = "Db1550 NAND FS 1",
67 .offset = MTDPART_OFS_APPEND,
68 .size = MTDPART_SIZ_FULL
73 static inline void write_cmd_reg(u8 cmd)
76 *((volatile u8 *)(p_nand + MEM_STNAND_CMD)) = cmd;
78 *((volatile u16 *)(p_nand + MEM_STNAND_CMD)) = cmd;
82 static inline void write_addr_reg(u8 addr)
85 *((volatile u8 *)(p_nand + MEM_STNAND_ADDR)) = addr;
87 *((volatile u16 *)(p_nand + MEM_STNAND_ADDR)) = addr;
91 static inline void write_data_reg(u8 data)
94 *((volatile u8 *)(p_nand + MEM_STNAND_DATA)) = data;
96 *((volatile u16 *)(p_nand + MEM_STNAND_DATA)) = data;
100 static inline u32 read_data_reg(void)
104 data = *((volatile u8 *)(p_nand + MEM_STNAND_DATA));
108 data = *((volatile u16 *)(p_nand + MEM_STNAND_DATA));
114 void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
118 int au1550_device_ready(struct mtd_info *mtd)
121 ready = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
125 static u_char au1550_nand_read_byte(struct mtd_info *mtd)
128 ret = read_data_reg();
132 static void au1550_nand_write_byte(struct mtd_info *mtd, u_char byte)
134 write_data_reg((u8)byte);
138 au1550_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
142 for (i=0; i<len; i++)
143 write_data_reg(buf[i]);
147 au1550_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
151 for (i=0; i<len; i++)
152 buf[i] = (u_char)read_data_reg();
156 au1550_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
160 for (i=0; i<len; i++)
161 if (buf[i] != (u_char)read_data_reg())
167 static void au1550_nand_select_chip(struct mtd_info *mtd, int chip)
171 /* deassert chip enable */
172 au_writel(au_readl(MEM_STNDCTL) & ~0x20 , MEM_STNDCTL);
175 /* assert (force assert) chip enable */
176 au_writel(au_readl(MEM_STNDCTL) | 0x20 , MEM_STNDCTL);
184 static void au1550_nand_command (struct mtd_info *mtd, unsigned command,
185 int column, int page_addr)
187 register struct nand_chip *this = mtd->priv;
190 * Write out the command to the device.
192 if (command == NAND_CMD_SEQIN) {
195 if (column >= mtd->oobblock) {
197 column -= mtd->oobblock;
198 readcmd = NAND_CMD_READOOB;
199 } else if (column < 256) {
200 /* First 256 bytes --> READ0 */
201 readcmd = NAND_CMD_READ0;
204 readcmd = NAND_CMD_READ1;
206 write_cmd_reg(readcmd);
208 write_cmd_reg(command);
210 if (column != -1 || page_addr != -1) {
212 /* Serially input address */
214 write_addr_reg(column);
215 if (page_addr != -1) {
216 write_addr_reg((unsigned char) (page_addr & 0xff));
217 write_addr_reg(((page_addr >> 8) & 0xff));
218 /* One more address cycle for higher density devices */
219 if (mtd->size & 0x0c000000)
220 write_addr_reg((unsigned char) ((page_addr >> 16) & 0x0f));
226 case NAND_CMD_PAGEPROG:
227 case NAND_CMD_ERASE1:
228 case NAND_CMD_ERASE2:
230 case NAND_CMD_STATUS:
236 udelay(this->chip_delay);
237 write_cmd_reg(NAND_CMD_STATUS);
238 while ( !(read_data_reg() & 0x40));
241 /* This applies to read commands */
243 udelay (this->chip_delay);
246 /* wait until command is processed */
247 while (!this->dev_ready(mtd));
252 * Main initialization routine
254 int __init au1550_init (void)
256 struct nand_chip *this;
257 u16 boot_swapboot = 0; /* default value */
260 /* Allocate memory for MTD device structure and private data */
261 au1550_mtd = kmalloc (sizeof(struct mtd_info) +
262 sizeof (struct nand_chip), GFP_KERNEL);
264 printk ("Unable to allocate NAND MTD dev structure.\n");
268 /* Get pointer to private data */
269 this = (struct nand_chip *) (&au1550_mtd[1]);
271 /* Initialize structures */
272 memset((char *) au1550_mtd, 0, sizeof(struct mtd_info));
273 memset((char *) this, 0, sizeof(struct nand_chip));
275 /* Link the private data with the MTD structure */
276 au1550_mtd->priv = this;
278 /* disable interrupts */
279 au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL);
281 /* disable NAND boot */
282 au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL);
284 #ifdef CONFIG_MIPS_PB1550
285 /* set gpio206 high */
286 au_writel(au_readl(GPIO2_DIR) & ~(1<<6), GPIO2_DIR);
288 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) |
289 ((bcsr->status >> 6) & 0x1);
290 switch (boot_swapboot) {
298 printk("Pb1550 NAND: 16-bit NAND not supported by MTD\n");
309 printk("Pb1550 NAND: bad boot:swap\n");
314 /* Configure RCE1 - should be done by YAMON */
315 au_writel(0x5 | (nand_width << 22), MEM_STCFG1);
316 au_writel(NAND_TIMING, MEM_STTIME1);
317 mem_time = au_readl(MEM_STTIME1);
320 /* setup and enable chip select */
321 /* we really need to decode offsets only up till 0x20 */
322 au_writel((1<<28) | (NAND_PHYS_ADDR>>4) |
323 (((NAND_PHYS_ADDR + 0x1000)-1) & (0x3fff<<18)>>18),
328 #ifdef CONFIG_MIPS_DB1550
329 /* Configure RCE1 - should be done by YAMON */
330 au_writel(0x00400005, MEM_STCFG1);
331 au_writel(0x00007774, MEM_STTIME1);
332 au_writel(0x12000FFF, MEM_STADDR1);
335 p_nand = (volatile struct nand_regs *)ioremap(NAND_PHYS_ADDR, 0x1000);
337 /* Set address of hardware control function */
338 this->hwcontrol = au1550_hwcontrol;
339 this->dev_ready = au1550_device_ready;
340 /* 30 us command delay time */
341 this->chip_delay = 30;
343 this->cmdfunc = au1550_nand_command;
344 this->select_chip = au1550_nand_select_chip;
345 this->write_byte = au1550_nand_write_byte;
346 this->read_byte = au1550_nand_read_byte;
347 this->write_buf = au1550_nand_write_buf;
348 this->read_buf = au1550_nand_read_buf;
349 this->verify_buf = au1550_nand_verify_buf;
350 this->eccmode = NAND_ECC_SOFT;
352 /* Set internal data buffer */
353 this->data_buf = data_buf;
354 this->oob_buf = oob_buf;
356 /* Scan to find existence of the device */
357 if (nand_scan (au1550_mtd, 1)) {
362 /* Register the partitions */
363 add_mtd_partitions(au1550_mtd, partition_info, NUM_PARTITIONS);
368 module_init(au1550_init);
374 static void __exit au1550_cleanup (void)
376 struct nand_chip *this = (struct nand_chip *) &au1550_mtd[1];
378 iounmap ((void *)p_nand);
380 /* Unregister partitions */
381 del_mtd_partitions(au1550_mtd);
383 /* Unregister the device */
384 del_mtd_device (au1550_mtd);
386 /* Free the MTD device structure */
389 module_exit(au1550_cleanup);
392 MODULE_LICENSE("GPL");
393 MODULE_AUTHOR("Embedded Edge, LLC");
394 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");