2 * drivers/mtd/nand/ppchameleonevb.c
4 * Copyright (C) 2003 DAVE Srl (info@wawnet.biz)
6 * Derived from drivers/mtd/nand/edb7312.c
9 * $Id: ppchameleonevb.c,v 1.2 2004/05/05 22:09:54 gleixner Exp $
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 * This is a device driver for the NAND flash devices found on the
17 * PPChameleon/PPChameleonEVB system.
18 * PPChameleon options (autodetected):
20 * - ME model: 32MB (Samsung K9F5608U0B)
21 * - HI model: 128MB (Samsung K9F1G08UOM)
22 * PPChameleonEVB options:
23 * - 32MB (Samsung K9F5608U0B)
26 #include <linux/init.h>
27 #include <linux/slab.h>
28 #include <linux/module.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/mtd/partitions.h>
33 #include <platforms/PPChameleonEVB.h>
35 #undef USE_READY_BUSY_PIN
36 #define USE_READY_BUSY_PIN
37 /* see datasheets (tR) */
38 #define NAND_BIG_DELAY_US 25
39 #define NAND_SMALL_DELAY_US 10
42 #define SZ_4M 0x00400000
43 #define NAND_SMALL_SIZE 0x02000000
44 #define NAND_MTD_NAME "ppchameleon-nand"
45 #define NAND_EVB_MTD_NAME "ppchameleonevb-nand"
47 /* GPIO pins used to drive NAND chip mounted on processor module */
48 #define NAND_nCE_GPIO_PIN (0x80000000 >> 1)
49 #define NAND_CLE_GPIO_PIN (0x80000000 >> 2)
50 #define NAND_ALE_GPIO_PIN (0x80000000 >> 3)
51 #define NAND_RB_GPIO_PIN (0x80000000 >> 4)
52 /* GPIO pins used to drive NAND chip mounted on EVB */
53 #define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14)
54 #define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15)
55 #define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16)
56 #define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31)
59 * MTD structure for PPChameleonEVB board
61 static struct mtd_info *ppchameleon_mtd = NULL;
62 static struct mtd_info *ppchameleonevb_mtd = NULL;
67 static int ppchameleon_fio_pbase = CFG_NAND0_PADDR;
68 static int ppchameleonevb_fio_pbase = CFG_NAND1_PADDR;
71 MODULE_PARM(ppchameleon_fio_pbase, "i");
72 __setup("ppchameleon_fio_pbase=",ppchameleon_fio_pbase);
73 MODULE_PARM(ppchameleonevb_fio_pbase, "i");
74 __setup("ppchameleonevb_fio_pbase=",ppchameleonevb_fio_pbase);
77 /* Internal buffers. Page buffer and oob buffer for one block */
78 static u_char data_buf[2048 + 64];
79 static u_char oob_buf[64 * 64];
80 static u_char data_buf_evb[512 + 16];
81 static u_char oob_buf_evb[16 * 32];
83 #ifdef CONFIG_MTD_PARTITIONS
85 * Define static partitions for flash devices
87 static struct mtd_partition partition_info_hi[] = {
88 { name: "PPChameleon HI Nand Flash",
93 static struct mtd_partition partition_info_me[] = {
94 { name: "PPChameleon ME Nand Flash",
99 static struct mtd_partition partition_info_evb[] = {
100 { name: "PPChameleonEVB Nand Flash",
105 #define NUM_PARTITIONS 1
107 extern int parse_cmdline_partitions(struct mtd_info *master,
108 struct mtd_partition **pparts,
114 * hardware specific access to control-lines
116 static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd)
120 case NAND_CTL_SETCLE:
121 MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
123 case NAND_CTL_CLRCLE:
124 MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
126 case NAND_CTL_SETALE:
127 MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
129 case NAND_CTL_CLRALE:
130 MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
132 case NAND_CTL_SETNCE:
133 MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
135 case NAND_CTL_CLRNCE:
136 MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
141 static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
145 case NAND_CTL_SETCLE:
146 MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
148 case NAND_CTL_CLRCLE:
149 MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
151 case NAND_CTL_SETALE:
152 MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
154 case NAND_CTL_CLRALE:
155 MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
157 case NAND_CTL_SETNCE:
158 MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
160 case NAND_CTL_CLRNCE:
161 MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
166 #ifdef USE_READY_BUSY_PIN
168 * read device ready pin
170 static int ppchameleon_device_ready(struct mtd_info *minfo)
172 if (in_be32((volatile unsigned*)GPIO0_IR) & NAND_RB_GPIO_PIN)
177 static int ppchameleonevb_device_ready(struct mtd_info *minfo)
179 if (in_be32((volatile unsigned*)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN)
185 #ifdef CONFIG_MTD_PARTITIONS
186 const char *part_probes[] = { "cmdlinepart", NULL };
187 const char *part_probes_evb[] = { "cmdlinepart", NULL };
191 * Main initialization routine
193 static int __init ppchameleonevb_init (void)
195 struct nand_chip *this;
196 const char *part_type = 0;
197 int mtd_parts_nb = 0;
198 struct mtd_partition *mtd_parts = 0;
199 int ppchameleon_fio_base;
200 int ppchameleonevb_fio_base;
203 /*********************************
204 * Processor module NAND (if any) *
205 *********************************/
206 /* Allocate memory for MTD device structure and private data */
207 ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) +
208 sizeof(struct nand_chip),
210 if (!ppchameleon_mtd) {
211 printk("Unable to allocate PPChameleon NAND MTD device structure.\n");
215 /* map physical address */
216 ppchameleon_fio_base = (unsigned long)ioremap(ppchameleon_fio_pbase, SZ_4M);
217 if(!ppchameleon_fio_base) {
218 printk("ioremap PPChameleon NAND flash failed\n");
219 kfree(ppchameleon_mtd);
223 /* Get pointer to private data */
224 this = (struct nand_chip *) (&ppchameleon_mtd[1]);
226 /* Initialize structures */
227 memset((char *) ppchameleon_mtd, 0, sizeof(struct mtd_info));
228 memset((char *) this, 0, sizeof(struct nand_chip));
230 /* Link the private data with the MTD structure */
231 ppchameleon_mtd->priv = this;
233 /* Initialize GPIOs */
234 /* Pin mapping for NAND chip */
242 out_be32((volatile unsigned*)GPIO0_OSRH, in_be32((volatile unsigned*)GPIO0_OSRH) & 0xC0FFFFFF);
243 /* three-state select */
244 out_be32((volatile unsigned*)GPIO0_TSRH, in_be32((volatile unsigned*)GPIO0_TSRH) & 0xC0FFFFFF);
245 /* enable output driver */
246 out_be32((volatile unsigned*)GPIO0_TCR, in_be32((volatile unsigned*)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN);
247 #ifdef USE_READY_BUSY_PIN
248 /* three-state select */
249 out_be32((volatile unsigned*)GPIO0_TSRH, in_be32((volatile unsigned*)GPIO0_TSRH) & 0xFF3FFFFF);
250 /* high-impedecence */
251 out_be32((volatile unsigned*)GPIO0_TCR, in_be32((volatile unsigned*)GPIO0_TCR) & (~NAND_RB_GPIO_PIN));
253 out_be32((volatile unsigned*)GPIO0_ISR1H, (in_be32((volatile unsigned*)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000);
256 /* insert callbacks */
257 this->IO_ADDR_R = ppchameleon_fio_base;
258 this->IO_ADDR_W = ppchameleon_fio_base;
259 this->hwcontrol = ppchameleon_hwcontrol;
260 #ifdef USE_READY_BUSY_PIN
261 this->dev_ready = ppchameleon_device_ready;
263 this->chip_delay = NAND_BIG_DELAY_US;
265 this->eccmode = NAND_ECC_SOFT;
267 /* Set internal data buffer */
268 this->data_buf = data_buf;
269 this->oob_buf = oob_buf;
271 /* Scan to find existence of the device (it could not be mounted) */
272 if (nand_scan (ppchameleon_mtd, 1)) {
273 iounmap((void *)ppchameleon_fio_base);
274 kfree (ppchameleon_mtd);
278 #ifndef USE_READY_BUSY_PIN
279 /* Adjust delay if necessary */
280 if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
281 this->chip_delay = NAND_SMALL_DELAY_US;
284 #ifdef CONFIG_MTD_PARTITIONS
285 ppchameleon_mtd->name = "ppchameleon-nand";
286 mtd_parts_nb = parse_mtd_partitions(ppchameleon_mtd, part_probes, &mtd_parts, 0);
287 if (mtd_parts_nb > 0)
288 part_type = "command line";
292 if (mtd_parts_nb == 0)
294 if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
295 mtd_parts = partition_info_me;
297 mtd_parts = partition_info_hi;
298 mtd_parts_nb = NUM_PARTITIONS;
299 part_type = "static";
302 /* Register the partitions */
303 printk(KERN_NOTICE "Using %s partition definition\n", part_type);
304 add_mtd_partitions(ppchameleon_mtd, mtd_parts, mtd_parts_nb);
307 /****************************
308 * EVB NAND (always present) *
309 ****************************/
310 /* Allocate memory for MTD device structure and private data */
311 ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) +
312 sizeof(struct nand_chip),
314 if (!ppchameleonevb_mtd) {
315 printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n");
319 /* map physical address */
320 ppchameleonevb_fio_base = (unsigned long)ioremap(ppchameleonevb_fio_pbase, SZ_4M);
321 if(!ppchameleonevb_fio_base) {
322 printk("ioremap PPChameleonEVB NAND flash failed\n");
323 kfree(ppchameleonevb_mtd);
327 /* Get pointer to private data */
328 this = (struct nand_chip *) (&ppchameleonevb_mtd[1]);
330 /* Initialize structures */
331 memset((char *) ppchameleonevb_mtd, 0, sizeof(struct mtd_info));
332 memset((char *) this, 0, sizeof(struct nand_chip));
334 /* Link the private data with the MTD structure */
335 ppchameleonevb_mtd->priv = this;
337 /* Initialize GPIOs */
338 /* Pin mapping for NAND chip */
346 out_be32((volatile unsigned*)GPIO0_OSRH, in_be32((volatile unsigned*)GPIO0_OSRH) & 0xFFFFFFF0);
347 out_be32((volatile unsigned*)GPIO0_OSRL, in_be32((volatile unsigned*)GPIO0_OSRL) & 0x3FFFFFFF);
348 /* three-state select */
349 out_be32((volatile unsigned*)GPIO0_TSRH, in_be32((volatile unsigned*)GPIO0_TSRH) & 0xFFFFFFF0);
350 out_be32((volatile unsigned*)GPIO0_TSRL, in_be32((volatile unsigned*)GPIO0_TSRL) & 0x3FFFFFFF);
351 /* enable output driver */
352 out_be32((volatile unsigned*)GPIO0_TCR, in_be32((volatile unsigned*)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN | NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN);
353 #ifdef USE_READY_BUSY_PIN
354 /* three-state select */
355 out_be32((volatile unsigned*)GPIO0_TSRL, in_be32((volatile unsigned*)GPIO0_TSRL) & 0xFFFFFFFC);
356 /* high-impedecence */
357 out_be32((volatile unsigned*)GPIO0_TCR, in_be32((volatile unsigned*)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN));
359 out_be32((volatile unsigned*)GPIO0_ISR1L, (in_be32((volatile unsigned*)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001);
363 /* insert callbacks */
364 this->IO_ADDR_R = ppchameleonevb_fio_base;
365 this->IO_ADDR_W = ppchameleonevb_fio_base;
366 this->hwcontrol = ppchameleonevb_hwcontrol;
367 #ifdef USE_READY_BUSY_PIN
368 this->dev_ready = ppchameleonevb_device_ready;
370 this->chip_delay = NAND_SMALL_DELAY_US;
373 this->eccmode = NAND_ECC_SOFT;
375 /* Set internal data buffer */
376 this->data_buf = data_buf_evb;
377 this->oob_buf = oob_buf_evb;
379 /* Scan to find existence of the device */
380 if (nand_scan (ppchameleonevb_mtd, 1)) {
381 iounmap((void *)ppchameleonevb_fio_base);
382 kfree (ppchameleonevb_mtd);
386 #ifdef CONFIG_MTD_PARTITIONS
387 ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME;
388 mtd_parts_nb = parse_mtd_partitions(ppchameleonevb_mtd, part_probes_evb, &mtd_parts, 0);
389 if (mtd_parts_nb > 0)
390 part_type = "command line";
394 if (mtd_parts_nb == 0)
396 mtd_parts = partition_info_evb;
397 mtd_parts_nb = NUM_PARTITIONS;
398 part_type = "static";
401 /* Register the partitions */
402 printk(KERN_NOTICE "Using %s partition definition\n", part_type);
403 add_mtd_partitions(ppchameleonevb_mtd, mtd_parts, mtd_parts_nb);
408 module_init(ppchameleonevb_init);
413 static void __exit ppchameleonevb_cleanup (void)
415 struct nand_chip *this = (struct nand_chip *) &ppchameleonevb_mtd[1];
417 /* Unregister the device */
418 del_mtd_device (ppchameleonevb_mtd);
420 /* Free internal data buffer */
421 kfree (this->data_buf);
423 /* Free the MTD device structure */
424 kfree (ppchameleonevb_mtd);
426 module_exit(ppchameleonevb_cleanup);
428 MODULE_LICENSE("GPL");
429 MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>");
430 MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board");