1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Linux Kernel Additions:
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
93 - Added 802.3x MAC-layer flow control support
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
198 #define DRV_NAME "3c59x"
199 #define DRV_VERSION "LK1.1.19"
200 #define DRV_RELDATE "10 Nov 2002"
204 /* A few values that may be tweaked. */
205 /* Keep the ring sizes a power of two for efficiency. */
206 #define TX_RING_SIZE 16
207 #define RX_RING_SIZE 32
208 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
210 /* "Knobs" that adjust features and parameters. */
211 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
212 Setting to > 1512 effectively disables this feature. */
214 static int rx_copybreak = 200;
216 /* ARM systems perform better by disregarding the bus-master
217 transfer capability of these cards. -- rmk */
218 static int rx_copybreak = 1513;
220 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
221 static const int mtu = 1500;
222 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
223 static int max_interrupt_work = 32;
224 /* Tx timeout interval (millisecs) */
225 static int watchdog = 5000;
227 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
228 * of possible Tx stalls if the system is blocking interrupts
229 * somewhere else. Undefine this to disable.
231 #define tx_interrupt_mitigation 1
233 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
234 #define vortex_debug debug
236 static int vortex_debug = VORTEX_DEBUG;
238 static int vortex_debug = 1;
241 #include <linux/config.h>
242 #include <linux/module.h>
243 #include <linux/kernel.h>
244 #include <linux/string.h>
245 #include <linux/timer.h>
246 #include <linux/errno.h>
247 #include <linux/in.h>
248 #include <linux/ioport.h>
249 #include <linux/slab.h>
250 #include <linux/interrupt.h>
251 #include <linux/pci.h>
252 #include <linux/mii.h>
253 #include <linux/init.h>
254 #include <linux/netdevice.h>
255 #include <linux/etherdevice.h>
256 #include <linux/skbuff.h>
257 #include <linux/ethtool.h>
258 #include <linux/highmem.h>
259 #include <linux/eisa.h>
260 #include <asm/irq.h> /* For NR_IRQS only. */
261 #include <asm/bitops.h>
263 #include <asm/uaccess.h>
265 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
266 This is only in the support-all-kernels source code. */
268 #define RUN_AT(x) (jiffies + (x))
270 #include <linux/delay.h>
273 static char version[] __devinitdata =
274 DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
276 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
277 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver "
278 DRV_VERSION " " DRV_RELDATE);
279 MODULE_LICENSE("GPL");
281 MODULE_PARM(debug, "i");
282 MODULE_PARM(global_options, "i");
283 MODULE_PARM(options, "1-" __MODULE_STRING(8) "i");
284 MODULE_PARM(global_full_duplex, "i");
285 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i");
286 MODULE_PARM(hw_checksums, "1-" __MODULE_STRING(8) "i");
287 MODULE_PARM(flow_ctrl, "1-" __MODULE_STRING(8) "i");
288 MODULE_PARM(global_enable_wol, "i");
289 MODULE_PARM(enable_wol, "1-" __MODULE_STRING(8) "i");
290 MODULE_PARM(rx_copybreak, "i");
291 MODULE_PARM(max_interrupt_work, "i");
292 MODULE_PARM(compaq_ioaddr, "i");
293 MODULE_PARM(compaq_irq, "i");
294 MODULE_PARM(compaq_device_id, "i");
295 MODULE_PARM(watchdog, "i");
296 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
297 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
298 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
299 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
300 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if options is unset");
301 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
302 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
303 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
304 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if options is unset");
305 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
306 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
307 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
308 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
309 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
310 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
312 /* Operational parameter that usually are not changed. */
314 /* The Vortex size is twice that of the original EtherLinkIII series: the
315 runtime register window, window 1, is now always mapped in.
316 The Boomerang size is twice as large as the Vortex -- it has additional
317 bus master control registers. */
318 #define VORTEX_TOTAL_SIZE 0x20
319 #define BOOMERANG_TOTAL_SIZE 0x40
321 /* Set iff a MII transceiver on any interface requires mdio preamble.
322 This only set with the original DP83840 on older 3c905 boards, so the extra
323 code size of a per-interface flag is not worthwhile. */
324 static char mii_preamble_required;
326 #define PFX DRV_NAME ": "
333 I. Board Compatibility
335 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
336 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
337 versions of the FastEtherLink cards. The supported product IDs are
338 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
340 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
341 with the kernel source or available from
342 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
344 II. Board-specific settings
346 PCI bus devices are configured by the system at boot time, so no jumpers
347 need to be set on the board. The system BIOS should be set to assign the
348 PCI INTA signal to an otherwise unused system IRQ line.
350 The EEPROM settings for media type and forced-full-duplex are observed.
351 The EEPROM media type should be left at the default "autoselect" unless using
352 10base2 or AUI connections which cannot be reliably detected.
354 III. Driver operation
356 The 3c59x series use an interface that's very similar to the previous 3c5x9
357 series. The primary interface is two programmed-I/O FIFOs, with an
358 alternate single-contiguous-region bus-master transfer (see next).
360 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
361 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
362 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
363 programmed-I/O interface that has been removed in 'B' and subsequent board
366 One extension that is advertised in a very large font is that the adapters
367 are capable of being bus masters. On the Vortex chip this capability was
368 only for a single contiguous region making it far less useful than the full
369 bus master capability. There is a significant performance impact of taking
370 an extra interrupt or polling for the completion of each transfer, as well
371 as difficulty sharing the single transfer engine between the transmit and
372 receive threads. Using DMA transfers is a win only with large blocks or
373 with the flawed versions of the Intel Orion motherboard PCI controller.
375 The Boomerang chip's full-bus-master interface is useful, and has the
376 currently-unused advantages over other similar chips that queued transmit
377 packets may be reordered and receive buffer groups are associated with a
380 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
381 Rather than a fixed intermediate receive buffer, this scheme allocates
382 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
383 the copying breakpoint: it is chosen to trade-off the memory wasted by
384 passing the full-sized skbuff to the queue layer for all frames vs. the
385 copying cost of copying a frame to a correctly-sized skbuff.
387 IIIC. Synchronization
388 The driver runs as two independent, single-threaded flows of control. One
389 is the send-packet routine, which enforces single-threaded use by the
390 dev->tbusy flag. The other thread is the interrupt handler, which is single
391 threaded by the hardware and other software.
395 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
396 3c590, 3c595, and 3c900 boards.
397 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
398 the EISA version is called "Demon". According to Terry these names come
399 from rides at the local amusement park.
401 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
402 This driver only supports ethernet packets because of the skbuff allocation
406 /* This table drives the PCI probe routines. It's mostly boilerplate in all
407 of the drivers, and will likely be provided by some future kernel.
410 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
411 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
414 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
415 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
416 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
417 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
418 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
419 EXTRA_PREAMBLE=0x8000, };
470 /* note: this array directly indexed by above enums, and MUST
471 * be kept in sync with both the enums above, and the PCI device
474 static struct vortex_chip_info {
479 } vortex_info_tbl[] __devinitdata = {
480 {"3c590 Vortex 10Mbps",
481 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
482 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
483 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
484 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
485 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
486 {"3c595 Vortex 100baseTx",
487 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
488 {"3c595 Vortex 100baseT4",
489 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
491 {"3c595 Vortex 100base-MII",
492 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
493 {"3c900 Boomerang 10baseT",
494 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, },
495 {"3c900 Boomerang 10Mbps Combo",
496 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, },
497 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
498 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
499 {"3c900 Cyclone 10Mbps Combo",
500 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
502 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
503 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
504 {"3c900B-FL Cyclone 10base-FL",
505 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
506 {"3c905 Boomerang 100baseTx",
507 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, },
508 {"3c905 Boomerang 100baseT4",
509 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, },
510 {"3c905B Cyclone 100baseTx",
511 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
513 {"3c905B Cyclone 10/100/BNC",
514 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
515 {"3c905B-FX Cyclone 100baseFx",
516 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
518 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
519 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
520 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
522 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
525 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
526 {"3cSOHO100-TX Hurricane",
527 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
528 {"3c555 Laptop Hurricane",
529 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
530 {"3c556 Laptop Tornado",
531 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
533 {"3c556B Laptop Hurricane",
534 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
535 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
537 {"3c575 [Megahertz] 10/100 LAN CardBus",
538 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
539 {"3c575 Boomerang CardBus",
540 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
541 {"3CCFE575BT Cyclone CardBus",
542 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
543 INVERT_LED_PWR|HAS_HWCKSM, 128, },
544 {"3CCFE575CT Tornado CardBus",
545 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
546 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
547 {"3CCFE656 Cyclone CardBus",
548 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
549 INVERT_LED_PWR|HAS_HWCKSM, 128, },
551 {"3CCFEM656B Cyclone+Winmodem CardBus",
552 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
553 INVERT_LED_PWR|HAS_HWCKSM, 128, },
554 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
555 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
556 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
557 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
558 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
560 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
561 {"3c982 Hydra Dual Port A",
562 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
564 {"3c982 Hydra Dual Port B",
565 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
567 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
568 {"3c920B-EMB-WNM Tornado",
569 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
571 {NULL,}, /* NULL terminated list. */
575 static struct pci_device_id vortex_pci_tbl[] = {
576 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
577 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
578 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
579 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
580 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
582 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
583 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
584 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
585 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
586 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
588 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
589 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
590 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
591 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
592 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
594 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
595 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
596 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
597 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
598 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
599 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
601 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
602 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
603 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
604 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
605 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
607 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
608 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
609 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
610 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
611 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
613 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
614 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
615 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
616 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
617 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
619 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
620 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
622 {0,} /* 0 terminated list. */
624 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
627 /* Operational definitions.
628 These are not used by other compilation units and thus are not
629 exported in a ".h" file.
631 First the windows. There are eight register windows, with the command
632 and status registers available in each.
634 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
636 #define EL3_STATUS 0x0e
638 /* The top five bits written to EL3_CMD are a command, the lower
639 11 bits are the parameter, if applicable.
640 Note that 11 parameters bits was fine for ethernet, but the new chip
641 can handle FDDI length frames (~4500 octets) and now parameters count
642 32-bit 'Dwords' rather than octets. */
645 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
646 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
647 UpStall = 6<<11, UpUnstall = (6<<11)+1,
648 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
649 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
650 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
651 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
652 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
653 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
654 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
656 /* The SetRxFilter command accepts the following classes: */
658 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
660 /* Bits in the general status register. */
662 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
663 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
664 IntReq = 0x0040, StatsFull = 0x0080,
665 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
666 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
667 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
670 /* Register window 1 offsets, the window used in normal operation.
671 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
673 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
674 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
675 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
678 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
679 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
680 IntrStatus=0x0E, /* Valid in all windows. */
682 enum Win0_EEPROM_bits {
683 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
684 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
685 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
687 /* EEPROM locations. */
689 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
690 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
691 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
692 DriverTune=13, Checksum=15};
694 enum Window2 { /* Window 2. */
697 enum Window3 { /* Window 3: MAC/config bits. */
698 Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8,
701 #define BFEXT(value, offset, bitcount) \
702 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
704 #define BFINS(lhs, rhs, offset, bitcount) \
705 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
706 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
708 #define RAM_SIZE(v) BFEXT(v, 0, 3)
709 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
710 #define RAM_SPEED(v) BFEXT(v, 4, 2)
711 #define ROM_SIZE(v) BFEXT(v, 6, 2)
712 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
713 #define XCVR(v) BFEXT(v, 20, 4)
714 #define AUTOSELECT(v) BFEXT(v, 24, 1)
716 enum Window4 { /* Window 4: Xcvr/media bits. */
717 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
719 enum Win4_Media_bits {
720 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
721 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
722 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
723 Media_LnkBeat = 0x0800,
725 enum Window7 { /* Window 7: Bus Master control. */
726 Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12,
728 /* Boomerang bus master control registers. */
730 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
731 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
734 /* The Rx and Tx descriptor lists.
735 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
736 alignment contraint on tx_ring[] and rx_ring[]. */
737 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
738 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
739 struct boom_rx_desc {
740 u32 next; /* Last entry points to 0. */
742 u32 addr; /* Up to 63 addr/len pairs possible. */
743 s32 length; /* Set LAST_FRAG to indicate last pair. */
745 /* Values for the Rx status entry. */
746 enum rx_desc_status {
747 RxDComplete=0x00008000, RxDError=0x4000,
748 /* See boomerang_rx() for actual error bits */
749 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
750 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
754 #define DO_ZEROCOPY 1
756 #define DO_ZEROCOPY 0
759 struct boom_tx_desc {
760 u32 next; /* Last entry points to 0. */
761 s32 status; /* bits 0:12 length, others see below. */
766 } frag[1+MAX_SKB_FRAGS];
773 /* Values for the Tx status entry. */
774 enum tx_desc_status {
775 CRCDisable=0x2000, TxDComplete=0x8000,
776 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
777 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
780 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
781 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
783 struct vortex_private {
784 /* The Rx and Tx rings should be quad-word-aligned. */
785 struct boom_rx_desc* rx_ring;
786 struct boom_tx_desc* tx_ring;
787 dma_addr_t rx_ring_dma;
788 dma_addr_t tx_ring_dma;
789 /* The addresses of transmit- and receive-in-place skbuffs. */
790 struct sk_buff* rx_skbuff[RX_RING_SIZE];
791 struct sk_buff* tx_skbuff[TX_RING_SIZE];
792 unsigned int cur_rx, cur_tx; /* The next free ring entry */
793 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
794 struct net_device_stats stats;
795 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
796 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
798 /* PCI configuration space information. */
799 struct device *gendev;
800 char *cb_fn_base; /* CardBus function status addr space. */
802 /* Some values here only for performance evaluation and path-coverage */
803 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
806 /* The remainder are related to chip state, mostly media selection. */
807 struct timer_list timer; /* Media selection timer. */
808 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
809 int options; /* User-settable misc. driver options. */
810 unsigned int media_override:4, /* Passed-in media type. */
811 default_media:4, /* Read from the EEPROM/Wn3_Config. */
812 full_duplex:1, force_fd:1, autoselect:1,
813 bus_master:1, /* Vortex can only do a fragment bus-m. */
814 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
815 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
816 partner_flow_ctrl:1, /* Partner supports flow control */
818 enable_wol:1, /* Wake-on-LAN is enabled */
819 pm_state_valid:1, /* power_state[] has sane contents */
822 must_free_region:1; /* Flag: if zero, Cardbus owns the I/O region */
826 u16 available_media; /* From Wn3_Options. */
827 u16 capabilities, info1, info2; /* Various, from EEPROM. */
828 u16 advertising; /* NWay media advertisement */
829 unsigned char phys[2]; /* MII device addresses. */
830 u16 deferred; /* Resend these interrupts when we
831 * bale from the ISR */
832 u16 io_size; /* Size of PCI region (for release_region) */
833 spinlock_t lock; /* Serialise access to device & its vortex_private */
834 spinlock_t mdio_lock; /* Serialise access to mdio hardware */
839 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
841 #define DEVICE_PCI(dev) NULL
844 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
847 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
849 #define DEVICE_EISA(dev) NULL
852 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
854 /* The action to take with a media selection timer tick.
855 Note that we deviate from the 3Com order by checking 10base2 before AUI.
858 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
859 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
862 static struct media_table {
864 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
865 mask:8, /* The transceiver-present bit in Wn3_Config.*/
866 next:8; /* The media type to try next. */
867 int wait; /* Time before we check media status. */
869 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
870 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
871 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
872 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
873 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
874 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
875 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
876 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
877 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
878 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
879 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
882 static int vortex_probe1(struct device *gendev, long ioaddr, int irq,
883 int chip_idx, int card_idx);
884 static void vortex_up(struct net_device *dev);
885 static void vortex_down(struct net_device *dev, int final);
886 static int vortex_open(struct net_device *dev);
887 static void mdio_sync(long ioaddr, int bits);
888 static int mdio_read(struct net_device *dev, int phy_id, int location);
889 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
890 static void vortex_timer(unsigned long arg);
891 static void rx_oom_timer(unsigned long arg);
892 static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
893 static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
894 static int vortex_rx(struct net_device *dev);
895 static int boomerang_rx(struct net_device *dev);
896 static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
897 static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
898 static int vortex_close(struct net_device *dev);
899 static void dump_tx_ring(struct net_device *dev);
900 static void update_stats(long ioaddr, struct net_device *dev);
901 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
902 static void set_rx_mode(struct net_device *dev);
903 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
904 static void vortex_tx_timeout(struct net_device *dev);
905 static void acpi_set_WOL(struct net_device *dev);
906 static struct ethtool_ops vortex_ethtool_ops;
908 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
909 /* Option count limit only -- unlimited interfaces are supported. */
911 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1,};
912 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
913 static int hw_checksums[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
914 static int flow_ctrl[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
915 static int enable_wol[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
916 static int global_options = -1;
917 static int global_full_duplex = -1;
918 static int global_enable_wol = -1;
920 /* #define dev_alloc_skb dev_alloc_skb_debug */
922 /* Variables to work-around the Compaq PCI BIOS32 problem. */
923 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
924 static struct net_device *compaq_net_device;
926 static int vortex_cards_found;
928 #ifdef CONFIG_NET_POLL_CONTROLLER
929 static void poll_vortex(struct net_device *dev)
931 struct vortex_private *vp = (struct vortex_private *)dev->priv;
933 local_save_flags(flags);
935 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
936 local_irq_restore(flags);
942 static int vortex_suspend (struct pci_dev *pdev, u32 state)
944 struct net_device *dev = pci_get_drvdata(pdev);
946 if (dev && dev->priv) {
947 if (netif_running(dev)) {
948 netif_device_detach(dev);
955 static int vortex_resume (struct pci_dev *pdev)
957 struct net_device *dev = pci_get_drvdata(pdev);
959 if (dev && dev->priv) {
960 if (netif_running(dev)) {
962 netif_device_attach(dev);
968 #endif /* CONFIG_PM */
971 static struct eisa_device_id vortex_eisa_ids[] = {
972 { "TCM5920", CH_3C592 },
973 { "TCM5970", CH_3C597 },
977 static int vortex_eisa_probe (struct device *device);
978 static int vortex_eisa_remove (struct device *device);
980 static struct eisa_driver vortex_eisa_driver = {
981 .id_table = vortex_eisa_ids,
984 .probe = vortex_eisa_probe,
985 .remove = vortex_eisa_remove
989 static int vortex_eisa_probe (struct device *device)
992 struct eisa_device *edev;
994 edev = to_eisa_device (device);
995 ioaddr = edev->base_addr;
997 if (!request_region(ioaddr, VORTEX_TOTAL_SIZE, DRV_NAME))
1000 if (vortex_probe1(device, ioaddr, inw(ioaddr + 0xC88) >> 12,
1001 edev->id.driver_data, vortex_cards_found)) {
1002 release_region (ioaddr, VORTEX_TOTAL_SIZE);
1006 vortex_cards_found++;
1011 static int vortex_eisa_remove (struct device *device)
1013 struct eisa_device *edev;
1014 struct net_device *dev;
1015 struct vortex_private *vp;
1018 edev = to_eisa_device (device);
1019 dev = eisa_get_drvdata (edev);
1022 printk("vortex_eisa_remove called for Compaq device!\n");
1026 vp = netdev_priv(dev);
1027 ioaddr = dev->base_addr;
1029 unregister_netdev (dev);
1030 outw (TotalReset|0x14, ioaddr + EL3_CMD);
1031 release_region (ioaddr, VORTEX_TOTAL_SIZE);
1038 /* returns count found (>= 0), or negative on error */
1039 static int __init vortex_eisa_init (void)
1042 int orig_cards_found = vortex_cards_found;
1045 if (eisa_driver_register (&vortex_eisa_driver) >= 0) {
1046 /* Because of the way EISA bus is probed, we cannot assume
1047 * any device have been found when we exit from
1048 * eisa_driver_register (the bus root driver may not be
1049 * initialized yet). So we blindly assume something was
1050 * found, and let the sysfs magic happend... */
1056 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1057 if (compaq_ioaddr) {
1058 vortex_probe1(NULL, compaq_ioaddr, compaq_irq,
1059 compaq_device_id, vortex_cards_found++);
1062 return vortex_cards_found - orig_cards_found + eisa_found;
1065 /* returns count (>= 0), or negative on error */
1066 static int __devinit vortex_init_one (struct pci_dev *pdev,
1067 const struct pci_device_id *ent)
1071 /* wake up and enable device */
1072 if (pci_enable_device (pdev)) {
1075 rc = vortex_probe1 (&pdev->dev, pci_resource_start (pdev, 0),
1076 pdev->irq, ent->driver_data, vortex_cards_found);
1078 vortex_cards_found++;
1084 * Start up the PCI/EISA device which is described by *gendev.
1085 * Return 0 on success.
1087 * NOTE: pdev can be NULL, for the case of a Compaq device
1089 static int __devinit vortex_probe1(struct device *gendev,
1090 long ioaddr, int irq,
1091 int chip_idx, int card_idx)
1093 struct vortex_private *vp;
1095 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1097 struct net_device *dev;
1098 static int printed_version;
1099 int retval, print_info;
1100 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1101 char *print_name = "3c59x";
1102 struct pci_dev *pdev = NULL;
1103 struct eisa_device *edev = NULL;
1105 if (!printed_version) {
1107 printed_version = 1;
1111 if ((pdev = DEVICE_PCI(gendev))) {
1112 print_name = pci_name(pdev);
1115 if ((edev = DEVICE_EISA(gendev))) {
1116 print_name = edev->dev.bus_id;
1120 dev = alloc_etherdev(sizeof(*vp));
1123 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1126 SET_MODULE_OWNER(dev);
1127 SET_NETDEV_DEV(dev, gendev);
1128 vp = netdev_priv(dev);
1130 option = global_options;
1132 /* The lower four bits are the media type. */
1133 if (dev->mem_start) {
1135 * The 'options' param is passed in as the third arg to the
1136 * LILO 'ether=' argument for non-modular use
1138 option = dev->mem_start;
1140 else if (card_idx < MAX_UNITS) {
1141 if (options[card_idx] >= 0)
1142 option = options[card_idx];
1146 if (option & 0x8000)
1148 if (option & 0x4000)
1150 if (option & 0x0400)
1154 print_info = (vortex_debug > 1);
1156 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1158 printk(KERN_INFO "%s: 3Com %s %s at 0x%lx. Vers " DRV_VERSION "\n",
1160 pdev ? "PCI" : "EISA",
1164 dev->base_addr = ioaddr;
1167 vp->drv_flags = vci->drv_flags;
1168 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1169 vp->io_size = vci->io_size;
1170 vp->card_idx = card_idx;
1172 /* module list only for Compaq device */
1173 if (gendev == NULL) {
1174 compaq_net_device = dev;
1177 /* PCI-only startup logic */
1179 /* EISA resources already marked, so only PCI needs to do this here */
1180 /* Ignore return value, because Cardbus drivers already allocate for us */
1181 if (request_region(ioaddr, vci->io_size, print_name) != NULL)
1182 vp->must_free_region = 1;
1184 /* enable bus-mastering if necessary */
1185 if (vci->flags & PCI_USES_MASTER)
1186 pci_set_master (pdev);
1188 if (vci->drv_flags & IS_VORTEX) {
1190 u8 new_latency = 248;
1192 /* Check the PCI latency value. On the 3c590 series the latency timer
1193 must be set to the maximum value to avoid data corruption that occurs
1194 when the timer expires during a transfer. This bug exists the Vortex
1196 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1197 if (pci_latency < new_latency) {
1198 printk(KERN_INFO "%s: Overriding PCI latency"
1199 " timer (CFLT) setting of %d, new value is %d.\n",
1200 print_name, pci_latency, new_latency);
1201 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1206 spin_lock_init(&vp->lock);
1207 spin_lock_init(&vp->mdio_lock);
1208 vp->gendev = gendev;
1210 /* Makes sure rings are at least 16 byte aligned. */
1211 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1212 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1215 if (vp->rx_ring == 0)
1218 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1219 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1221 /* if we are a PCI driver, we store info in pdev->driver_data
1222 * instead of a module list */
1224 pci_set_drvdata(pdev, dev);
1226 eisa_set_drvdata (edev, dev);
1228 vp->media_override = 7;
1230 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1231 if (vp->media_override != 7)
1233 vp->full_duplex = (option & 0x200) ? 1 : 0;
1234 vp->bus_master = (option & 16) ? 1 : 0;
1237 if (global_full_duplex > 0)
1238 vp->full_duplex = 1;
1239 if (global_enable_wol > 0)
1242 if (card_idx < MAX_UNITS) {
1243 if (full_duplex[card_idx] > 0)
1244 vp->full_duplex = 1;
1245 if (flow_ctrl[card_idx] > 0)
1247 if (enable_wol[card_idx] > 0)
1251 vp->force_fd = vp->full_duplex;
1252 vp->options = option;
1253 /* Read the station address from the EEPROM. */
1258 if (vci->drv_flags & EEPROM_8BIT)
1260 else if (vci->drv_flags & EEPROM_OFFSET)
1261 base = EEPROM_Read + 0x30;
1265 for (i = 0; i < 0x40; i++) {
1267 outw(base + i, ioaddr + Wn0EepromCmd);
1268 /* Pause for at least 162 us. for the read to take place. */
1269 for (timer = 10; timer >= 0; timer--) {
1271 if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1274 eeprom[i] = inw(ioaddr + Wn0EepromData);
1277 for (i = 0; i < 0x18; i++)
1278 checksum ^= eeprom[i];
1279 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1280 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1282 checksum ^= eeprom[i++];
1283 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1285 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1286 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1287 for (i = 0; i < 3; i++)
1288 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1290 for (i = 0; i < 6; i++)
1291 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1294 for (i = 0; i < 6; i++)
1295 outb(dev->dev_addr[i], ioaddr + i);
1299 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1302 printk(", IRQ %d\n", dev->irq);
1303 /* Tell them about an invalid IRQ. */
1304 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1305 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1310 step = (inb(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1312 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1313 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1314 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1318 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1319 unsigned long fn_st_addr; /* Cardbus function status space */
1322 fn_st_addr = pci_resource_start (pdev, 2);
1324 vp->cb_fn_base = ioremap(fn_st_addr, 128);
1326 if (!vp->cb_fn_base)
1330 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
1331 print_name, fn_st_addr, vp->cb_fn_base);
1335 n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
1336 if (vp->drv_flags & INVERT_LED_PWR)
1338 if (vp->drv_flags & INVERT_MII_PWR)
1340 outw(n, ioaddr + Wn2_ResetOptions);
1341 if (vp->drv_flags & WNO_XCVR_PWR) {
1343 outw(0x0800, ioaddr);
1347 /* Extract our information from the EEPROM data. */
1348 vp->info1 = eeprom[13];
1349 vp->info2 = eeprom[15];
1350 vp->capabilities = eeprom[16];
1352 if (vp->info1 & 0x8000) {
1353 vp->full_duplex = 1;
1355 printk(KERN_INFO "Full duplex capable\n");
1359 static const char * ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1360 unsigned int config;
1362 vp->available_media = inw(ioaddr + Wn3_Options);
1363 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1364 vp->available_media = 0x40;
1365 config = inl(ioaddr + Wn3_Config);
1367 printk(KERN_DEBUG " Internal config register is %4.4x, "
1368 "transceivers %#x.\n", config, inw(ioaddr + Wn3_Options));
1369 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1370 8 << RAM_SIZE(config),
1371 RAM_WIDTH(config) ? "word" : "byte",
1372 ram_split[RAM_SPLIT(config)],
1373 AUTOSELECT(config) ? "autoselect/" : "",
1374 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1375 media_tbl[XCVR(config)].name);
1377 vp->default_media = XCVR(config);
1378 if (vp->default_media == XCVR_NWAY)
1380 vp->autoselect = AUTOSELECT(config);
1383 if (vp->media_override != 7) {
1384 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1385 print_name, vp->media_override,
1386 media_tbl[vp->media_override].name);
1387 dev->if_port = vp->media_override;
1389 dev->if_port = vp->default_media;
1391 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1392 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1393 int phy, phy_idx = 0;
1395 mii_preamble_required++;
1396 if (vp->drv_flags & EXTRA_PREAMBLE)
1397 mii_preamble_required++;
1398 mdio_sync(ioaddr, 32);
1399 mdio_read(dev, 24, 1);
1400 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1401 int mii_status, phyx;
1404 * For the 3c905CX we look at index 24 first, because it bogusly
1405 * reports an external PHY at all indices
1413 mii_status = mdio_read(dev, phyx, 1);
1414 if (mii_status && mii_status != 0xffff) {
1415 vp->phys[phy_idx++] = phyx;
1417 printk(KERN_INFO " MII transceiver found at address %d,"
1418 " status %4x.\n", phyx, mii_status);
1420 if ((mii_status & 0x0040) == 0)
1421 mii_preamble_required++;
1424 mii_preamble_required--;
1426 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1429 vp->advertising = mdio_read(dev, vp->phys[0], 4);
1430 if (vp->full_duplex) {
1431 /* Only advertise the FD media types. */
1432 vp->advertising &= ~0x02A0;
1433 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1438 if (vp->capabilities & CapBusMaster) {
1439 vp->full_bus_master_tx = 1;
1441 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1442 (vp->info2 & 1) ? "early" : "whole-frame" );
1444 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1445 vp->bus_master = 0; /* AKPM: vortex only */
1448 /* The 3c59x-specific entries in the device structure. */
1449 dev->open = vortex_open;
1450 if (vp->full_bus_master_tx) {
1451 dev->hard_start_xmit = boomerang_start_xmit;
1452 /* Actually, it still should work with iommu. */
1453 dev->features |= NETIF_F_SG;
1454 if (((hw_checksums[card_idx] == -1) && (vp->drv_flags & HAS_HWCKSM)) ||
1455 (hw_checksums[card_idx] == 1)) {
1456 dev->features |= NETIF_F_IP_CSUM;
1459 dev->hard_start_xmit = vortex_start_xmit;
1463 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1465 (dev->features & NETIF_F_SG) ? "en":"dis",
1466 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1469 dev->stop = vortex_close;
1470 dev->get_stats = vortex_get_stats;
1471 dev->do_ioctl = vortex_ioctl;
1472 dev->ethtool_ops = &vortex_ethtool_ops;
1473 dev->set_multicast_list = set_rx_mode;
1474 dev->tx_timeout = vortex_tx_timeout;
1475 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1476 #ifdef CONFIG_NET_POLL_CONTROLLER
1477 dev->poll_controller = poll_vortex;
1479 if (pdev && vp->enable_wol) {
1480 vp->pm_state_valid = 1;
1481 pci_save_state(VORTEX_PCI(vp), vp->power_state);
1484 retval = register_netdev(dev);
1489 pci_free_consistent(pdev,
1490 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1491 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1495 if (vp->must_free_region)
1496 release_region(ioaddr, vci->io_size);
1498 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1504 issue_and_wait(struct net_device *dev, int cmd)
1508 outw(cmd, dev->base_addr + EL3_CMD);
1509 for (i = 0; i < 2000; i++) {
1510 if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress))
1514 /* OK, that didn't work. Do it the slow way. One second */
1515 for (i = 0; i < 100000; i++) {
1516 if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress)) {
1517 if (vortex_debug > 1)
1518 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1519 dev->name, cmd, i * 10);
1524 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1525 dev->name, cmd, inw(dev->base_addr + EL3_STATUS));
1529 vortex_up(struct net_device *dev)
1531 long ioaddr = dev->base_addr;
1532 struct vortex_private *vp = netdev_priv(dev);
1533 unsigned int config;
1536 if (VORTEX_PCI(vp) && vp->enable_wol) {
1537 pci_set_power_state(VORTEX_PCI(vp), 0); /* Go active */
1538 pci_restore_state(VORTEX_PCI(vp), vp->power_state);
1541 /* Before initializing select the active media port. */
1543 config = inl(ioaddr + Wn3_Config);
1545 if (vp->media_override != 7) {
1546 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1547 dev->name, vp->media_override,
1548 media_tbl[vp->media_override].name);
1549 dev->if_port = vp->media_override;
1550 } else if (vp->autoselect) {
1552 if (vortex_debug > 1)
1553 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1554 dev->name, dev->if_port);
1555 dev->if_port = XCVR_NWAY;
1557 /* Find first available media type, starting with 100baseTx. */
1558 dev->if_port = XCVR_100baseTx;
1559 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1560 dev->if_port = media_tbl[dev->if_port].next;
1561 if (vortex_debug > 1)
1562 printk(KERN_INFO "%s: first available media type: %s\n",
1563 dev->name, media_tbl[dev->if_port].name);
1566 dev->if_port = vp->default_media;
1567 if (vortex_debug > 1)
1568 printk(KERN_INFO "%s: using default media %s\n",
1569 dev->name, media_tbl[dev->if_port].name);
1572 init_timer(&vp->timer);
1573 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1574 vp->timer.data = (unsigned long)dev;
1575 vp->timer.function = vortex_timer; /* timer handler */
1576 add_timer(&vp->timer);
1578 init_timer(&vp->rx_oom_timer);
1579 vp->rx_oom_timer.data = (unsigned long)dev;
1580 vp->rx_oom_timer.function = rx_oom_timer;
1582 if (vortex_debug > 1)
1583 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1584 dev->name, media_tbl[dev->if_port].name);
1586 vp->full_duplex = vp->force_fd;
1587 config = BFINS(config, dev->if_port, 20, 4);
1588 if (vortex_debug > 6)
1589 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
1590 outl(config, ioaddr + Wn3_Config);
1592 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1593 int mii_reg1, mii_reg5;
1595 /* Read BMSR (reg1) only to clear old status. */
1596 mii_reg1 = mdio_read(dev, vp->phys[0], 1);
1597 mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1598 if (mii_reg5 == 0xffff || mii_reg5 == 0x0000) {
1599 netif_carrier_off(dev); /* No MII device or no link partner report */
1601 mii_reg5 &= vp->advertising;
1602 if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */
1603 || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */
1604 vp->full_duplex = 1;
1605 netif_carrier_on(dev);
1607 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1608 if (vortex_debug > 1)
1609 printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x,"
1610 " info1 %04x, setting %s-duplex.\n",
1611 dev->name, vp->phys[0],
1613 vp->info1, ((vp->info1 & 0x8000) || vp->full_duplex) ? "full" : "half");
1617 /* Set the full-duplex bit. */
1618 outw( ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1619 (dev->mtu > 1500 ? 0x40 : 0) |
1620 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1621 ioaddr + Wn3_MAC_Ctrl);
1623 if (vortex_debug > 1) {
1624 printk(KERN_DEBUG "%s: vortex_up() InternalConfig %8.8x.\n",
1628 issue_and_wait(dev, TxReset);
1630 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1632 issue_and_wait(dev, RxReset|0x04);
1634 outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1636 if (vortex_debug > 1) {
1638 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1639 dev->name, dev->irq, inw(ioaddr + Wn4_Media));
1642 /* Set the station address and mask in window 2 each time opened. */
1644 for (i = 0; i < 6; i++)
1645 outb(dev->dev_addr[i], ioaddr + i);
1646 for (; i < 12; i+=2)
1647 outw(0, ioaddr + i);
1649 if (vp->cb_fn_base) {
1650 unsigned short n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
1651 if (vp->drv_flags & INVERT_LED_PWR)
1653 if (vp->drv_flags & INVERT_MII_PWR)
1655 outw(n, ioaddr + Wn2_ResetOptions);
1658 if (dev->if_port == XCVR_10base2)
1659 /* Start the thinnet transceiver. We should really wait 50ms...*/
1660 outw(StartCoax, ioaddr + EL3_CMD);
1661 if (dev->if_port != XCVR_NWAY) {
1663 outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1664 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1667 /* Switch to the stats window, and clear all stats by reading. */
1668 outw(StatsDisable, ioaddr + EL3_CMD);
1670 for (i = 0; i < 10; i++)
1674 /* New: On the Vortex we must also clear the BadSSD counter. */
1677 /* ..and on the Boomerang we enable the extra statistics bits. */
1678 outw(0x0040, ioaddr + Wn4_NetDiag);
1680 /* Switch to register set 7 for normal use. */
1683 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1684 vp->cur_rx = vp->dirty_rx = 0;
1685 /* Initialize the RxEarly register as recommended. */
1686 outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1687 outl(0x0020, ioaddr + PktStatus);
1688 outl(vp->rx_ring_dma, ioaddr + UpListPtr);
1690 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1691 vp->cur_tx = vp->dirty_tx = 0;
1692 if (vp->drv_flags & IS_BOOMERANG)
1693 outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1694 /* Clear the Rx, Tx rings. */
1695 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1696 vp->rx_ring[i].status = 0;
1697 for (i = 0; i < TX_RING_SIZE; i++)
1698 vp->tx_skbuff[i] = NULL;
1699 outl(0, ioaddr + DownListPtr);
1701 /* Set receiver mode: presumably accept b-case and phys addr only. */
1703 outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1705 // issue_and_wait(dev, SetTxStart|0x07ff);
1706 outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1707 outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1708 /* Allow status bits to be seen. */
1709 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1710 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1711 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1712 (vp->bus_master ? DMADone : 0);
1713 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1714 (vp->full_bus_master_rx ? 0 : RxComplete) |
1715 StatsFull | HostError | TxComplete | IntReq
1716 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1717 outw(vp->status_enable, ioaddr + EL3_CMD);
1718 /* Ack all pending events, and set active indicator mask. */
1719 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1721 outw(vp->intr_enable, ioaddr + EL3_CMD);
1722 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1723 writel(0x8000, vp->cb_fn_base + 4);
1724 netif_start_queue (dev);
1728 vortex_open(struct net_device *dev)
1730 struct vortex_private *vp = netdev_priv(dev);
1734 /* Use the now-standard shared IRQ implementation. */
1735 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1736 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1737 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1741 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1742 if (vortex_debug > 2)
1743 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1744 for (i = 0; i < RX_RING_SIZE; i++) {
1745 struct sk_buff *skb;
1746 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1747 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1748 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1749 skb = dev_alloc_skb(PKT_BUF_SZ);
1750 vp->rx_skbuff[i] = skb;
1752 break; /* Bad news! */
1753 skb->dev = dev; /* Mark as being used by this device. */
1754 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1755 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->tail, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1757 if (i != RX_RING_SIZE) {
1759 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1760 for (j = 0; j < i; j++) {
1761 if (vp->rx_skbuff[j]) {
1762 dev_kfree_skb(vp->rx_skbuff[j]);
1763 vp->rx_skbuff[j] = NULL;
1769 /* Wrap the ring. */
1770 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1777 free_irq(dev->irq, dev);
1779 if (vortex_debug > 1)
1780 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1785 vortex_timer(unsigned long data)
1787 struct net_device *dev = (struct net_device *)data;
1788 struct vortex_private *vp = netdev_priv(dev);
1789 long ioaddr = dev->base_addr;
1790 int next_tick = 10*HZ;
1792 int media_status, mii_status, old_window;
1794 if (vortex_debug > 2) {
1795 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1796 dev->name, media_tbl[dev->if_port].name);
1797 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1801 goto leave_media_alone;
1802 disable_irq(dev->irq);
1803 old_window = inw(ioaddr + EL3_CMD) >> 13;
1805 media_status = inw(ioaddr + Wn4_Media);
1806 switch (dev->if_port) {
1807 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1808 if (media_status & Media_LnkBeat) {
1809 netif_carrier_on(dev);
1811 if (vortex_debug > 1)
1812 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1813 dev->name, media_tbl[dev->if_port].name, media_status);
1815 netif_carrier_off(dev);
1816 if (vortex_debug > 1) {
1817 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1818 dev->name, media_tbl[dev->if_port].name, media_status);
1822 case XCVR_MII: case XCVR_NWAY:
1824 mii_status = mdio_read(dev, vp->phys[0], 1);
1826 if (vortex_debug > 2)
1827 printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n",
1828 dev->name, mii_status);
1829 if (mii_status & BMSR_LSTATUS) {
1830 int mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1831 if (! vp->force_fd && mii_reg5 != 0xffff) {
1834 mii_reg5 &= vp->advertising;
1835 duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
1836 if (vp->full_duplex != duplex) {
1837 vp->full_duplex = duplex;
1838 printk(KERN_INFO "%s: Setting %s-duplex based on MII "
1839 "#%d link partner capability of %4.4x.\n",
1840 dev->name, vp->full_duplex ? "full" : "half",
1841 vp->phys[0], mii_reg5);
1842 /* Set the full-duplex bit. */
1844 outw( (vp->full_duplex ? 0x20 : 0) |
1845 (dev->mtu > 1500 ? 0x40 : 0) |
1846 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1847 ioaddr + Wn3_MAC_Ctrl);
1848 if (vortex_debug > 1)
1849 printk(KERN_DEBUG "Setting duplex in Wn3_MAC_Ctrl\n");
1850 /* AKPM: bug: should reset Tx and Rx after setting Duplex. Page 180 */
1853 netif_carrier_on(dev);
1855 netif_carrier_off(dev);
1859 default: /* Other media types handled by Tx timeouts. */
1860 if (vortex_debug > 1)
1861 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1862 dev->name, media_tbl[dev->if_port].name, media_status);
1866 unsigned int config;
1869 dev->if_port = media_tbl[dev->if_port].next;
1870 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1871 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1872 dev->if_port = vp->default_media;
1873 if (vortex_debug > 1)
1874 printk(KERN_DEBUG "%s: Media selection failing, using default "
1876 dev->name, media_tbl[dev->if_port].name);
1878 if (vortex_debug > 1)
1879 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1881 dev->name, media_tbl[dev->if_port].name);
1882 next_tick = media_tbl[dev->if_port].wait;
1884 outw((media_status & ~(Media_10TP|Media_SQE)) |
1885 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1888 config = inl(ioaddr + Wn3_Config);
1889 config = BFINS(config, dev->if_port, 20, 4);
1890 outl(config, ioaddr + Wn3_Config);
1892 outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1894 if (vortex_debug > 1)
1895 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1896 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1898 EL3WINDOW(old_window);
1899 enable_irq(dev->irq);
1902 if (vortex_debug > 2)
1903 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1904 dev->name, media_tbl[dev->if_port].name);
1906 mod_timer(&vp->timer, RUN_AT(next_tick));
1908 outw(FakeIntr, ioaddr + EL3_CMD);
1912 static void vortex_tx_timeout(struct net_device *dev)
1914 struct vortex_private *vp = netdev_priv(dev);
1915 long ioaddr = dev->base_addr;
1917 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1918 dev->name, inb(ioaddr + TxStatus),
1919 inw(ioaddr + EL3_STATUS));
1921 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1922 inw(ioaddr + Wn4_NetDiag),
1923 inw(ioaddr + Wn4_Media),
1924 inl(ioaddr + PktStatus),
1925 inw(ioaddr + Wn4_FIFODiag));
1926 /* Slight code bloat to be user friendly. */
1927 if ((inb(ioaddr + TxStatus) & 0x88) == 0x88)
1928 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1929 " network cable problem?\n", dev->name);
1930 if (inw(ioaddr + EL3_STATUS) & IntLatch) {
1931 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1932 " IRQ blocked by another device?\n", dev->name);
1933 /* Bad idea here.. but we might as well handle a few events. */
1936 * Block interrupts because vortex_interrupt does a bare spin_lock()
1938 unsigned long flags;
1939 local_irq_save(flags);
1940 if (vp->full_bus_master_tx)
1941 boomerang_interrupt(dev->irq, dev, NULL);
1943 vortex_interrupt(dev->irq, dev, NULL);
1944 local_irq_restore(flags);
1948 if (vortex_debug > 0)
1951 issue_and_wait(dev, TxReset);
1953 vp->stats.tx_errors++;
1954 if (vp->full_bus_master_tx) {
1955 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
1956 if (vp->cur_tx - vp->dirty_tx > 0 && inl(ioaddr + DownListPtr) == 0)
1957 outl(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1958 ioaddr + DownListPtr);
1959 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1960 netif_wake_queue (dev);
1961 if (vp->drv_flags & IS_BOOMERANG)
1962 outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1963 outw(DownUnstall, ioaddr + EL3_CMD);
1965 vp->stats.tx_dropped++;
1966 netif_wake_queue(dev);
1969 /* Issue Tx Enable */
1970 outw(TxEnable, ioaddr + EL3_CMD);
1971 dev->trans_start = jiffies;
1973 /* Switch to register set 7 for normal use. */
1978 * Handle uncommon interrupt sources. This is a separate routine to minimize
1982 vortex_error(struct net_device *dev, int status)
1984 struct vortex_private *vp = netdev_priv(dev);
1985 long ioaddr = dev->base_addr;
1986 int do_tx_reset = 0, reset_mask = 0;
1987 unsigned char tx_status = 0;
1989 if (vortex_debug > 2) {
1990 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1993 if (status & TxComplete) { /* Really "TxError" for us. */
1994 tx_status = inb(ioaddr + TxStatus);
1995 /* Presumably a tx-timeout. We must merely re-enable. */
1996 if (vortex_debug > 2
1997 || (tx_status != 0x88 && vortex_debug > 0)) {
1998 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1999 dev->name, tx_status);
2000 if (tx_status == 0x82) {
2001 printk(KERN_ERR "Probably a duplex mismatch. See "
2002 "Documentation/networking/vortex.txt\n");
2006 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2007 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2008 outb(0, ioaddr + TxStatus);
2009 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2011 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
2013 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2014 } else { /* Merely re-enable the transmitter. */
2015 outw(TxEnable, ioaddr + EL3_CMD);
2019 if (status & RxEarly) { /* Rx early is unused. */
2021 outw(AckIntr | RxEarly, ioaddr + EL3_CMD);
2023 if (status & StatsFull) { /* Empty statistics. */
2024 static int DoneDidThat;
2025 if (vortex_debug > 4)
2026 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2027 update_stats(ioaddr, dev);
2028 /* HACK: Disable statistics as an interrupt source. */
2029 /* This occurs when we have the wrong media type! */
2030 if (DoneDidThat == 0 &&
2031 inw(ioaddr + EL3_STATUS) & StatsFull) {
2032 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2033 "stats as an interrupt source.\n", dev->name);
2035 outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
2036 vp->intr_enable &= ~StatsFull;
2041 if (status & IntReq) { /* Restore all interrupt sources. */
2042 outw(vp->status_enable, ioaddr + EL3_CMD);
2043 outw(vp->intr_enable, ioaddr + EL3_CMD);
2045 if (status & HostError) {
2048 fifo_diag = inw(ioaddr + Wn4_FIFODiag);
2049 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2050 dev->name, fifo_diag);
2051 /* Adapter failure requires Tx/Rx reset and reinit. */
2052 if (vp->full_bus_master_tx) {
2053 int bus_status = inl(ioaddr + PktStatus);
2054 /* 0x80000000 PCI master abort. */
2055 /* 0x40000000 PCI target abort. */
2057 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2059 /* In this case, blow the card away */
2060 /* Must not enter D3 or we can't legally issue the reset! */
2061 vortex_down(dev, 0);
2062 issue_and_wait(dev, TotalReset | 0xff);
2063 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2064 } else if (fifo_diag & 0x0400)
2066 if (fifo_diag & 0x3000) {
2067 /* Reset Rx fifo and upload logic */
2068 issue_and_wait(dev, RxReset|0x07);
2069 /* Set the Rx filter to the current state. */
2071 outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2072 outw(AckIntr | HostError, ioaddr + EL3_CMD);
2077 issue_and_wait(dev, TxReset|reset_mask);
2078 outw(TxEnable, ioaddr + EL3_CMD);
2079 if (!vp->full_bus_master_tx)
2080 netif_wake_queue(dev);
2085 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2087 struct vortex_private *vp = netdev_priv(dev);
2088 long ioaddr = dev->base_addr;
2090 /* Put out the doubleword header... */
2091 outl(skb->len, ioaddr + TX_FIFO);
2092 if (vp->bus_master) {
2093 /* Set the bus-master controller to transfer the packet. */
2094 int len = (skb->len + 3) & ~3;
2095 outl( vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2096 ioaddr + Wn7_MasterAddr);
2097 outw(len, ioaddr + Wn7_MasterLen);
2099 outw(StartDMADown, ioaddr + EL3_CMD);
2100 /* netif_wake_queue() will be called at the DMADone interrupt. */
2102 /* ... and the packet rounded to a doubleword. */
2103 outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2104 dev_kfree_skb (skb);
2105 if (inw(ioaddr + TxFree) > 1536) {
2106 netif_start_queue (dev); /* AKPM: redundant? */
2108 /* Interrupt us when the FIFO has room for max-sized packet. */
2109 netif_stop_queue(dev);
2110 outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2114 dev->trans_start = jiffies;
2116 /* Clear the Tx status stack. */
2121 while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) {
2122 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2123 if (vortex_debug > 2)
2124 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2125 dev->name, tx_status);
2126 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2127 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2128 if (tx_status & 0x30) {
2129 issue_and_wait(dev, TxReset);
2131 outw(TxEnable, ioaddr + EL3_CMD);
2133 outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2140 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2142 struct vortex_private *vp = netdev_priv(dev);
2143 long ioaddr = dev->base_addr;
2144 /* Calculate the next Tx descriptor entry. */
2145 int entry = vp->cur_tx % TX_RING_SIZE;
2146 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2147 unsigned long flags;
2149 if (vortex_debug > 6) {
2150 printk(KERN_DEBUG "boomerang_start_xmit()\n");
2151 if (vortex_debug > 3)
2152 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2153 dev->name, vp->cur_tx);
2156 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2157 if (vortex_debug > 0)
2158 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2160 netif_stop_queue(dev);
2164 vp->tx_skbuff[entry] = skb;
2166 vp->tx_ring[entry].next = 0;
2168 if (skb->ip_summed != CHECKSUM_HW)
2169 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2171 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2173 if (!skb_shinfo(skb)->nr_frags) {
2174 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2175 skb->len, PCI_DMA_TODEVICE));
2176 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2180 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2181 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2182 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2184 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2185 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2187 vp->tx_ring[entry].frag[i+1].addr =
2188 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2189 (void*)page_address(frag->page) + frag->page_offset,
2190 frag->size, PCI_DMA_TODEVICE));
2192 if (i == skb_shinfo(skb)->nr_frags-1)
2193 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2195 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2199 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2200 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2201 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2204 spin_lock_irqsave(&vp->lock, flags);
2205 /* Wait for the stall to complete. */
2206 issue_and_wait(dev, DownStall);
2207 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2208 if (inl(ioaddr + DownListPtr) == 0) {
2209 outl(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2210 vp->queued_packet++;
2214 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2215 netif_stop_queue (dev);
2216 } else { /* Clear previous interrupt enable. */
2217 #if defined(tx_interrupt_mitigation)
2218 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2219 * were selected, this would corrupt DN_COMPLETE. No?
2221 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2224 outw(DownUnstall, ioaddr + EL3_CMD);
2225 spin_unlock_irqrestore(&vp->lock, flags);
2226 dev->trans_start = jiffies;
2230 /* The interrupt handler does all of the Rx thread work and cleans up
2231 after the Tx thread. */
2234 * This is the ISR for the vortex series chips.
2235 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2239 vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2241 struct net_device *dev = dev_id;
2242 struct vortex_private *vp = netdev_priv(dev);
2245 int work_done = max_interrupt_work;
2248 ioaddr = dev->base_addr;
2249 spin_lock(&vp->lock);
2251 status = inw(ioaddr + EL3_STATUS);
2253 if (vortex_debug > 6)
2254 printk("vortex_interrupt(). status=0x%4x\n", status);
2256 if ((status & IntLatch) == 0)
2257 goto handler_exit; /* No interrupt: shared IRQs cause this */
2260 if (status & IntReq) {
2261 status |= vp->deferred;
2265 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2268 if (vortex_debug > 4)
2269 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2270 dev->name, status, inb(ioaddr + Timer));
2273 if (vortex_debug > 5)
2274 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2276 if (status & RxComplete)
2279 if (status & TxAvailable) {
2280 if (vortex_debug > 5)
2281 printk(KERN_DEBUG " TX room bit was handled.\n");
2282 /* There's room in the FIFO for a full-sized packet. */
2283 outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2284 netif_wake_queue (dev);
2287 if (status & DMADone) {
2288 if (inw(ioaddr + Wn7_MasterStatus) & 0x1000) {
2289 outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2290 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2291 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2292 if (inw(ioaddr + TxFree) > 1536) {
2294 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2295 * insufficient FIFO room, the TxAvailable test will succeed and call
2296 * netif_wake_queue()
2298 netif_wake_queue(dev);
2299 } else { /* Interrupt when FIFO has room for max-sized packet. */
2300 outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2301 netif_stop_queue(dev);
2305 /* Check for all uncommon interrupts at once. */
2306 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2307 if (status == 0xffff)
2309 vortex_error(dev, status);
2312 if (--work_done < 0) {
2313 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2314 "%4.4x.\n", dev->name, status);
2315 /* Disable all pending interrupts. */
2317 vp->deferred |= status;
2318 outw(SetStatusEnb | (~vp->deferred & vp->status_enable),
2320 outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2321 } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch);
2322 /* The timer will reenable interrupts. */
2323 mod_timer(&vp->timer, jiffies + 1*HZ);
2326 /* Acknowledge the IRQ. */
2327 outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2328 } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2330 if (vortex_debug > 4)
2331 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2334 spin_unlock(&vp->lock);
2335 return IRQ_RETVAL(handled);
2339 * This is the ISR for the boomerang series chips.
2340 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2344 boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2346 struct net_device *dev = dev_id;
2347 struct vortex_private *vp = netdev_priv(dev);
2350 int work_done = max_interrupt_work;
2352 ioaddr = dev->base_addr;
2355 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2356 * and boomerang_start_xmit
2358 spin_lock(&vp->lock);
2360 status = inw(ioaddr + EL3_STATUS);
2362 if (vortex_debug > 6)
2363 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2365 if ((status & IntLatch) == 0)
2366 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2368 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2369 if (vortex_debug > 1)
2370 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2374 if (status & IntReq) {
2375 status |= vp->deferred;
2379 if (vortex_debug > 4)
2380 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2381 dev->name, status, inb(ioaddr + Timer));
2383 if (vortex_debug > 5)
2384 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2386 if (status & UpComplete) {
2387 outw(AckIntr | UpComplete, ioaddr + EL3_CMD);
2388 if (vortex_debug > 5)
2389 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2393 if (status & DownComplete) {
2394 unsigned int dirty_tx = vp->dirty_tx;
2396 outw(AckIntr | DownComplete, ioaddr + EL3_CMD);
2397 while (vp->cur_tx - dirty_tx > 0) {
2398 int entry = dirty_tx % TX_RING_SIZE;
2399 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2400 if (inl(ioaddr + DownListPtr) ==
2401 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2402 break; /* It still hasn't been processed. */
2404 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2405 break; /* It still hasn't been processed. */
2408 if (vp->tx_skbuff[entry]) {
2409 struct sk_buff *skb = vp->tx_skbuff[entry];
2412 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2413 pci_unmap_single(VORTEX_PCI(vp),
2414 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2415 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2418 pci_unmap_single(VORTEX_PCI(vp),
2419 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2421 dev_kfree_skb_irq(skb);
2422 vp->tx_skbuff[entry] = NULL;
2424 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2426 /* vp->stats.tx_packets++; Counted below. */
2429 vp->dirty_tx = dirty_tx;
2430 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2431 if (vortex_debug > 6)
2432 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2433 netif_wake_queue (dev);
2437 /* Check for all uncommon interrupts at once. */
2438 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2439 vortex_error(dev, status);
2441 if (--work_done < 0) {
2442 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2443 "%4.4x.\n", dev->name, status);
2444 /* Disable all pending interrupts. */
2446 vp->deferred |= status;
2447 outw(SetStatusEnb | (~vp->deferred & vp->status_enable),
2449 outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2450 } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch);
2451 /* The timer will reenable interrupts. */
2452 mod_timer(&vp->timer, jiffies + 1*HZ);
2455 /* Acknowledge the IRQ. */
2456 outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2457 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2458 writel(0x8000, vp->cb_fn_base + 4);
2460 } while ((status = inw(ioaddr + EL3_STATUS)) & IntLatch);
2462 if (vortex_debug > 4)
2463 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2466 spin_unlock(&vp->lock);
2470 static int vortex_rx(struct net_device *dev)
2472 struct vortex_private *vp = netdev_priv(dev);
2473 long ioaddr = dev->base_addr;
2477 if (vortex_debug > 5)
2478 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2479 inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus));
2480 while ((rx_status = inw(ioaddr + RxStatus)) > 0) {
2481 if (rx_status & 0x4000) { /* Error, update stats. */
2482 unsigned char rx_error = inb(ioaddr + RxErrors);
2483 if (vortex_debug > 2)
2484 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2485 vp->stats.rx_errors++;
2486 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2487 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2488 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2489 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2490 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2492 /* The packet length: up to 4.5K!. */
2493 int pkt_len = rx_status & 0x1fff;
2494 struct sk_buff *skb;
2496 skb = dev_alloc_skb(pkt_len + 5);
2497 if (vortex_debug > 4)
2498 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2499 pkt_len, rx_status);
2502 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2503 /* 'skb_put()' points to the start of sk_buff data area. */
2504 if (vp->bus_master &&
2505 ! (inw(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2506 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2507 pkt_len, PCI_DMA_FROMDEVICE);
2508 outl(dma, ioaddr + Wn7_MasterAddr);
2509 outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2510 outw(StartDMAUp, ioaddr + EL3_CMD);
2511 while (inw(ioaddr + Wn7_MasterStatus) & 0x8000)
2513 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2515 insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len),
2516 (pkt_len + 3) >> 2);
2518 outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2519 skb->protocol = eth_type_trans(skb, dev);
2521 dev->last_rx = jiffies;
2522 vp->stats.rx_packets++;
2523 /* Wait a limited time to go to next packet. */
2524 for (i = 200; i >= 0; i--)
2525 if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
2528 } else if (vortex_debug > 0)
2529 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2530 "size %d.\n", dev->name, pkt_len);
2532 vp->stats.rx_dropped++;
2533 issue_and_wait(dev, RxDiscard);
2540 boomerang_rx(struct net_device *dev)
2542 struct vortex_private *vp = netdev_priv(dev);
2543 int entry = vp->cur_rx % RX_RING_SIZE;
2544 long ioaddr = dev->base_addr;
2546 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2548 if (vortex_debug > 5)
2549 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", inw(ioaddr+EL3_STATUS));
2551 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2552 if (--rx_work_limit < 0)
2554 if (rx_status & RxDError) { /* Error, update stats. */
2555 unsigned char rx_error = rx_status >> 16;
2556 if (vortex_debug > 2)
2557 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2558 vp->stats.rx_errors++;
2559 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2560 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2561 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2562 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2563 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2565 /* The packet length: up to 4.5K!. */
2566 int pkt_len = rx_status & 0x1fff;
2567 struct sk_buff *skb;
2568 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2570 if (vortex_debug > 4)
2571 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2572 pkt_len, rx_status);
2574 /* Check if the packet is long enough to just accept without
2575 copying to a properly sized skbuff. */
2576 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2578 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2579 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2580 /* 'skb_put()' points to the start of sk_buff data area. */
2581 memcpy(skb_put(skb, pkt_len),
2582 vp->rx_skbuff[entry]->tail,
2584 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2587 /* Pass up the skbuff already on the Rx ring. */
2588 skb = vp->rx_skbuff[entry];
2589 vp->rx_skbuff[entry] = NULL;
2590 skb_put(skb, pkt_len);
2591 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2594 skb->protocol = eth_type_trans(skb, dev);
2595 { /* Use hardware checksum info. */
2596 int csum_bits = rx_status & 0xee000000;
2598 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2599 csum_bits == (IPChksumValid | UDPChksumValid))) {
2600 skb->ip_summed = CHECKSUM_UNNECESSARY;
2605 dev->last_rx = jiffies;
2606 vp->stats.rx_packets++;
2608 entry = (++vp->cur_rx) % RX_RING_SIZE;
2610 /* Refill the Rx ring buffers. */
2611 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2612 struct sk_buff *skb;
2613 entry = vp->dirty_rx % RX_RING_SIZE;
2614 if (vp->rx_skbuff[entry] == NULL) {
2615 skb = dev_alloc_skb(PKT_BUF_SZ);
2617 static unsigned long last_jif;
2618 if ((jiffies - last_jif) > 10 * HZ) {
2619 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2622 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2623 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2624 break; /* Bad news! */
2626 skb->dev = dev; /* Mark as being used by this device. */
2627 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2628 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->tail, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2629 vp->rx_skbuff[entry] = skb;
2631 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2632 outw(UpUnstall, ioaddr + EL3_CMD);
2638 * If we've hit a total OOM refilling the Rx ring we poll once a second
2639 * for some memory. Otherwise there is no way to restart the rx process.
2642 rx_oom_timer(unsigned long arg)
2644 struct net_device *dev = (struct net_device *)arg;
2645 struct vortex_private *vp = netdev_priv(dev);
2647 spin_lock_irq(&vp->lock);
2648 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2650 if (vortex_debug > 1) {
2651 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2652 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2654 spin_unlock_irq(&vp->lock);
2658 vortex_down(struct net_device *dev, int final_down)
2660 struct vortex_private *vp = netdev_priv(dev);
2661 long ioaddr = dev->base_addr;
2663 netif_stop_queue (dev);
2665 del_timer_sync(&vp->rx_oom_timer);
2666 del_timer_sync(&vp->timer);
2668 /* Turn off statistics ASAP. We update vp->stats below. */
2669 outw(StatsDisable, ioaddr + EL3_CMD);
2671 /* Disable the receiver and transmitter. */
2672 outw(RxDisable, ioaddr + EL3_CMD);
2673 outw(TxDisable, ioaddr + EL3_CMD);
2675 if (dev->if_port == XCVR_10base2)
2676 /* Turn off thinnet power. Green! */
2677 outw(StopCoax, ioaddr + EL3_CMD);
2679 outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2681 update_stats(ioaddr, dev);
2682 if (vp->full_bus_master_rx)
2683 outl(0, ioaddr + UpListPtr);
2684 if (vp->full_bus_master_tx)
2685 outl(0, ioaddr + DownListPtr);
2687 if (final_down && VORTEX_PCI(vp) && vp->enable_wol) {
2688 pci_save_state(VORTEX_PCI(vp), vp->power_state);
2694 vortex_close(struct net_device *dev)
2696 struct vortex_private *vp = netdev_priv(dev);
2697 long ioaddr = dev->base_addr;
2700 if (netif_device_present(dev))
2701 vortex_down(dev, 1);
2703 if (vortex_debug > 1) {
2704 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2705 dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus));
2706 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2707 " tx_queued %d Rx pre-checksummed %d.\n",
2708 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2712 if ( vp->rx_csumhits &&
2713 ((vp->drv_flags & HAS_HWCKSM) == 0) &&
2714 (hw_checksums[vp->card_idx] == -1)) {
2715 printk(KERN_WARNING "%s supports hardware checksums, and we're not using them!\n", dev->name);
2719 free_irq(dev->irq, dev);
2721 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2722 for (i = 0; i < RX_RING_SIZE; i++)
2723 if (vp->rx_skbuff[i]) {
2724 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2725 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2726 dev_kfree_skb(vp->rx_skbuff[i]);
2727 vp->rx_skbuff[i] = NULL;
2730 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2731 for (i = 0; i < TX_RING_SIZE; i++) {
2732 if (vp->tx_skbuff[i]) {
2733 struct sk_buff *skb = vp->tx_skbuff[i];
2737 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2738 pci_unmap_single(VORTEX_PCI(vp),
2739 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2740 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2743 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2746 vp->tx_skbuff[i] = NULL;
2755 dump_tx_ring(struct net_device *dev)
2757 if (vortex_debug > 0) {
2758 struct vortex_private *vp = netdev_priv(dev);
2759 long ioaddr = dev->base_addr;
2761 if (vp->full_bus_master_tx) {
2763 int stalled = inl(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2765 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2766 vp->full_bus_master_tx,
2767 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2768 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2769 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2770 inl(ioaddr + DownListPtr),
2771 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2772 issue_and_wait(dev, DownStall);
2773 for (i = 0; i < TX_RING_SIZE; i++) {
2774 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2777 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2779 le32_to_cpu(vp->tx_ring[i].length),
2781 le32_to_cpu(vp->tx_ring[i].status));
2784 outw(DownUnstall, ioaddr + EL3_CMD);
2789 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2791 struct vortex_private *vp = netdev_priv(dev);
2792 unsigned long flags;
2794 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2795 spin_lock_irqsave (&vp->lock, flags);
2796 update_stats(dev->base_addr, dev);
2797 spin_unlock_irqrestore (&vp->lock, flags);
2802 /* Update statistics.
2803 Unlike with the EL3 we need not worry about interrupts changing
2804 the window setting from underneath us, but we must still guard
2805 against a race condition with a StatsUpdate interrupt updating the
2806 table. This is done by checking that the ASM (!) code generated uses
2807 atomic updates with '+='.
2809 static void update_stats(long ioaddr, struct net_device *dev)
2811 struct vortex_private *vp = netdev_priv(dev);
2812 int old_window = inw(ioaddr + EL3_CMD);
2814 if (old_window == 0xffff) /* Chip suspended or ejected. */
2816 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2817 /* Switch to the stats window, and read everything. */
2819 vp->stats.tx_carrier_errors += inb(ioaddr + 0);
2820 vp->stats.tx_heartbeat_errors += inb(ioaddr + 1);
2821 /* Multiple collisions. */ inb(ioaddr + 2);
2822 vp->stats.collisions += inb(ioaddr + 3);
2823 vp->stats.tx_window_errors += inb(ioaddr + 4);
2824 vp->stats.rx_fifo_errors += inb(ioaddr + 5);
2825 vp->stats.tx_packets += inb(ioaddr + 6);
2826 vp->stats.tx_packets += (inb(ioaddr + 9)&0x30) << 4;
2827 /* Rx packets */ inb(ioaddr + 7); /* Must read to clear */
2828 /* Tx deferrals */ inb(ioaddr + 8);
2829 /* Don't bother with register 9, an extension of registers 6&7.
2830 If we do use the 6&7 values the atomic update assumption above
2832 vp->stats.rx_bytes += inw(ioaddr + 10);
2833 vp->stats.tx_bytes += inw(ioaddr + 12);
2834 /* New: On the Vortex we must also clear the BadSSD counter. */
2839 u8 up = inb(ioaddr + 13);
2840 vp->stats.rx_bytes += (up & 0x0f) << 16;
2841 vp->stats.tx_bytes += (up & 0xf0) << 12;
2844 EL3WINDOW(old_window >> 13);
2849 static void vortex_get_drvinfo(struct net_device *dev,
2850 struct ethtool_drvinfo *info)
2852 struct vortex_private *vp = netdev_priv(dev);
2854 strcpy(info->driver, DRV_NAME);
2855 strcpy(info->version, DRV_VERSION);
2856 if (VORTEX_PCI(vp)) {
2857 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2859 if (VORTEX_EISA(vp))
2860 sprintf(info->bus_info, vp->gendev->bus_id);
2862 sprintf(info->bus_info, "EISA 0x%lx %d",
2863 dev->base_addr, dev->irq);
2867 static struct ethtool_ops vortex_ethtool_ops = {
2868 .get_drvinfo = vortex_get_drvinfo,
2871 static int vortex_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2873 struct vortex_private *vp = netdev_priv(dev);
2874 long ioaddr = dev->base_addr;
2875 struct mii_ioctl_data *data = if_mii(rq);
2876 int phy = vp->phys[0] & 0x1f;
2880 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2883 case SIOCGMIIREG: /* Read MII PHY register. */
2885 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
2889 case SIOCSMIIREG: /* Write MII PHY register. */
2890 if (!capable(CAP_NET_ADMIN)) {
2894 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2899 retval = -EOPNOTSUPP;
2907 * Must power the device up to do MDIO operations
2909 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2912 struct vortex_private *vp = netdev_priv(dev);
2916 state = VORTEX_PCI(vp)->current_state;
2918 /* The kernel core really should have pci_get_power_state() */
2921 pci_set_power_state(VORTEX_PCI(vp), 0);
2922 err = vortex_do_ioctl(dev, rq, cmd);
2924 pci_set_power_state(VORTEX_PCI(vp), state);
2930 /* Pre-Cyclone chips have no documented multicast filter, so the only
2931 multicast setting is to receive all multicast frames. At least
2932 the chip has a very clean way to set the mode, unlike many others. */
2933 static void set_rx_mode(struct net_device *dev)
2935 long ioaddr = dev->base_addr;
2938 if (dev->flags & IFF_PROMISC) {
2939 if (vortex_debug > 0)
2940 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2941 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2942 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2943 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2945 new_mode = SetRxFilter | RxStation | RxBroadcast;
2947 outw(new_mode, ioaddr + EL3_CMD);
2950 /* MII transceiver control section.
2951 Read and write the MII registers using software-generated serial
2952 MDIO protocol. See the MII specifications or DP83840A data sheet
2955 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
2956 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
2957 "overclocking" issues. */
2958 #define mdio_delay() inl(mdio_addr)
2960 #define MDIO_SHIFT_CLK 0x01
2961 #define MDIO_DIR_WRITE 0x04
2962 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
2963 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
2964 #define MDIO_DATA_READ 0x02
2965 #define MDIO_ENB_IN 0x00
2967 /* Generate the preamble required for initial synchronization and
2968 a few older transceivers. */
2969 static void mdio_sync(long ioaddr, int bits)
2971 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2973 /* Establish sync by sending at least 32 logic ones. */
2974 while (-- bits >= 0) {
2975 outw(MDIO_DATA_WRITE1, mdio_addr);
2977 outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
2982 static int mdio_read(struct net_device *dev, int phy_id, int location)
2984 struct vortex_private *vp = netdev_priv(dev);
2986 long ioaddr = dev->base_addr;
2987 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
2988 unsigned int retval = 0;
2989 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2991 spin_lock_bh(&vp->mdio_lock);
2993 if (mii_preamble_required)
2994 mdio_sync(ioaddr, 32);
2996 /* Shift the read command bits out. */
2997 for (i = 14; i >= 0; i--) {
2998 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
2999 outw(dataval, mdio_addr);
3001 outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
3004 /* Read the two transition, 16 data, and wire-idle bits. */
3005 for (i = 19; i > 0; i--) {
3006 outw(MDIO_ENB_IN, mdio_addr);
3008 retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3009 outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3012 spin_unlock_bh(&vp->mdio_lock);
3013 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3016 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3018 struct vortex_private *vp = netdev_priv(dev);
3019 long ioaddr = dev->base_addr;
3020 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3021 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3024 spin_lock_bh(&vp->mdio_lock);
3026 if (mii_preamble_required)
3027 mdio_sync(ioaddr, 32);
3029 /* Shift the command bits out. */
3030 for (i = 31; i >= 0; i--) {
3031 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3032 outw(dataval, mdio_addr);
3034 outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
3037 /* Leave the interface idle. */
3038 for (i = 1; i >= 0; i--) {
3039 outw(MDIO_ENB_IN, mdio_addr);
3041 outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3044 spin_unlock_bh(&vp->mdio_lock);
3048 /* ACPI: Advanced Configuration and Power Interface. */
3049 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3050 static void acpi_set_WOL(struct net_device *dev)
3052 struct vortex_private *vp = netdev_priv(dev);
3053 long ioaddr = dev->base_addr;
3055 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3057 outw(2, ioaddr + 0x0c);
3058 /* The RxFilter must accept the WOL frames. */
3059 outw(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3060 outw(RxEnable, ioaddr + EL3_CMD);
3062 /* Change the power state to D3; RxEnable doesn't take effect. */
3063 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3064 pci_set_power_state(VORTEX_PCI(vp), 3);
3068 static void __devexit vortex_remove_one (struct pci_dev *pdev)
3070 struct net_device *dev = pci_get_drvdata(pdev);
3071 struct vortex_private *vp;
3074 printk("vortex_remove_one called for Compaq device!\n");
3078 vp = netdev_priv(dev);
3080 /* AKPM: FIXME: we should have
3081 * if (vp->cb_fn_base) iounmap(vp->cb_fn_base);
3084 unregister_netdev(dev);
3086 if (VORTEX_PCI(vp) && vp->enable_wol) {
3087 pci_set_power_state(VORTEX_PCI(vp), 0); /* Go active */
3088 if (vp->pm_state_valid)
3089 pci_restore_state(VORTEX_PCI(vp), vp->power_state);
3091 /* Should really use issue_and_wait() here */
3092 outw(TotalReset|0x14, dev->base_addr + EL3_CMD);
3094 pci_free_consistent(pdev,
3095 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3096 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3099 if (vp->must_free_region)
3100 release_region(dev->base_addr, vp->io_size);
3105 static struct pci_driver vortex_driver = {
3107 .probe = vortex_init_one,
3108 .remove = __devexit_p(vortex_remove_one),
3109 .id_table = vortex_pci_tbl,
3111 .suspend = vortex_suspend,
3112 .resume = vortex_resume,
3117 static int vortex_have_pci;
3118 static int vortex_have_eisa;
3121 static int __init vortex_init (void)
3123 int pci_rc, eisa_rc;
3125 pci_rc = pci_module_init(&vortex_driver);
3126 eisa_rc = vortex_eisa_init();
3129 vortex_have_pci = 1;
3131 vortex_have_eisa = 1;
3133 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3137 static void __exit vortex_eisa_cleanup (void)
3139 struct vortex_private *vp;
3143 /* Take care of the EISA devices */
3144 eisa_driver_unregister (&vortex_eisa_driver);
3147 if (compaq_net_device) {
3148 vp = compaq_net_device->priv;
3149 ioaddr = compaq_net_device->base_addr;
3151 unregister_netdev (compaq_net_device);
3152 outw (TotalReset, ioaddr + EL3_CMD);
3153 release_region (ioaddr, VORTEX_TOTAL_SIZE);
3155 free_netdev (compaq_net_device);
3160 static void __exit vortex_cleanup (void)
3162 if (vortex_have_pci)
3163 pci_unregister_driver (&vortex_driver);
3164 if (vortex_have_eisa)
3165 vortex_eisa_cleanup ();
3169 module_init(vortex_init);
3170 module_exit(vortex_cleanup);