1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/kernel.h>
58 #include <linux/compiler.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/delay.h>
64 #include <linux/ethtool.h>
65 #include <linux/mii.h>
66 #include <linux/if_vlan.h>
67 #include <linux/crc32.h>
70 #include <linux/tcp.h>
71 #include <linux/udp.h>
72 #include <linux/cache.h>
74 #include <asm/uaccess.h>
76 /* VLAN tagging feature enable/disable */
77 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
78 #define CP_VLAN_TAG_USED 1
79 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
80 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
82 #define CP_VLAN_TAG_USED 0
83 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
84 do { (tx_desc)->opts2 = 0; } while (0)
87 /* These identify the driver base version and may not be removed. */
88 static char version[] =
89 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
91 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
92 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
93 MODULE_LICENSE("GPL");
95 static int debug = -1;
96 MODULE_PARM (debug, "i");
97 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
99 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
100 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
101 static int multicast_filter_limit = 32;
102 MODULE_PARM (multicast_filter_limit, "i");
103 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
105 #define PFX DRV_NAME ": "
109 #define TRUE (!FALSE)
112 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
115 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
116 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
117 #define CP_REGS_SIZE (0xff + 1)
118 #define CP_REGS_VER 1 /* version 1 */
119 #define CP_RX_RING_SIZE 64
120 #define CP_TX_RING_SIZE 64
121 #define CP_RING_BYTES \
122 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
123 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
125 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
126 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
127 #define TX_BUFFS_AVAIL(CP) \
128 (((CP)->tx_tail <= (CP)->tx_head) ? \
129 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
130 (CP)->tx_tail - (CP)->tx_head - 1)
132 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
134 #define CP_INTERNAL_PHY 32
136 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
137 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
138 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
139 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
140 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
142 /* Time in jiffies before concluding the transmitter is hung. */
143 #define TX_TIMEOUT (6*HZ)
145 /* hardware minimum and maximum for a single frame's data payload */
146 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
147 #define CP_MAX_MTU 4096
150 /* NIC register offsets */
151 MAC0 = 0x00, /* Ethernet hardware address. */
152 MAR0 = 0x08, /* Multicast filter. */
153 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
154 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
155 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
156 Cmd = 0x37, /* Command register */
157 IntrMask = 0x3C, /* Interrupt mask */
158 IntrStatus = 0x3E, /* Interrupt status */
159 TxConfig = 0x40, /* Tx configuration */
160 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
161 RxConfig = 0x44, /* Rx configuration */
162 RxMissed = 0x4C, /* 24 bits valid, write clears */
163 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
164 Config1 = 0x52, /* Config1 */
165 Config3 = 0x59, /* Config3 */
166 Config4 = 0x5A, /* Config4 */
167 MultiIntr = 0x5C, /* Multiple interrupt select */
168 BasicModeCtrl = 0x62, /* MII BMCR */
169 BasicModeStatus = 0x64, /* MII BMSR */
170 NWayAdvert = 0x66, /* MII ADVERTISE */
171 NWayLPAR = 0x68, /* MII LPA */
172 NWayExpansion = 0x6A, /* MII Expansion */
173 Config5 = 0xD8, /* Config5 */
174 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
175 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
176 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
177 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
178 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
179 TxThresh = 0xEC, /* Early Tx threshold */
180 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
181 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
183 /* Tx and Rx status descriptors */
184 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
185 RingEnd = (1 << 30), /* End of descriptor ring */
186 FirstFrag = (1 << 29), /* First segment of a packet */
187 LastFrag = (1 << 28), /* Final segment of a packet */
188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
301 static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
317 struct cp_dma_stats {
331 } __attribute__((packed));
333 struct cp_extra_stats {
334 unsigned long rx_frags;
339 struct net_device *dev;
343 struct pci_dev *pdev;
347 struct net_device_stats net_stats;
348 struct cp_extra_stats cp_stats;
349 struct cp_dma_stats *nic_stats;
350 dma_addr_t nic_stats_dma;
352 unsigned rx_tail ____cacheline_aligned;
353 struct cp_desc *rx_ring;
354 struct ring_info rx_skb[CP_RX_RING_SIZE];
357 unsigned tx_head ____cacheline_aligned;
360 struct cp_desc *tx_ring;
361 struct ring_info tx_skb[CP_TX_RING_SIZE];
365 struct vlan_group *vlgrp;
368 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
371 struct mii_if_info mii_if;
374 #define cpr8(reg) readb(cp->regs + (reg))
375 #define cpr16(reg) readw(cp->regs + (reg))
376 #define cpr32(reg) readl(cp->regs + (reg))
377 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
378 #define cpw16(reg,val) writew((val), cp->regs + (reg))
379 #define cpw32(reg,val) writel((val), cp->regs + (reg))
380 #define cpw8_f(reg,val) do { \
381 writeb((val), cp->regs + (reg)); \
382 readb(cp->regs + (reg)); \
384 #define cpw16_f(reg,val) do { \
385 writew((val), cp->regs + (reg)); \
386 readw(cp->regs + (reg)); \
388 #define cpw32_f(reg,val) do { \
389 writel((val), cp->regs + (reg)); \
390 readl(cp->regs + (reg)); \
394 static void __cp_set_rx_mode (struct net_device *dev);
395 static void cp_tx (struct cp_private *cp);
396 static void cp_clean_rings (struct cp_private *cp);
398 static struct pci_device_id cp_pci_tbl[] = {
399 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
403 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
406 const char str[ETH_GSTRING_LEN];
407 } ethtool_stats_keys[] = {
426 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
428 struct cp_private *cp = netdev_priv(dev);
431 spin_lock_irqsave(&cp->lock, flags);
433 cp->cpcmd |= RxVlanOn;
434 cpw16(CpCmd, cp->cpcmd);
435 spin_unlock_irqrestore(&cp->lock, flags);
438 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
440 struct cp_private *cp = netdev_priv(dev);
443 spin_lock_irqsave(&cp->lock, flags);
444 cp->cpcmd &= ~RxVlanOn;
445 cpw16(CpCmd, cp->cpcmd);
447 cp->vlgrp->vlan_devices[vid] = NULL;
448 spin_unlock_irqrestore(&cp->lock, flags);
450 #endif /* CP_VLAN_TAG_USED */
452 static inline void cp_set_rxbufsize (struct cp_private *cp)
454 unsigned int mtu = cp->dev->mtu;
456 if (mtu > ETH_DATA_LEN)
457 /* MTU + ethernet header + FCS + optional VLAN tag */
458 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
460 cp->rx_buf_sz = PKT_BUF_SZ;
463 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
464 struct cp_desc *desc)
466 skb->protocol = eth_type_trans (skb, cp->dev);
468 cp->net_stats.rx_packets++;
469 cp->net_stats.rx_bytes += skb->len;
470 cp->dev->last_rx = jiffies;
473 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
474 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
475 be16_to_cpu(desc->opts2 & 0xffff));
478 netif_receive_skb(skb);
481 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
484 if (netif_msg_rx_err (cp))
486 "%s: rx err, slot %d status 0x%x len %d\n",
487 cp->dev->name, rx_tail, status, len);
488 cp->net_stats.rx_errors++;
489 if (status & RxErrFrame)
490 cp->net_stats.rx_frame_errors++;
491 if (status & RxErrCRC)
492 cp->net_stats.rx_crc_errors++;
493 if ((status & RxErrRunt) || (status & RxErrLong))
494 cp->net_stats.rx_length_errors++;
495 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
496 cp->net_stats.rx_length_errors++;
497 if (status & RxErrFIFO)
498 cp->net_stats.rx_fifo_errors++;
501 static inline unsigned int cp_rx_csum_ok (u32 status)
503 unsigned int protocol = (status >> 16) & 0x3;
505 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
507 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
509 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
514 static int cp_rx_poll (struct net_device *dev, int *budget)
516 struct cp_private *cp = netdev_priv(dev);
517 unsigned rx_tail = cp->rx_tail;
518 unsigned rx_work = dev->quota;
523 cpw16(IntrStatus, cp_rx_intr_mask);
528 struct sk_buff *skb, *new_skb;
529 struct cp_desc *desc;
532 skb = cp->rx_skb[rx_tail].skb;
536 desc = &cp->rx_ring[rx_tail];
537 status = le32_to_cpu(desc->opts1);
538 if (status & DescOwn)
541 len = (status & 0x1fff) - 4;
542 mapping = cp->rx_skb[rx_tail].mapping;
544 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
545 /* we don't support incoming fragmented frames.
546 * instead, we attempt to ensure that the
547 * pre-allocated RX skbs are properly sized such
548 * that RX fragments are never encountered
550 cp_rx_err_acct(cp, rx_tail, status, len);
551 cp->net_stats.rx_dropped++;
552 cp->cp_stats.rx_frags++;
556 if (status & (RxError | RxErrFIFO)) {
557 cp_rx_err_acct(cp, rx_tail, status, len);
561 if (netif_msg_rx_status(cp))
562 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
563 cp->dev->name, rx_tail, status, len);
565 buflen = cp->rx_buf_sz + RX_OFFSET;
566 new_skb = dev_alloc_skb (buflen);
568 cp->net_stats.rx_dropped++;
572 skb_reserve(new_skb, RX_OFFSET);
573 new_skb->dev = cp->dev;
575 pci_unmap_single(cp->pdev, mapping,
576 buflen, PCI_DMA_FROMDEVICE);
578 /* Handle checksum offloading for incoming packets. */
579 if (cp_rx_csum_ok(status))
580 skb->ip_summed = CHECKSUM_UNNECESSARY;
582 skb->ip_summed = CHECKSUM_NONE;
587 cp->rx_skb[rx_tail].mapping =
588 pci_map_single(cp->pdev, new_skb->tail,
589 buflen, PCI_DMA_FROMDEVICE);
590 cp->rx_skb[rx_tail].skb = new_skb;
592 cp_rx_skb(cp, skb, desc);
596 cp->rx_ring[rx_tail].opts2 = 0;
597 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
598 if (rx_tail == (CP_RX_RING_SIZE - 1))
599 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
602 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
603 rx_tail = NEXT_RX(rx_tail);
609 cp->rx_tail = rx_tail;
614 /* if we did not reach work limit, then we're done with
615 * this round of polling
618 if (cpr16(IntrStatus) & cp_rx_intr_mask)
622 cpw16_f(IntrMask, cp_intr_mask);
623 __netif_rx_complete(dev);
629 return 1; /* not done */
633 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
635 struct net_device *dev = dev_instance;
636 struct cp_private *cp;
639 if (unlikely(dev == NULL))
641 cp = netdev_priv(dev);
643 status = cpr16(IntrStatus);
644 if (!status || (status == 0xFFFF))
647 if (netif_msg_intr(cp))
648 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
649 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
651 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
653 spin_lock(&cp->lock);
655 /* close possible race's with dev_close */
656 if (unlikely(!netif_running(dev))) {
658 spin_unlock(&cp->lock);
662 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
663 if (netif_rx_schedule_prep(dev)) {
664 cpw16_f(IntrMask, cp_norx_intr_mask);
665 __netif_rx_schedule(dev);
668 if (status & (TxOK | TxErr | TxEmpty | SWInt))
670 if (status & LinkChg)
671 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
673 spin_unlock(&cp->lock);
675 if (status & PciErr) {
678 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
679 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
680 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
681 dev->name, status, pci_status);
683 /* TODO: reset hardware */
689 static void cp_tx (struct cp_private *cp)
691 unsigned tx_head = cp->tx_head;
692 unsigned tx_tail = cp->tx_tail;
694 while (tx_tail != tx_head) {
699 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
700 if (status & DescOwn)
703 skb = cp->tx_skb[tx_tail].skb;
707 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
708 skb->len, PCI_DMA_TODEVICE);
710 if (status & LastFrag) {
711 if (status & (TxError | TxFIFOUnder)) {
712 if (netif_msg_tx_err(cp))
713 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
714 cp->dev->name, status);
715 cp->net_stats.tx_errors++;
717 cp->net_stats.tx_window_errors++;
718 if (status & TxMaxCol)
719 cp->net_stats.tx_aborted_errors++;
720 if (status & TxLinkFail)
721 cp->net_stats.tx_carrier_errors++;
722 if (status & TxFIFOUnder)
723 cp->net_stats.tx_fifo_errors++;
725 cp->net_stats.collisions +=
726 ((status >> TxColCntShift) & TxColCntMask);
727 cp->net_stats.tx_packets++;
728 cp->net_stats.tx_bytes += skb->len;
729 if (netif_msg_tx_done(cp))
730 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
732 dev_kfree_skb_irq(skb);
735 cp->tx_skb[tx_tail].skb = NULL;
737 tx_tail = NEXT_TX(tx_tail);
740 cp->tx_tail = tx_tail;
742 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
743 netif_wake_queue(cp->dev);
746 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
748 struct cp_private *cp = netdev_priv(dev);
755 spin_lock_irq(&cp->lock);
757 /* This is a hard error, log it. */
758 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
759 netif_stop_queue(dev);
760 spin_unlock_irq(&cp->lock);
761 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
767 if (cp->vlgrp && vlan_tx_tag_present(skb))
768 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
772 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
773 if (skb_shinfo(skb)->nr_frags == 0) {
774 struct cp_desc *txd = &cp->tx_ring[entry];
779 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
780 CP_VLAN_TX_TAG(txd, vlan_tag);
781 txd->addr = cpu_to_le64(mapping);
784 if (skb->ip_summed == CHECKSUM_HW) {
785 const struct iphdr *ip = skb->nh.iph;
786 if (ip->protocol == IPPROTO_TCP)
787 txd->opts1 = cpu_to_le32(eor | len | DescOwn |
788 FirstFrag | LastFrag |
790 else if (ip->protocol == IPPROTO_UDP)
791 txd->opts1 = cpu_to_le32(eor | len | DescOwn |
792 FirstFrag | LastFrag |
797 txd->opts1 = cpu_to_le32(eor | len | DescOwn |
798 FirstFrag | LastFrag);
801 cp->tx_skb[entry].skb = skb;
802 cp->tx_skb[entry].mapping = mapping;
803 cp->tx_skb[entry].frag = 0;
804 entry = NEXT_TX(entry);
807 u32 first_len, first_eor;
808 dma_addr_t first_mapping;
809 int frag, first_entry = entry;
810 const struct iphdr *ip = skb->nh.iph;
812 /* We must give this initial chunk to the device last.
813 * Otherwise we could race with the device.
816 first_len = skb_headlen(skb);
817 first_mapping = pci_map_single(cp->pdev, skb->data,
818 first_len, PCI_DMA_TODEVICE);
819 cp->tx_skb[entry].skb = skb;
820 cp->tx_skb[entry].mapping = first_mapping;
821 cp->tx_skb[entry].frag = 1;
822 entry = NEXT_TX(entry);
824 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
825 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
830 len = this_frag->size;
831 mapping = pci_map_single(cp->pdev,
832 ((void *) page_address(this_frag->page) +
833 this_frag->page_offset),
834 len, PCI_DMA_TODEVICE);
835 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
837 if (skb->ip_summed == CHECKSUM_HW) {
838 ctrl = eor | len | DescOwn | IPCS;
839 if (ip->protocol == IPPROTO_TCP)
841 else if (ip->protocol == IPPROTO_UDP)
846 ctrl = eor | len | DescOwn;
848 if (frag == skb_shinfo(skb)->nr_frags - 1)
851 txd = &cp->tx_ring[entry];
852 CP_VLAN_TX_TAG(txd, vlan_tag);
853 txd->addr = cpu_to_le64(mapping);
856 txd->opts1 = cpu_to_le32(ctrl);
859 cp->tx_skb[entry].skb = skb;
860 cp->tx_skb[entry].mapping = mapping;
861 cp->tx_skb[entry].frag = frag + 2;
862 entry = NEXT_TX(entry);
865 txd = &cp->tx_ring[first_entry];
866 CP_VLAN_TX_TAG(txd, vlan_tag);
867 txd->addr = cpu_to_le64(first_mapping);
870 if (skb->ip_summed == CHECKSUM_HW) {
871 if (ip->protocol == IPPROTO_TCP)
872 txd->opts1 = cpu_to_le32(first_eor | first_len |
873 FirstFrag | DescOwn |
875 else if (ip->protocol == IPPROTO_UDP)
876 txd->opts1 = cpu_to_le32(first_eor | first_len |
877 FirstFrag | DescOwn |
882 txd->opts1 = cpu_to_le32(first_eor | first_len |
883 FirstFrag | DescOwn);
887 if (netif_msg_tx_queued(cp))
888 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
889 dev->name, entry, skb->len);
890 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
891 netif_stop_queue(dev);
893 spin_unlock_irq(&cp->lock);
895 cpw8(TxPoll, NormalTxPoll);
896 dev->trans_start = jiffies;
901 /* Set or clear the multicast filter for this adaptor.
902 This routine is not state sensitive and need not be SMP locked. */
904 static void __cp_set_rx_mode (struct net_device *dev)
906 struct cp_private *cp = netdev_priv(dev);
907 u32 mc_filter[2]; /* Multicast hash filter */
911 /* Note: do not reorder, GCC is clever about common statements. */
912 if (dev->flags & IFF_PROMISC) {
913 /* Unconditionally log net taps. */
914 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
917 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
919 mc_filter[1] = mc_filter[0] = 0xffffffff;
920 } else if ((dev->mc_count > multicast_filter_limit)
921 || (dev->flags & IFF_ALLMULTI)) {
922 /* Too many to filter perfectly -- accept all multicasts. */
923 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
924 mc_filter[1] = mc_filter[0] = 0xffffffff;
926 struct dev_mc_list *mclist;
927 rx_mode = AcceptBroadcast | AcceptMyPhys;
928 mc_filter[1] = mc_filter[0] = 0;
929 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
930 i++, mclist = mclist->next) {
931 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
933 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
934 rx_mode |= AcceptMulticast;
938 /* We can safely update without stopping the chip. */
939 tmp = cp_rx_config | rx_mode;
940 if (cp->rx_config != tmp) {
941 cpw32_f (RxConfig, tmp);
944 cpw32_f (MAR0 + 0, mc_filter[0]);
945 cpw32_f (MAR0 + 4, mc_filter[1]);
948 static void cp_set_rx_mode (struct net_device *dev)
951 struct cp_private *cp = netdev_priv(dev);
953 spin_lock_irqsave (&cp->lock, flags);
954 __cp_set_rx_mode(dev);
955 spin_unlock_irqrestore (&cp->lock, flags);
958 static void __cp_get_stats(struct cp_private *cp)
960 /* only lower 24 bits valid; write any value to clear */
961 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
965 static struct net_device_stats *cp_get_stats(struct net_device *dev)
967 struct cp_private *cp = netdev_priv(dev);
970 /* The chip only need report frame silently dropped. */
971 spin_lock_irqsave(&cp->lock, flags);
972 if (netif_running(dev) && netif_device_present(dev))
974 spin_unlock_irqrestore(&cp->lock, flags);
976 return &cp->net_stats;
979 static void cp_stop_hw (struct cp_private *cp)
981 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
982 cpw16_f(IntrMask, 0);
985 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
988 cp->tx_head = cp->tx_tail = 0;
991 static void cp_reset_hw (struct cp_private *cp)
993 unsigned work = 1000;
998 if (!(cpr8(Cmd) & CmdReset))
1001 set_current_state(TASK_UNINTERRUPTIBLE);
1002 schedule_timeout(10);
1005 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1008 static inline void cp_start_hw (struct cp_private *cp)
1010 cpw16(CpCmd, cp->cpcmd);
1011 cpw8(Cmd, RxOn | TxOn);
1014 static void cp_init_hw (struct cp_private *cp)
1016 struct net_device *dev = cp->dev;
1017 dma_addr_t ring_dma;
1021 cpw8_f (Cfg9346, Cfg9346_Unlock);
1023 /* Restore our idea of the MAC address. */
1024 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1025 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1028 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1030 __cp_set_rx_mode(dev);
1031 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1033 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1034 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1035 cpw8(Config3, PARMEnable);
1036 cp->wol_enabled = 0;
1038 cpw8(Config5, cpr8(Config5) & PMEStatus);
1040 cpw32_f(HiTxRingAddr, 0);
1041 cpw32_f(HiTxRingAddr + 4, 0);
1043 ring_dma = cp->ring_dma;
1044 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1045 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1047 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1048 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1049 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1051 cpw16(MultiIntr, 0);
1053 cpw16_f(IntrMask, cp_intr_mask);
1055 cpw8_f(Cfg9346, Cfg9346_Lock);
1058 static int cp_refill_rx (struct cp_private *cp)
1062 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1063 struct sk_buff *skb;
1065 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1070 skb_reserve(skb, RX_OFFSET);
1072 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1073 skb->tail, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1074 cp->rx_skb[i].skb = skb;
1075 cp->rx_skb[i].frag = 0;
1077 cp->rx_ring[i].opts2 = 0;
1078 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1079 if (i == (CP_RX_RING_SIZE - 1))
1080 cp->rx_ring[i].opts1 =
1081 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1083 cp->rx_ring[i].opts1 =
1084 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1094 static int cp_init_rings (struct cp_private *cp)
1096 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1097 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1100 cp->tx_head = cp->tx_tail = 0;
1102 return cp_refill_rx (cp);
1105 static int cp_alloc_rings (struct cp_private *cp)
1109 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1114 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1116 mem += (CP_RING_BYTES - CP_STATS_SIZE);
1117 cp->nic_stats = mem;
1118 cp->nic_stats_dma = cp->ring_dma + (CP_RING_BYTES - CP_STATS_SIZE);
1120 return cp_init_rings(cp);
1123 static void cp_clean_rings (struct cp_private *cp)
1127 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1128 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1130 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1131 if (cp->rx_skb[i].skb) {
1132 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1133 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1134 dev_kfree_skb(cp->rx_skb[i].skb);
1138 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1139 if (cp->tx_skb[i].skb) {
1140 struct sk_buff *skb = cp->tx_skb[i].skb;
1141 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1142 skb->len, PCI_DMA_TODEVICE);
1144 cp->net_stats.tx_dropped++;
1148 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1149 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1152 static void cp_free_rings (struct cp_private *cp)
1155 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1158 cp->nic_stats = NULL;
1161 static int cp_open (struct net_device *dev)
1163 struct cp_private *cp = netdev_priv(dev);
1166 if (netif_msg_ifup(cp))
1167 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1169 rc = cp_alloc_rings(cp);
1175 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1179 netif_carrier_off(dev);
1180 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1181 netif_start_queue(dev);
1191 static int cp_close (struct net_device *dev)
1193 struct cp_private *cp = netdev_priv(dev);
1194 unsigned long flags;
1196 if (netif_msg_ifdown(cp))
1197 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1199 spin_lock_irqsave(&cp->lock, flags);
1201 netif_stop_queue(dev);
1202 netif_carrier_off(dev);
1206 spin_unlock_irqrestore(&cp->lock, flags);
1208 synchronize_irq(dev->irq);
1209 free_irq(dev->irq, dev);
1216 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1218 struct cp_private *cp = netdev_priv(dev);
1220 unsigned long flags;
1222 /* check for invalid MTU, according to hardware limits */
1223 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1226 /* if network interface not up, no need for complexity */
1227 if (!netif_running(dev)) {
1229 cp_set_rxbufsize(cp); /* set new rx buf size */
1233 spin_lock_irqsave(&cp->lock, flags);
1235 cp_stop_hw(cp); /* stop h/w and free rings */
1239 cp_set_rxbufsize(cp); /* set new rx buf size */
1241 rc = cp_init_rings(cp); /* realloc and restart h/w */
1244 spin_unlock_irqrestore(&cp->lock, flags);
1250 static char mii_2_8139_map[8] = {
1261 static int mdio_read(struct net_device *dev, int phy_id, int location)
1263 struct cp_private *cp = netdev_priv(dev);
1265 return location < 8 && mii_2_8139_map[location] ?
1266 readw(cp->regs + mii_2_8139_map[location]) : 0;
1270 static void mdio_write(struct net_device *dev, int phy_id, int location,
1273 struct cp_private *cp = netdev_priv(dev);
1275 if (location == 0) {
1276 cpw8(Cfg9346, Cfg9346_Unlock);
1277 cpw16(BasicModeCtrl, value);
1278 cpw8(Cfg9346, Cfg9346_Lock);
1279 } else if (location < 8 && mii_2_8139_map[location])
1280 cpw16(mii_2_8139_map[location], value);
1283 /* Set the ethtool Wake-on-LAN settings */
1284 static int netdev_set_wol (struct cp_private *cp,
1285 const struct ethtool_wolinfo *wol)
1289 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1290 /* If WOL is being disabled, no need for complexity */
1292 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1293 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1296 cpw8 (Cfg9346, Cfg9346_Unlock);
1297 cpw8 (Config3, options);
1298 cpw8 (Cfg9346, Cfg9346_Lock);
1300 options = 0; /* Paranoia setting */
1301 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1302 /* If WOL is being disabled, no need for complexity */
1304 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1305 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1306 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1309 cpw8 (Config5, options);
1311 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1316 /* Get the ethtool Wake-on-LAN settings */
1317 static void netdev_get_wol (struct cp_private *cp,
1318 struct ethtool_wolinfo *wol)
1322 wol->wolopts = 0; /* Start from scratch */
1323 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1324 WAKE_MCAST | WAKE_UCAST;
1325 /* We don't need to go on if WOL is disabled */
1326 if (!cp->wol_enabled) return;
1328 options = cpr8 (Config3);
1329 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1330 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1332 options = 0; /* Paranoia setting */
1333 options = cpr8 (Config5);
1334 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1335 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1336 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1339 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1341 struct cp_private *cp = netdev_priv(dev);
1343 strcpy (info->driver, DRV_NAME);
1344 strcpy (info->version, DRV_VERSION);
1345 strcpy (info->bus_info, pci_name(cp->pdev));
1348 static int cp_get_regs_len(struct net_device *dev)
1350 return CP_REGS_SIZE;
1353 static int cp_get_stats_count (struct net_device *dev)
1355 return CP_NUM_STATS;
1358 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1360 struct cp_private *cp = netdev_priv(dev);
1362 unsigned long flags;
1364 spin_lock_irqsave(&cp->lock, flags);
1365 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1366 spin_unlock_irqrestore(&cp->lock, flags);
1371 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1373 struct cp_private *cp = netdev_priv(dev);
1375 unsigned long flags;
1377 spin_lock_irqsave(&cp->lock, flags);
1378 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1379 spin_unlock_irqrestore(&cp->lock, flags);
1384 static int cp_nway_reset(struct net_device *dev)
1386 struct cp_private *cp = netdev_priv(dev);
1387 return mii_nway_restart(&cp->mii_if);
1390 static u32 cp_get_msglevel(struct net_device *dev)
1392 struct cp_private *cp = netdev_priv(dev);
1393 return cp->msg_enable;
1396 static void cp_set_msglevel(struct net_device *dev, u32 value)
1398 struct cp_private *cp = netdev_priv(dev);
1399 cp->msg_enable = value;
1402 static u32 cp_get_rx_csum(struct net_device *dev)
1404 struct cp_private *cp = netdev_priv(dev);
1405 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1408 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1410 struct cp_private *cp = netdev_priv(dev);
1411 u16 cmd = cp->cpcmd, newcmd;
1418 newcmd &= ~RxChkSum;
1420 if (newcmd != cmd) {
1421 unsigned long flags;
1423 spin_lock_irqsave(&cp->lock, flags);
1425 cpw16_f(CpCmd, newcmd);
1426 spin_unlock_irqrestore(&cp->lock, flags);
1432 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1435 struct cp_private *cp = netdev_priv(dev);
1436 unsigned long flags;
1438 if (regs->len < CP_REGS_SIZE)
1439 return /* -EINVAL */;
1441 regs->version = CP_REGS_VER;
1443 spin_lock_irqsave(&cp->lock, flags);
1444 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1445 spin_unlock_irqrestore(&cp->lock, flags);
1448 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1450 struct cp_private *cp = netdev_priv(dev);
1451 unsigned long flags;
1453 spin_lock_irqsave (&cp->lock, flags);
1454 netdev_get_wol (cp, wol);
1455 spin_unlock_irqrestore (&cp->lock, flags);
1458 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1460 struct cp_private *cp = netdev_priv(dev);
1461 unsigned long flags;
1464 spin_lock_irqsave (&cp->lock, flags);
1465 rc = netdev_set_wol (cp, wol);
1466 spin_unlock_irqrestore (&cp->lock, flags);
1471 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1473 switch (stringset) {
1475 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1483 static void cp_get_ethtool_stats (struct net_device *dev,
1484 struct ethtool_stats *estats, u64 *tmp_stats)
1486 struct cp_private *cp = netdev_priv(dev);
1487 unsigned int work = 100;
1490 /* begin NIC statistics dump */
1491 cpw32(StatsAddr + 4, (cp->nic_stats_dma >> 16) >> 16);
1492 cpw32(StatsAddr, (cp->nic_stats_dma & 0xffffffff) | DumpStats);
1495 while (work-- > 0) {
1496 if ((cpr32(StatsAddr) & DumpStats) == 0)
1501 if (cpr32(StatsAddr) & DumpStats)
1505 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_ok);
1506 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok);
1507 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_err);
1508 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_err);
1509 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->rx_fifo);
1510 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->frame_align);
1511 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_1col);
1512 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_mcol);
1513 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_phys);
1514 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_bcast);
1515 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_ok_mcast);
1516 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_abort);
1517 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_underrun);
1518 tmp_stats[i++] = cp->cp_stats.rx_frags;
1519 if (i != CP_NUM_STATS)
1523 static struct ethtool_ops cp_ethtool_ops = {
1524 .get_drvinfo = cp_get_drvinfo,
1525 .get_regs_len = cp_get_regs_len,
1526 .get_stats_count = cp_get_stats_count,
1527 .get_settings = cp_get_settings,
1528 .set_settings = cp_set_settings,
1529 .nway_reset = cp_nway_reset,
1530 .get_link = ethtool_op_get_link,
1531 .get_msglevel = cp_get_msglevel,
1532 .set_msglevel = cp_set_msglevel,
1533 .get_rx_csum = cp_get_rx_csum,
1534 .set_rx_csum = cp_set_rx_csum,
1535 .get_tx_csum = ethtool_op_get_tx_csum,
1536 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1537 .get_sg = ethtool_op_get_sg,
1538 .set_sg = ethtool_op_set_sg,
1539 .get_regs = cp_get_regs,
1540 .get_wol = cp_get_wol,
1541 .set_wol = cp_set_wol,
1542 .get_strings = cp_get_strings,
1543 .get_ethtool_stats = cp_get_ethtool_stats,
1546 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1548 struct cp_private *cp = netdev_priv(dev);
1550 unsigned long flags;
1552 if (!netif_running(dev))
1555 spin_lock_irqsave(&cp->lock, flags);
1556 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1557 spin_unlock_irqrestore(&cp->lock, flags);
1561 /* Serial EEPROM section. */
1563 /* EEPROM_Ctrl bits. */
1564 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1565 #define EE_CS 0x08 /* EEPROM chip select. */
1566 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1567 #define EE_WRITE_0 0x00
1568 #define EE_WRITE_1 0x02
1569 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1570 #define EE_ENB (0x80 | EE_CS)
1572 /* Delay between EEPROM clock transitions.
1573 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1576 #define eeprom_delay() readl(ee_addr)
1578 /* The EEPROM commands include the alway-set leading bit. */
1579 #define EE_WRITE_CMD (5)
1580 #define EE_READ_CMD (6)
1581 #define EE_ERASE_CMD (7)
1583 static int read_eeprom (void *ioaddr, int location, int addr_len)
1586 unsigned retval = 0;
1587 void *ee_addr = ioaddr + Cfg9346;
1588 int read_cmd = location | (EE_READ_CMD << addr_len);
1590 writeb (EE_ENB & ~EE_CS, ee_addr);
1591 writeb (EE_ENB, ee_addr);
1594 /* Shift the read command bits out. */
1595 for (i = 4 + addr_len; i >= 0; i--) {
1596 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1597 writeb (EE_ENB | dataval, ee_addr);
1599 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1602 writeb (EE_ENB, ee_addr);
1605 for (i = 16; i > 0; i--) {
1606 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1609 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1611 writeb (EE_ENB, ee_addr);
1615 /* Terminate the EEPROM access. */
1616 writeb (~EE_CS, ee_addr);
1622 /* Put the board into D3cold state and wait for WakeUp signal */
1623 static void cp_set_d3_state (struct cp_private *cp)
1625 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1626 pci_set_power_state (cp->pdev, 3);
1629 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1631 struct net_device *dev;
1632 struct cp_private *cp;
1636 unsigned int addr_len, i, pci_using_dac;
1640 static int version_printed;
1641 if (version_printed++ == 0)
1642 printk("%s", version);
1645 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1647 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1648 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1649 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1650 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1651 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1655 dev = alloc_etherdev(sizeof(struct cp_private));
1658 SET_MODULE_OWNER(dev);
1659 SET_NETDEV_DEV(dev, &pdev->dev);
1661 cp = netdev_priv(dev);
1664 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1665 spin_lock_init (&cp->lock);
1666 cp->mii_if.dev = dev;
1667 cp->mii_if.mdio_read = mdio_read;
1668 cp->mii_if.mdio_write = mdio_write;
1669 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1670 cp->mii_if.phy_id_mask = 0x1f;
1671 cp->mii_if.reg_num_mask = 0x1f;
1672 cp_set_rxbufsize(cp);
1674 rc = pci_enable_device(pdev);
1678 rc = pci_set_mwi(pdev);
1680 goto err_out_disable;
1682 rc = pci_request_regions(pdev, DRV_NAME);
1686 pciaddr = pci_resource_start(pdev, 1);
1689 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1693 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1695 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1696 pci_resource_len(pdev, 1), pci_name(pdev));
1700 /* Configure DMA attributes. */
1701 if ((sizeof(dma_addr_t) > 32) &&
1702 !pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL) &&
1703 !pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
1708 rc = pci_set_dma_mask(pdev, 0xffffffffULL);
1710 printk(KERN_ERR PFX "No usable DMA configuration, "
1714 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffULL);
1716 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1722 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1723 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1725 regs = ioremap(pciaddr, CP_REGS_SIZE);
1728 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1729 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1732 dev->base_addr = (unsigned long) regs;
1737 /* read MAC address from EEPROM */
1738 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1739 for (i = 0; i < 3; i++)
1740 ((u16 *) (dev->dev_addr))[i] =
1741 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1743 dev->open = cp_open;
1744 dev->stop = cp_close;
1745 dev->set_multicast_list = cp_set_rx_mode;
1746 dev->hard_start_xmit = cp_start_xmit;
1747 dev->get_stats = cp_get_stats;
1748 dev->do_ioctl = cp_ioctl;
1749 dev->poll = cp_rx_poll;
1750 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1752 dev->change_mtu = cp_change_mtu;
1754 dev->ethtool_ops = &cp_ethtool_ops;
1756 dev->tx_timeout = cp_tx_timeout;
1757 dev->watchdog_timeo = TX_TIMEOUT;
1760 #if CP_VLAN_TAG_USED
1761 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1762 dev->vlan_rx_register = cp_vlan_rx_register;
1763 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1767 dev->features |= NETIF_F_HIGHDMA;
1769 dev->irq = pdev->irq;
1771 rc = register_netdev(dev);
1775 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1776 "%02x:%02x:%02x:%02x:%02x:%02x, "
1780 dev->dev_addr[0], dev->dev_addr[1],
1781 dev->dev_addr[2], dev->dev_addr[3],
1782 dev->dev_addr[4], dev->dev_addr[5],
1785 pci_set_drvdata(pdev, dev);
1787 /* enable busmastering and memory-write-invalidate */
1788 pci_set_master(pdev);
1790 if (cp->wol_enabled) cp_set_d3_state (cp);
1797 pci_release_regions(pdev);
1799 pci_clear_mwi(pdev);
1801 pci_disable_device(pdev);
1807 static void cp_remove_one (struct pci_dev *pdev)
1809 struct net_device *dev = pci_get_drvdata(pdev);
1810 struct cp_private *cp = netdev_priv(dev);
1814 unregister_netdev(dev);
1816 if (cp->wol_enabled) pci_set_power_state (pdev, 0);
1817 pci_release_regions(pdev);
1818 pci_clear_mwi(pdev);
1819 pci_disable_device(pdev);
1820 pci_set_drvdata(pdev, NULL);
1825 static int cp_suspend (struct pci_dev *pdev, u32 state)
1827 struct net_device *dev;
1828 struct cp_private *cp;
1829 unsigned long flags;
1831 dev = pci_get_drvdata (pdev);
1832 cp = netdev_priv(dev);
1834 if (!dev || !netif_running (dev)) return 0;
1836 netif_device_detach (dev);
1837 netif_stop_queue (dev);
1839 spin_lock_irqsave (&cp->lock, flags);
1841 /* Disable Rx and Tx */
1842 cpw16 (IntrMask, 0);
1843 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1845 spin_unlock_irqrestore (&cp->lock, flags);
1847 if (cp->pdev && cp->wol_enabled) {
1848 pci_save_state (cp->pdev, cp->power_state);
1849 cp_set_d3_state (cp);
1855 static int cp_resume (struct pci_dev *pdev)
1857 struct net_device *dev;
1858 struct cp_private *cp;
1860 dev = pci_get_drvdata (pdev);
1861 cp = netdev_priv(dev);
1863 netif_device_attach (dev);
1865 if (cp->pdev && cp->wol_enabled) {
1866 pci_set_power_state (cp->pdev, 0);
1867 pci_restore_state (cp->pdev, cp->power_state);
1871 netif_start_queue (dev);
1875 #endif /* CONFIG_PM */
1877 static struct pci_driver cp_driver = {
1879 .id_table = cp_pci_tbl,
1880 .probe = cp_init_one,
1881 .remove = cp_remove_one,
1883 .resume = cp_resume,
1884 .suspend = cp_suspend,
1888 static int __init cp_init (void)
1891 printk("%s", version);
1893 return pci_module_init (&cp_driver);
1896 static void __exit cp_exit (void)
1898 pci_unregister_driver (&cp_driver);
1901 module_init(cp_init);
1902 module_exit(cp_exit);