3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
23 This driver is for boards based on the RTL8129 and RTL8139
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
46 Tigran Aivazian - bug fixes, skbuff free cleanup
48 Martin Mares - suggestions for PCI cleanup
50 David S. Miller - PCI DMA and softnet updates
52 Ernst Gill - fixes ported from BSD driver
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
57 Gerard Sharp - bug fix, testing and feedback
59 David Ford - Rx ring wrap fix
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
67 Santiago Garcia Mantinan - testing and feedback
69 Jens David - 2.2.x kernel backports
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
74 Jean-Jacques Michel - bug fix
76 Tobias Ringström - Rx interrupt status checking suggestion
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
83 Robert Kuebel - Save kernel thread from dying on any signal.
85 Submitting bug reports:
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/kernel.h>
99 #include <linux/compiler.h>
100 #include <linux/pci.h>
101 #include <linux/init.h>
102 #include <linux/ioport.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
112 #include <asm/uaccess.h>
115 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
116 #define PFX DRV_NAME ": "
118 /* Default Message level */
119 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
124 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
125 #ifdef CONFIG_8139TOO_PIO
129 /* define to 1 to enable copious debugging info */
132 /* define to 1 to disable lightweight runtime debugging checks */
133 #undef RTL8139_NDEBUG
137 /* note: prints function name for you */
138 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
140 # define DPRINTK(fmt, args...)
143 #ifdef RTL8139_NDEBUG
144 # define assert(expr) do {} while (0)
146 # define assert(expr) \
147 if(unlikely(!(expr))) { \
148 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
149 #expr,__FILE__,__FUNCTION__,__LINE__); \
154 /* A few user-configurable values. */
157 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
164 /* bitmapped message enable number */
165 static int debug = -1;
169 * Warning: 64K ring has hardware issues and may lock up.
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 1 /* 16K ring */
174 #define RX_BUF_IDX 2 /* 32K ring */
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
231 /* indexed by board_t, above */
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
288 { "rx_lost_in_ring" },
291 /* The rest of these values should never change. */
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
315 Config4 = 0x5A, /* absent on RTL-8139A */
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
328 PARA7c = 0x7c, /* Magic transceiver parameter register. */
329 Config5 = 0xD8, /* absent on RTL-8139A */
333 MultiIntrClear = 0xF000,
335 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
345 /* Interrupt register bits, using my own meaningful names. */
346 enum IntrStatusBits {
357 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
364 TxOutOfWindow = 0x20000000,
365 TxAborted = 0x40000000,
366 TxCarrierLost = 0x80000000,
369 RxMulticast = 0x8000,
371 RxBroadcast = 0x2000,
372 RxBadSymbol = 0x0020,
380 /* Bits in RxConfig. */
384 AcceptBroadcast = 0x08,
385 AcceptMulticast = 0x04,
387 AcceptAllPhys = 0x01,
390 /* Bits in TxConfig. */
391 enum tx_config_bits {
392 TxIFG1 = (1 << 25), /* Interframe Gap Time */
393 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
394 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
395 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
396 TxClearAbt = (1 << 0), /* Clear abort (WO) */
397 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
398 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
400 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
403 /* Bits in Config1 */
405 Cfg1_PM_Enable = 0x01,
406 Cfg1_VPD_Enable = 0x02,
409 LWAKE = 0x10, /* not on 8139, 8139A */
410 Cfg1_Driver_Load = 0x20,
413 SLEEP = (1 << 1), /* only on 8139, 8139A */
414 PWRDN = (1 << 0), /* only on 8139, 8139A */
417 /* Bits in Config3 */
419 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
420 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
421 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
422 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
423 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
424 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
425 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
426 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
429 /* Bits in Config4 */
431 LWPTN = (1 << 2), /* not on 8139, 8139A */
434 /* Bits in Config5 */
436 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
437 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
438 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
439 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
440 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
441 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
442 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
446 /* rx fifo threshold */
448 RxCfgFIFONone = (7 << RxCfgFIFOShift),
452 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
454 /* rx ring buffer length */
456 RxCfgRcv16K = (1 << 11),
457 RxCfgRcv32K = (1 << 12),
458 RxCfgRcv64K = (1 << 11) | (1 << 12),
460 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
464 /* Twister tuning parameters from RealTek.
465 Completely undocumented, but required to tune bad links on some boards. */
467 CSCR_LinkOKBit = 0x0400,
468 CSCR_LinkChangeBit = 0x0800,
469 CSCR_LinkStatusBits = 0x0f000,
470 CSCR_LinkDownOffCmd = 0x003c0,
471 CSCR_LinkDownCmd = 0x0f3c0,
476 Cfg9346_Unlock = 0xC0,
493 HasHltClk = (1 << 0),
497 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
498 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
499 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
501 /* directly indexed by chip_t, above */
502 const static struct {
504 u32 version; /* from RTL8139C/RTL8139D docs */
506 } rtl_chip_info[] = {
508 HW_REVID(1, 0, 0, 0, 0, 0, 0),
513 HW_REVID(1, 1, 0, 0, 0, 0, 0),
518 HW_REVID(1, 1, 1, 0, 0, 0, 0),
519 HasHltClk, /* XXX undocumented? */
523 HW_REVID(1, 1, 1, 0, 0, 1, 0),
524 HasHltClk, /* XXX undocumented? */
528 HW_REVID(1, 1, 1, 1, 0, 0, 0),
533 HW_REVID(1, 1, 1, 1, 1, 0, 0),
538 HW_REVID(1, 1, 1, 0, 1, 0, 0),
543 HW_REVID(1, 1, 1, 1, 0, 1, 0),
548 HW_REVID(1, 1, 1, 0, 1, 0, 1),
553 HW_REVID(1, 1, 1, 0, 1, 1, 1),
558 struct rtl_extra_stats {
559 unsigned long early_rx;
560 unsigned long tx_buf_mapped;
561 unsigned long tx_timeouts;
562 unsigned long rx_lost_in_ring;
565 struct rtl8139_private {
568 struct pci_dev *pci_dev;
570 struct net_device_stats stats;
571 unsigned char *rx_ring;
572 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
573 unsigned int tx_flag;
574 unsigned long cur_tx;
575 unsigned long dirty_tx;
576 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
577 unsigned char *tx_bufs; /* Tx bounce buffer region. */
578 dma_addr_t rx_ring_dma;
579 dma_addr_t tx_bufs_dma;
580 signed char phys[4]; /* MII device addresses. */
581 char twistie, twist_row, twist_col; /* Twister tune state. */
582 unsigned int default_port:4; /* Last dev->if_port value. */
587 wait_queue_head_t thr_wait;
588 struct completion thr_exited;
590 struct rtl_extra_stats xstats;
592 struct mii_if_info mii;
593 unsigned int regs_len;
594 unsigned long fifo_copy_timeout;
597 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
598 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
599 MODULE_LICENSE("GPL");
600 MODULE_VERSION(DRV_VERSION);
602 module_param(multicast_filter_limit, int, 0);
603 module_param_array(media, int, NULL, 0);
604 module_param_array(full_duplex, int, NULL, 0);
605 module_param(debug, int, 0);
606 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
607 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
608 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
609 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
611 static int read_eeprom (void *ioaddr, int location, int addr_len);
612 static int rtl8139_open (struct net_device *dev);
613 static int mdio_read (struct net_device *dev, int phy_id, int location);
614 static void mdio_write (struct net_device *dev, int phy_id, int location,
616 static void rtl8139_start_thread(struct net_device *dev);
617 static void rtl8139_tx_timeout (struct net_device *dev);
618 static void rtl8139_init_ring (struct net_device *dev);
619 static int rtl8139_start_xmit (struct sk_buff *skb,
620 struct net_device *dev);
621 static int rtl8139_poll(struct net_device *dev, int *budget);
622 #ifdef CONFIG_NET_POLL_CONTROLLER
623 static void rtl8139_poll_controller(struct net_device *dev);
625 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
626 struct pt_regs *regs);
627 static int rtl8139_close (struct net_device *dev);
628 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
629 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
630 static void rtl8139_set_rx_mode (struct net_device *dev);
631 static void __set_rx_mode (struct net_device *dev);
632 static void rtl8139_hw_start (struct net_device *dev);
633 static struct ethtool_ops rtl8139_ethtool_ops;
637 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
638 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
639 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
640 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
641 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
642 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
643 #define RTL_W8_F RTL_W8
644 #define RTL_W16_F RTL_W16
645 #define RTL_W32_F RTL_W32
652 #define readb(addr) inb((unsigned long)(addr))
653 #define readw(addr) inw((unsigned long)(addr))
654 #define readl(addr) inl((unsigned long)(addr))
655 #define writeb(val,addr) outb((val),(unsigned long)(addr))
656 #define writew(val,addr) outw((val),(unsigned long)(addr))
657 #define writel(val,addr) outl((val),(unsigned long)(addr))
661 /* write MMIO register, with flush */
662 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
663 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
664 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
665 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
668 #define MMIO_FLUSH_AUDIT_COMPLETE 1
669 #if MMIO_FLUSH_AUDIT_COMPLETE
671 /* write MMIO register */
672 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
673 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
674 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
678 /* write MMIO register, then flush */
679 #define RTL_W8 RTL_W8_F
680 #define RTL_W16 RTL_W16_F
681 #define RTL_W32 RTL_W32_F
683 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
685 /* read MMIO register */
686 #define RTL_R8(reg) readb (ioaddr + (reg))
687 #define RTL_R16(reg) readw (ioaddr + (reg))
688 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
690 #endif /* USE_IO_OPS */
693 static const u16 rtl8139_intr_mask =
694 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
695 TxErr | TxOK | RxErr | RxOK;
697 static const u16 rtl8139_norx_intr_mask =
698 PCIErr | PCSTimeout | RxUnderrun |
699 TxErr | TxOK | RxErr ;
702 static const unsigned int rtl8139_rx_config =
703 RxCfgRcv8K | RxNoWrap |
704 (RX_FIFO_THRESH << RxCfgFIFOShift) |
705 (RX_DMA_BURST << RxCfgDMAShift);
706 #elif RX_BUF_IDX == 1
707 static const unsigned int rtl8139_rx_config =
708 RxCfgRcv16K | RxNoWrap |
709 (RX_FIFO_THRESH << RxCfgFIFOShift) |
710 (RX_DMA_BURST << RxCfgDMAShift);
711 #elif RX_BUF_IDX == 2
712 static const unsigned int rtl8139_rx_config =
713 RxCfgRcv32K | RxNoWrap |
714 (RX_FIFO_THRESH << RxCfgFIFOShift) |
715 (RX_DMA_BURST << RxCfgDMAShift);
716 #elif RX_BUF_IDX == 3
717 static const unsigned int rtl8139_rx_config =
719 (RX_FIFO_THRESH << RxCfgFIFOShift) |
720 (RX_DMA_BURST << RxCfgDMAShift);
722 #error "Invalid configuration for 8139_RXBUF_IDX"
725 static const unsigned int rtl8139_tx_config =
726 (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
728 static void __rtl8139_cleanup_dev (struct net_device *dev)
730 struct rtl8139_private *tp;
731 struct pci_dev *pdev;
733 assert (dev != NULL);
734 assert (dev->priv != NULL);
737 assert (tp->pci_dev != NULL);
742 iounmap (tp->mmio_addr);
743 #endif /* !USE_IO_OPS */
745 /* it's ok to call this even if we have no regions to free */
746 pci_release_regions (pdev);
750 pci_set_drvdata (pdev, NULL);
754 static void rtl8139_chip_reset (void *ioaddr)
758 /* Soft reset the chip. */
759 RTL_W8 (ChipCmd, CmdReset);
761 /* Check that the chip has finished the reset. */
762 for (i = 1000; i > 0; i--) {
764 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
771 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
772 struct net_device **dev_out)
775 struct net_device *dev;
776 struct rtl8139_private *tp;
780 unsigned long pio_start, pio_end, pio_flags, pio_len;
781 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
784 assert (pdev != NULL);
788 /* dev and dev->priv zeroed in alloc_etherdev */
789 dev = alloc_etherdev (sizeof (*tp));
791 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
794 SET_MODULE_OWNER(dev);
795 SET_NETDEV_DEV(dev, &pdev->dev);
800 /* enable device (incl. PCI PM wakeup and hotplug setup) */
801 rc = pci_enable_device (pdev);
805 pio_start = pci_resource_start (pdev, 0);
806 pio_end = pci_resource_end (pdev, 0);
807 pio_flags = pci_resource_flags (pdev, 0);
808 pio_len = pci_resource_len (pdev, 0);
810 mmio_start = pci_resource_start (pdev, 1);
811 mmio_end = pci_resource_end (pdev, 1);
812 mmio_flags = pci_resource_flags (pdev, 1);
813 mmio_len = pci_resource_len (pdev, 1);
815 /* set this immediately, we need to know before
816 * we talk to the chip directly */
817 DPRINTK("PIO region size == 0x%02X\n", pio_len);
818 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
821 /* make sure PCI base addr 0 is PIO */
822 if (!(pio_flags & IORESOURCE_IO)) {
823 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
827 /* check for weird/broken PCI region reporting */
828 if (pio_len < RTL_MIN_IO_SIZE) {
829 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
834 /* make sure PCI base addr 1 is MMIO */
835 if (!(mmio_flags & IORESOURCE_MEM)) {
836 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
840 if (mmio_len < RTL_MIN_IO_SIZE) {
841 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
847 rc = pci_request_regions (pdev, "8139too");
851 /* enable PCI bus-mastering */
852 pci_set_master (pdev);
855 ioaddr = (void *) pio_start;
856 dev->base_addr = pio_start;
857 tp->mmio_addr = ioaddr;
858 tp->regs_len = pio_len;
860 /* ioremap MMIO region */
861 ioaddr = ioremap (mmio_start, mmio_len);
862 if (ioaddr == NULL) {
863 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
867 dev->base_addr = (long) ioaddr;
868 tp->mmio_addr = ioaddr;
869 tp->regs_len = mmio_len;
870 #endif /* USE_IO_OPS */
872 /* Bring old chips out of low-power mode. */
873 RTL_W8 (HltClk, 'R');
875 /* check for missing/broken hardware */
876 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
877 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
883 /* identify chip attached to board */
884 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
885 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
886 if (version == rtl_chip_info[i].version) {
891 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
892 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
894 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
898 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
899 version, i, rtl_chip_info[i].name);
901 if (tp->chipset >= CH_8139B) {
902 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
903 DPRINTK("PCI PM wakeup\n");
904 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
907 new_tmp8 |= Cfg1_PM_Enable;
908 if (new_tmp8 != tmp8) {
909 RTL_W8 (Cfg9346, Cfg9346_Unlock);
910 RTL_W8 (Config1, tmp8);
911 RTL_W8 (Cfg9346, Cfg9346_Lock);
913 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
914 tmp8 = RTL_R8 (Config4);
916 RTL_W8 (Cfg9346, Cfg9346_Unlock);
917 RTL_W8 (Config4, tmp8 & ~LWPTN);
918 RTL_W8 (Cfg9346, Cfg9346_Lock);
922 DPRINTK("Old chip wakeup\n");
923 tmp8 = RTL_R8 (Config1);
924 tmp8 &= ~(SLEEP | PWRDN);
925 RTL_W8 (Config1, tmp8);
928 rtl8139_chip_reset (ioaddr);
934 __rtl8139_cleanup_dev (dev);
939 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
940 const struct pci_device_id *ent)
942 struct net_device *dev = NULL;
943 struct rtl8139_private *tp;
944 int i, addr_len, option;
946 static int board_idx = -1;
949 assert (pdev != NULL);
950 assert (ent != NULL);
954 /* when we're built into the kernel, the driver version message
955 * is only printed if at least one 8139 board has been found
959 static int printed_version;
960 if (!printed_version++)
961 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
965 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
967 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
968 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
969 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
970 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
971 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
974 i = rtl8139_init_board (pdev, &dev);
978 assert (dev != NULL);
981 ioaddr = tp->mmio_addr;
982 assert (ioaddr != NULL);
984 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
985 for (i = 0; i < 3; i++)
986 ((u16 *) (dev->dev_addr))[i] =
987 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
989 /* The Rtl8139-specific entries in the device structure. */
990 dev->open = rtl8139_open;
991 dev->hard_start_xmit = rtl8139_start_xmit;
992 dev->poll = rtl8139_poll;
994 dev->stop = rtl8139_close;
995 dev->get_stats = rtl8139_get_stats;
996 dev->set_multicast_list = rtl8139_set_rx_mode;
997 dev->do_ioctl = netdev_ioctl;
998 dev->ethtool_ops = &rtl8139_ethtool_ops;
999 dev->tx_timeout = rtl8139_tx_timeout;
1000 dev->watchdog_timeo = TX_TIMEOUT;
1001 #ifdef CONFIG_NET_POLL_CONTROLLER
1002 dev->poll_controller = rtl8139_poll_controller;
1005 /* note: the hardware is not capable of sg/csum/highdma, however
1006 * through the use of skb_copy_and_csum_dev we enable these
1009 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1011 dev->irq = pdev->irq;
1013 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
1016 /* note: tp->chipset set in rtl8139_init_board */
1017 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1018 tp->mmio_addr = ioaddr;
1020 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1021 spin_lock_init (&tp->lock);
1022 spin_lock_init (&tp->rx_lock);
1023 init_waitqueue_head (&tp->thr_wait);
1024 init_completion (&tp->thr_exited);
1026 tp->mii.mdio_read = mdio_read;
1027 tp->mii.mdio_write = mdio_write;
1028 tp->mii.phy_id_mask = 0x3f;
1029 tp->mii.reg_num_mask = 0x1f;
1031 /* dev is fully set up and ready to use now */
1032 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1033 i = register_netdev (dev);
1034 if (i) goto err_out;
1036 pci_set_drvdata (pdev, dev);
1038 printk (KERN_INFO "%s: %s at 0x%lx, "
1039 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1042 board_info[ent->driver_data].name,
1044 dev->dev_addr[0], dev->dev_addr[1],
1045 dev->dev_addr[2], dev->dev_addr[3],
1046 dev->dev_addr[4], dev->dev_addr[5],
1049 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1050 dev->name, rtl_chip_info[tp->chipset].name);
1052 /* Find the connected MII xcvrs.
1053 Doing this in open() would allow detecting external xcvrs later, but
1054 takes too much time. */
1055 #ifdef CONFIG_8139TOO_8129
1056 if (tp->drv_flags & HAS_MII_XCVR) {
1057 int phy, phy_idx = 0;
1058 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1059 int mii_status = mdio_read(dev, phy, 1);
1060 if (mii_status != 0xffff && mii_status != 0x0000) {
1061 u16 advertising = mdio_read(dev, phy, 4);
1062 tp->phys[phy_idx++] = phy;
1063 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1064 "advertising %4.4x.\n",
1065 dev->name, phy, mii_status, advertising);
1069 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1077 tp->mii.phy_id = tp->phys[0];
1079 /* The lower four bits are the media type. */
1080 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1082 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1083 tp->default_port = option & 0xFF;
1084 if (tp->default_port)
1085 tp->mii.force_media = 1;
1087 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1088 tp->mii.full_duplex = full_duplex[board_idx];
1089 if (tp->mii.full_duplex) {
1090 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1091 /* Changing the MII-advertised media because might prevent
1093 tp->mii.force_media = 1;
1095 if (tp->default_port) {
1096 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1097 (option & 0x20 ? 100 : 10),
1098 (option & 0x10 ? "full" : "half"));
1099 mdio_write(dev, tp->phys[0], 0,
1100 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1101 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1104 /* Put the chip into low-power mode. */
1105 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1106 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1111 __rtl8139_cleanup_dev (dev);
1116 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1118 struct net_device *dev = pci_get_drvdata (pdev);
1119 struct rtl8139_private *np;
1121 assert (dev != NULL);
1123 assert (np != NULL);
1125 unregister_netdev (dev);
1127 __rtl8139_cleanup_dev (dev);
1131 /* Serial EEPROM section. */
1133 /* EEPROM_Ctrl bits. */
1134 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1135 #define EE_CS 0x08 /* EEPROM chip select. */
1136 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1137 #define EE_WRITE_0 0x00
1138 #define EE_WRITE_1 0x02
1139 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1140 #define EE_ENB (0x80 | EE_CS)
1142 /* Delay between EEPROM clock transitions.
1143 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1146 #define eeprom_delay() readl(ee_addr)
1148 /* The EEPROM commands include the alway-set leading bit. */
1149 #define EE_WRITE_CMD (5)
1150 #define EE_READ_CMD (6)
1151 #define EE_ERASE_CMD (7)
1153 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1156 unsigned retval = 0;
1157 void *ee_addr = ioaddr + Cfg9346;
1158 int read_cmd = location | (EE_READ_CMD << addr_len);
1160 writeb (EE_ENB & ~EE_CS, ee_addr);
1161 writeb (EE_ENB, ee_addr);
1164 /* Shift the read command bits out. */
1165 for (i = 4 + addr_len; i >= 0; i--) {
1166 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1167 writeb (EE_ENB | dataval, ee_addr);
1169 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1172 writeb (EE_ENB, ee_addr);
1175 for (i = 16; i > 0; i--) {
1176 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1179 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1181 writeb (EE_ENB, ee_addr);
1185 /* Terminate the EEPROM access. */
1186 writeb (~EE_CS, ee_addr);
1192 /* MII serial management: mostly bogus for now. */
1193 /* Read and write the MII management registers using software-generated
1194 serial MDIO protocol.
1195 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1196 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1197 "overclocking" issues. */
1198 #define MDIO_DIR 0x80
1199 #define MDIO_DATA_OUT 0x04
1200 #define MDIO_DATA_IN 0x02
1201 #define MDIO_CLK 0x01
1202 #define MDIO_WRITE0 (MDIO_DIR)
1203 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1205 #define mdio_delay(mdio_addr) readb(mdio_addr)
1208 static char mii_2_8139_map[8] = {
1220 #ifdef CONFIG_8139TOO_8129
1221 /* Syncronize the MII management interface by shifting 32 one bits out. */
1222 static void mdio_sync (void *mdio_addr)
1226 for (i = 32; i >= 0; i--) {
1227 writeb (MDIO_WRITE1, mdio_addr);
1228 mdio_delay (mdio_addr);
1229 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1230 mdio_delay (mdio_addr);
1235 static int mdio_read (struct net_device *dev, int phy_id, int location)
1237 struct rtl8139_private *tp = dev->priv;
1239 #ifdef CONFIG_8139TOO_8129
1240 void *mdio_addr = tp->mmio_addr + Config4;
1241 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1245 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1246 return location < 8 && mii_2_8139_map[location] ?
1247 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1250 #ifdef CONFIG_8139TOO_8129
1251 mdio_sync (mdio_addr);
1252 /* Shift the read command bits out. */
1253 for (i = 15; i >= 0; i--) {
1254 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1256 writeb (MDIO_DIR | dataval, mdio_addr);
1257 mdio_delay (mdio_addr);
1258 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1259 mdio_delay (mdio_addr);
1262 /* Read the two transition, 16 data, and wire-idle bits. */
1263 for (i = 19; i > 0; i--) {
1264 writeb (0, mdio_addr);
1265 mdio_delay (mdio_addr);
1266 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1267 writeb (MDIO_CLK, mdio_addr);
1268 mdio_delay (mdio_addr);
1272 return (retval >> 1) & 0xffff;
1276 static void mdio_write (struct net_device *dev, int phy_id, int location,
1279 struct rtl8139_private *tp = dev->priv;
1280 #ifdef CONFIG_8139TOO_8129
1281 void *mdio_addr = tp->mmio_addr + Config4;
1282 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1286 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1287 void *ioaddr = tp->mmio_addr;
1288 if (location == 0) {
1289 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1290 RTL_W16 (BasicModeCtrl, value);
1291 RTL_W8 (Cfg9346, Cfg9346_Lock);
1292 } else if (location < 8 && mii_2_8139_map[location])
1293 RTL_W16 (mii_2_8139_map[location], value);
1297 #ifdef CONFIG_8139TOO_8129
1298 mdio_sync (mdio_addr);
1300 /* Shift the command bits out. */
1301 for (i = 31; i >= 0; i--) {
1303 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1304 writeb (dataval, mdio_addr);
1305 mdio_delay (mdio_addr);
1306 writeb (dataval | MDIO_CLK, mdio_addr);
1307 mdio_delay (mdio_addr);
1309 /* Clear out extra bits. */
1310 for (i = 2; i > 0; i--) {
1311 writeb (0, mdio_addr);
1312 mdio_delay (mdio_addr);
1313 writeb (MDIO_CLK, mdio_addr);
1314 mdio_delay (mdio_addr);
1320 static int rtl8139_open (struct net_device *dev)
1322 struct rtl8139_private *tp = dev->priv;
1324 void *ioaddr = tp->mmio_addr;
1326 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1330 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1332 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1334 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1335 free_irq(dev->irq, dev);
1338 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1339 tp->tx_bufs, tp->tx_bufs_dma);
1341 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1342 tp->rx_ring, tp->rx_ring_dma);
1348 tp->mii.full_duplex = tp->mii.force_media;
1349 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1351 rtl8139_init_ring (dev);
1352 rtl8139_hw_start (dev);
1353 netif_start_queue (dev);
1355 if (netif_msg_ifup(tp))
1356 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1357 " GP Pins %2.2x %s-duplex.\n",
1358 dev->name, pci_resource_start (tp->pci_dev, 1),
1359 dev->irq, RTL_R8 (MediaStatus),
1360 tp->mii.full_duplex ? "full" : "half");
1362 rtl8139_start_thread(dev);
1368 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1370 struct rtl8139_private *tp = dev->priv;
1372 if (tp->phys[0] >= 0) {
1373 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1377 /* Start the hardware at open or resume. */
1378 static void rtl8139_hw_start (struct net_device *dev)
1380 struct rtl8139_private *tp = dev->priv;
1381 void *ioaddr = tp->mmio_addr;
1385 /* Bring old chips out of low-power mode. */
1386 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1387 RTL_W8 (HltClk, 'R');
1389 rtl8139_chip_reset (ioaddr);
1391 /* unlock Config[01234] and BMCR register writes */
1392 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1393 /* Restore our idea of the MAC address. */
1394 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1395 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1397 /* Must enable Tx/Rx before setting transfer thresholds! */
1398 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1400 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1401 RTL_W32 (RxConfig, tp->rx_config);
1403 /* Check this value: the documentation for IFG contradicts ifself. */
1404 RTL_W32 (TxConfig, rtl8139_tx_config);
1408 rtl_check_media (dev, 1);
1410 if (tp->chipset >= CH_8139B) {
1411 /* Disable magic packet scanning, which is enabled
1412 * when PM is enabled in Config1. It can be reenabled
1413 * via ETHTOOL_SWOL if desired. */
1414 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1417 DPRINTK("init buffer addresses\n");
1419 /* Lock Config[01234] and BMCR register writes */
1420 RTL_W8 (Cfg9346, Cfg9346_Lock);
1422 /* init Rx ring buffer DMA address */
1423 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1425 /* init Tx buffer DMA addresses */
1426 for (i = 0; i < NUM_TX_DESC; i++)
1427 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1429 RTL_W32 (RxMissed, 0);
1431 rtl8139_set_rx_mode (dev);
1433 /* no early-rx interrupts */
1434 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1436 /* make sure RxTx has started */
1437 tmp = RTL_R8 (ChipCmd);
1438 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1439 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1441 /* Enable all known interrupts by setting the interrupt mask. */
1442 RTL_W16 (IntrMask, rtl8139_intr_mask);
1446 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1447 static void rtl8139_init_ring (struct net_device *dev)
1449 struct rtl8139_private *tp = dev->priv;
1456 for (i = 0; i < NUM_TX_DESC; i++)
1457 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1461 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1462 static int next_tick = 3 * HZ;
1464 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1465 static inline void rtl8139_tune_twister (struct net_device *dev,
1466 struct rtl8139_private *tp) {}
1468 enum TwisterParamVals {
1469 PARA78_default = 0x78fa8388,
1470 PARA7c_default = 0xcb38de43, /* param[0][3] */
1471 PARA7c_xxx = 0xcb38de43,
1474 static const unsigned long param[4][4] = {
1475 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1476 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1477 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1478 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1481 static void rtl8139_tune_twister (struct net_device *dev,
1482 struct rtl8139_private *tp)
1485 void *ioaddr = tp->mmio_addr;
1487 /* This is a complicated state machine to configure the "twister" for
1488 impedance/echos based on the cable length.
1489 All of this is magic and undocumented.
1491 switch (tp->twistie) {
1493 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1494 /* We have link beat, let us tune the twister. */
1495 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1496 tp->twistie = 2; /* Change to state 2. */
1497 next_tick = HZ / 10;
1499 /* Just put in some reasonable defaults for when beat returns. */
1500 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1501 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1502 RTL_W32 (PARA78, PARA78_default);
1503 RTL_W32 (PARA7c, PARA7c_default);
1504 tp->twistie = 0; /* Bail from future actions. */
1508 /* Read how long it took to hear the echo. */
1509 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1510 if (linkcase == 0x7000)
1512 else if (linkcase == 0x3000)
1514 else if (linkcase == 0x1000)
1519 tp->twistie = 3; /* Change to state 2. */
1520 next_tick = HZ / 10;
1523 /* Put out four tuning parameters, one per 100msec. */
1524 if (tp->twist_col == 0)
1525 RTL_W16 (FIFOTMS, 0);
1526 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1527 [(int) tp->twist_col]);
1528 next_tick = HZ / 10;
1529 if (++tp->twist_col >= 4) {
1530 /* For short cables we are done.
1531 For long cables (row == 3) check for mistune. */
1533 (tp->twist_row == 3) ? 4 : 0;
1537 /* Special case for long cables: check for mistune. */
1538 if ((RTL_R16 (CSCR) &
1539 CSCR_LinkStatusBits) == 0x7000) {
1543 RTL_W32 (PARA7c, 0xfb38de03);
1545 next_tick = HZ / 10;
1549 /* Retune for shorter cable (column 2). */
1550 RTL_W32 (FIFOTMS, 0x20);
1551 RTL_W32 (PARA78, PARA78_default);
1552 RTL_W32 (PARA7c, PARA7c_default);
1553 RTL_W32 (FIFOTMS, 0x00);
1557 next_tick = HZ / 10;
1565 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1567 static inline void rtl8139_thread_iter (struct net_device *dev,
1568 struct rtl8139_private *tp,
1573 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1575 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1576 int duplex = (mii_lpa & LPA_100FULL)
1577 || (mii_lpa & 0x01C0) == 0x0040;
1578 if (tp->mii.full_duplex != duplex) {
1579 tp->mii.full_duplex = duplex;
1583 "%s: Setting %s-duplex based on MII #%d link"
1584 " partner ability of %4.4x.\n",
1586 tp->mii.full_duplex ? "full" : "half",
1587 tp->phys[0], mii_lpa);
1589 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1593 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1594 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1595 RTL_W8 (Cfg9346, Cfg9346_Lock);
1600 next_tick = HZ * 60;
1602 rtl8139_tune_twister (dev, tp);
1604 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1605 dev->name, RTL_R16 (NWayLPAR));
1606 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1607 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1608 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1609 dev->name, RTL_R8 (Config0),
1613 static int rtl8139_thread (void *data)
1615 struct net_device *dev = data;
1616 struct rtl8139_private *tp = dev->priv;
1617 unsigned long timeout;
1619 daemonize("%s", dev->name);
1620 allow_signal(SIGTERM);
1623 timeout = next_tick;
1625 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1626 /* make swsusp happy with our thread */
1627 try_to_freeze(PF_FREEZE);
1628 } while (!signal_pending (current) && (timeout > 0));
1630 if (signal_pending (current)) {
1631 flush_signals(current);
1634 if (tp->time_to_die)
1637 if (rtnl_lock_interruptible ())
1639 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1643 complete_and_exit (&tp->thr_exited, 0);
1646 static void rtl8139_start_thread(struct net_device *dev)
1648 struct rtl8139_private *tp = dev->priv;
1652 tp->time_to_die = 0;
1653 if (tp->chipset == CH_8139_K)
1655 else if (tp->drv_flags & HAS_LNK_CHNG)
1658 tp->thr_pid = kernel_thread(rtl8139_thread, dev, CLONE_FS|CLONE_FILES);
1659 if (tp->thr_pid < 0) {
1660 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1665 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1670 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1674 static void rtl8139_tx_timeout (struct net_device *dev)
1676 struct rtl8139_private *tp = dev->priv;
1677 void *ioaddr = tp->mmio_addr;
1680 unsigned long flags;
1682 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1683 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1684 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1685 /* Emit info to figure out what went wrong. */
1686 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1687 dev->name, tp->cur_tx, tp->dirty_tx);
1688 for (i = 0; i < NUM_TX_DESC; i++)
1689 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1690 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1691 i == tp->dirty_tx % NUM_TX_DESC ?
1692 " (queue head)" : "");
1694 tp->xstats.tx_timeouts++;
1696 /* disable Tx ASAP, if not already */
1697 tmp8 = RTL_R8 (ChipCmd);
1698 if (tmp8 & CmdTxEnb)
1699 RTL_W8 (ChipCmd, CmdRxEnb);
1701 spin_lock(&tp->rx_lock);
1702 /* Disable interrupts by clearing the interrupt mask. */
1703 RTL_W16 (IntrMask, 0x0000);
1705 /* Stop a shared interrupt from scavenging while we are. */
1706 spin_lock_irqsave (&tp->lock, flags);
1707 rtl8139_tx_clear (tp);
1708 spin_unlock_irqrestore (&tp->lock, flags);
1710 /* ...and finally, reset everything */
1711 if (netif_running(dev)) {
1712 rtl8139_hw_start (dev);
1713 netif_wake_queue (dev);
1715 spin_unlock(&tp->rx_lock);
1719 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1721 struct rtl8139_private *tp = dev->priv;
1722 void *ioaddr = tp->mmio_addr;
1724 unsigned int len = skb->len;
1726 /* Calculate the next Tx descriptor entry. */
1727 entry = tp->cur_tx % NUM_TX_DESC;
1729 /* Note: the chip doesn't have auto-pad! */
1730 if (likely(len < TX_BUF_SIZE)) {
1732 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1733 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1737 tp->stats.tx_dropped++;
1741 spin_lock_irq(&tp->lock);
1742 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1743 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1745 dev->trans_start = jiffies;
1750 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1751 netif_stop_queue (dev);
1752 spin_unlock_irq(&tp->lock);
1754 if (netif_msg_tx_queued(tp))
1755 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1756 dev->name, len, entry);
1762 static void rtl8139_tx_interrupt (struct net_device *dev,
1763 struct rtl8139_private *tp,
1766 unsigned long dirty_tx, tx_left;
1768 assert (dev != NULL);
1769 assert (tp != NULL);
1770 assert (ioaddr != NULL);
1772 dirty_tx = tp->dirty_tx;
1773 tx_left = tp->cur_tx - dirty_tx;
1774 while (tx_left > 0) {
1775 int entry = dirty_tx % NUM_TX_DESC;
1778 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1780 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1781 break; /* It still hasn't been Txed */
1783 /* Note: TxCarrierLost is always asserted at 100mbps. */
1784 if (txstatus & (TxOutOfWindow | TxAborted)) {
1785 /* There was an major error, log it. */
1786 if (netif_msg_tx_err(tp))
1787 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1788 dev->name, txstatus);
1789 tp->stats.tx_errors++;
1790 if (txstatus & TxAborted) {
1791 tp->stats.tx_aborted_errors++;
1792 RTL_W32 (TxConfig, TxClearAbt);
1793 RTL_W16 (IntrStatus, TxErr);
1796 if (txstatus & TxCarrierLost)
1797 tp->stats.tx_carrier_errors++;
1798 if (txstatus & TxOutOfWindow)
1799 tp->stats.tx_window_errors++;
1801 if (txstatus & TxUnderrun) {
1802 /* Add 64 to the Tx FIFO threshold. */
1803 if (tp->tx_flag < 0x00300000)
1804 tp->tx_flag += 0x00020000;
1805 tp->stats.tx_fifo_errors++;
1807 tp->stats.collisions += (txstatus >> 24) & 15;
1808 tp->stats.tx_bytes += txstatus & 0x7ff;
1809 tp->stats.tx_packets++;
1816 #ifndef RTL8139_NDEBUG
1817 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1818 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1819 dev->name, dirty_tx, tp->cur_tx);
1820 dirty_tx += NUM_TX_DESC;
1822 #endif /* RTL8139_NDEBUG */
1824 /* only wake the queue if we did work, and the queue is stopped */
1825 if (tp->dirty_tx != dirty_tx) {
1826 tp->dirty_tx = dirty_tx;
1828 netif_wake_queue (dev);
1833 /* TODO: clean this up! Rx reset need not be this intensive */
1834 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1835 struct rtl8139_private *tp, void *ioaddr)
1838 #ifdef CONFIG_8139_OLD_RX_RESET
1842 if (netif_msg_rx_err (tp))
1843 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1844 dev->name, rx_status);
1845 tp->stats.rx_errors++;
1846 if (!(rx_status & RxStatusOK)) {
1847 if (rx_status & RxTooLong) {
1848 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1849 dev->name, rx_status);
1850 /* A.C.: The chip hangs here. */
1852 if (rx_status & (RxBadSymbol | RxBadAlign))
1853 tp->stats.rx_frame_errors++;
1854 if (rx_status & (RxRunt | RxTooLong))
1855 tp->stats.rx_length_errors++;
1856 if (rx_status & RxCRCErr)
1857 tp->stats.rx_crc_errors++;
1859 tp->xstats.rx_lost_in_ring++;
1862 #ifndef CONFIG_8139_OLD_RX_RESET
1863 tmp8 = RTL_R8 (ChipCmd);
1864 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1865 RTL_W8 (ChipCmd, tmp8);
1866 RTL_W32 (RxConfig, tp->rx_config);
1869 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1871 /* disable receive */
1872 RTL_W8_F (ChipCmd, CmdTxEnb);
1874 while (--tmp_work > 0) {
1876 tmp8 = RTL_R8 (ChipCmd);
1877 if (!(tmp8 & CmdRxEnb))
1881 printk (KERN_WARNING PFX "rx stop wait too long\n");
1882 /* restart receive */
1884 while (--tmp_work > 0) {
1885 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1887 tmp8 = RTL_R8 (ChipCmd);
1888 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1892 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1894 /* and reinitialize all rx related registers */
1895 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1896 /* Must enable Tx/Rx before setting transfer thresholds! */
1897 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1899 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1900 RTL_W32 (RxConfig, tp->rx_config);
1903 DPRINTK("init buffer addresses\n");
1905 /* Lock Config[01234] and BMCR register writes */
1906 RTL_W8 (Cfg9346, Cfg9346_Lock);
1908 /* init Rx ring buffer DMA address */
1909 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1911 /* A.C.: Reset the multicast list. */
1912 __set_rx_mode (dev);
1917 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1918 u32 offset, unsigned int size)
1920 u32 left = RX_BUF_LEN - offset;
1923 memcpy(skb->data, ring + offset, left);
1924 memcpy(skb->data+left, ring, size - left);
1926 memcpy(skb->data, ring + offset, size);
1930 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1932 void *ioaddr = tp->mmio_addr;
1935 status = RTL_R16 (IntrStatus) & RxAckBits;
1937 /* Clear out errors and receive interrupts */
1938 if (likely(status != 0)) {
1939 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1940 tp->stats.rx_errors++;
1941 if (status & RxFIFOOver)
1942 tp->stats.rx_fifo_errors++;
1944 RTL_W16_F (IntrStatus, RxAckBits);
1948 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1951 void *ioaddr = tp->mmio_addr;
1953 unsigned char *rx_ring = tp->rx_ring;
1954 unsigned int cur_rx = tp->cur_rx;
1955 unsigned int rx_size = 0;
1957 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1958 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1959 RTL_R16 (RxBufAddr),
1960 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1962 while (netif_running(dev) && received < budget
1963 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1964 u32 ring_offset = cur_rx % RX_BUF_LEN;
1966 unsigned int pkt_size;
1967 struct sk_buff *skb;
1971 /* read size+status of next frame from DMA ring buffer */
1972 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1973 rx_size = rx_status >> 16;
1974 pkt_size = rx_size - 4;
1976 if (netif_msg_rx_status(tp))
1977 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1978 " cur %4.4x.\n", dev->name, rx_status,
1980 #if RTL8139_DEBUG > 2
1983 DPRINTK ("%s: Frame contents ", dev->name);
1984 for (i = 0; i < 70; i++)
1986 rx_ring[ring_offset + i]);
1991 /* Packet copy from FIFO still in progress.
1992 * Theoretically, this should never happen
1993 * since EarlyRx is disabled.
1995 if (unlikely(rx_size == 0xfff0)) {
1996 if (!tp->fifo_copy_timeout)
1997 tp->fifo_copy_timeout = jiffies + 2;
1998 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1999 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
2003 if (netif_msg_intr(tp)) {
2004 printk(KERN_DEBUG "%s: fifo copy in progress.",
2007 tp->xstats.early_rx++;
2012 tp->fifo_copy_timeout = 0;
2014 /* If Rx err or invalid rx_size/rx_status received
2015 * (which happens if we get lost in the ring),
2016 * Rx process gets reset, so we abort any further
2019 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2021 (!(rx_status & RxStatusOK)))) {
2022 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2027 /* Malloc up new buffer, compatible with net-2e. */
2028 /* Omit the four octet CRC from the length. */
2030 skb = dev_alloc_skb (pkt_size + 2);
2033 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2035 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2037 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2039 skb_put (skb, pkt_size);
2041 skb->protocol = eth_type_trans (skb, dev);
2043 dev->last_rx = jiffies;
2044 tp->stats.rx_bytes += pkt_size;
2045 tp->stats.rx_packets++;
2047 netif_receive_skb (skb);
2049 if (net_ratelimit())
2050 printk (KERN_WARNING
2051 "%s: Memory squeeze, dropping packet.\n",
2053 tp->stats.rx_dropped++;
2057 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2058 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2060 rtl8139_isr_ack(tp);
2063 if (unlikely(!received || rx_size == 0xfff0))
2064 rtl8139_isr_ack(tp);
2066 #if RTL8139_DEBUG > 1
2067 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2068 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2069 RTL_R16 (RxBufAddr),
2070 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2073 tp->cur_rx = cur_rx;
2076 * The receive buffer should be mostly empty.
2077 * Tell NAPI to reenable the Rx irq.
2079 if (tp->fifo_copy_timeout)
2087 static void rtl8139_weird_interrupt (struct net_device *dev,
2088 struct rtl8139_private *tp,
2090 int status, int link_changed)
2092 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2095 assert (dev != NULL);
2096 assert (tp != NULL);
2097 assert (ioaddr != NULL);
2099 /* Update the error count. */
2100 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2101 RTL_W32 (RxMissed, 0);
2103 if ((status & RxUnderrun) && link_changed &&
2104 (tp->drv_flags & HAS_LNK_CHNG)) {
2105 rtl_check_media(dev, 0);
2106 status &= ~RxUnderrun;
2109 if (status & (RxUnderrun | RxErr))
2110 tp->stats.rx_errors++;
2112 if (status & PCSTimeout)
2113 tp->stats.rx_length_errors++;
2114 if (status & RxUnderrun)
2115 tp->stats.rx_fifo_errors++;
2116 if (status & PCIErr) {
2118 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2119 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2121 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2122 dev->name, pci_cmd_status);
2126 static int rtl8139_poll(struct net_device *dev, int *budget)
2128 struct rtl8139_private *tp = dev->priv;
2129 void *ioaddr = tp->mmio_addr;
2130 int orig_budget = min(*budget, dev->quota);
2133 spin_lock(&tp->rx_lock);
2134 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2137 work_done = rtl8139_rx(dev, tp, orig_budget);
2138 if (likely(work_done > 0)) {
2139 *budget -= work_done;
2140 dev->quota -= work_done;
2141 done = (work_done < orig_budget);
2147 * Order is important since data can get interrupted
2148 * again when we think we are done.
2150 local_irq_disable();
2151 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2152 __netif_rx_complete(dev);
2155 spin_unlock(&tp->rx_lock);
2160 /* The interrupt handler does all of the Rx thread work and cleans up
2161 after the Tx thread. */
2162 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2163 struct pt_regs *regs)
2165 struct net_device *dev = (struct net_device *) dev_instance;
2166 struct rtl8139_private *tp = dev->priv;
2167 void *ioaddr = tp->mmio_addr;
2168 u16 status, ackstat;
2169 int link_changed = 0; /* avoid bogus "uninit" warning */
2172 spin_lock (&tp->lock);
2173 status = RTL_R16 (IntrStatus);
2176 if (unlikely((status & rtl8139_intr_mask) == 0))
2181 /* h/w no longer present (hotplug?) or major error, bail */
2182 if (unlikely(status == 0xFFFF))
2185 /* close possible race's with dev_close */
2186 if (unlikely(!netif_running(dev))) {
2187 RTL_W16 (IntrMask, 0);
2191 /* Acknowledge all of the current interrupt sources ASAP, but
2192 an first get an additional status bit from CSCR. */
2193 if (unlikely(status & RxUnderrun))
2194 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2196 ackstat = status & ~(RxAckBits | TxErr);
2198 RTL_W16 (IntrStatus, ackstat);
2200 /* Receive packets are processed by poll routine.
2201 If not running start it now. */
2202 if (status & RxAckBits){
2203 if (netif_rx_schedule_prep(dev)) {
2204 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2205 __netif_rx_schedule (dev);
2209 /* Check uncommon events with one test. */
2210 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2211 rtl8139_weird_interrupt (dev, tp, ioaddr,
2212 status, link_changed);
2214 if (status & (TxOK | TxErr)) {
2215 rtl8139_tx_interrupt (dev, tp, ioaddr);
2217 RTL_W16 (IntrStatus, TxErr);
2220 spin_unlock (&tp->lock);
2222 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2223 dev->name, RTL_R16 (IntrStatus));
2224 return IRQ_RETVAL(handled);
2227 #ifdef CONFIG_NET_POLL_CONTROLLER
2229 * Polling receive - used by netconsole and other diagnostic tools
2230 * to allow network i/o with interrupts disabled.
2232 static void rtl8139_poll_controller(struct net_device *dev)
2234 disable_irq(dev->irq);
2235 rtl8139_interrupt(dev->irq, dev, NULL);
2236 enable_irq(dev->irq);
2240 static int rtl8139_close (struct net_device *dev)
2242 struct rtl8139_private *tp = dev->priv;
2243 void *ioaddr = tp->mmio_addr;
2245 unsigned long flags;
2247 netif_stop_queue (dev);
2249 if (tp->thr_pid >= 0) {
2250 tp->time_to_die = 1;
2252 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2254 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2257 wait_for_completion (&tp->thr_exited);
2260 if (netif_msg_ifdown(tp))
2261 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2262 dev->name, RTL_R16 (IntrStatus));
2264 spin_lock_irqsave (&tp->lock, flags);
2266 /* Stop the chip's Tx and Rx DMA processes. */
2267 RTL_W8 (ChipCmd, 0);
2269 /* Disable interrupts by clearing the interrupt mask. */
2270 RTL_W16 (IntrMask, 0);
2272 /* Update the error counts. */
2273 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2274 RTL_W32 (RxMissed, 0);
2276 spin_unlock_irqrestore (&tp->lock, flags);
2278 synchronize_irq (dev->irq); /* racy, but that's ok here */
2279 free_irq (dev->irq, dev);
2281 rtl8139_tx_clear (tp);
2283 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2284 tp->rx_ring, tp->rx_ring_dma);
2285 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2286 tp->tx_bufs, tp->tx_bufs_dma);
2290 /* Green! Put the chip in low-power mode. */
2291 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2293 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2294 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2300 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2301 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2302 other threads or interrupts aren't messing with the 8139. */
2303 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2305 struct rtl8139_private *np = dev->priv;
2306 void *ioaddr = np->mmio_addr;
2308 spin_lock_irq(&np->lock);
2309 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2310 u8 cfg3 = RTL_R8 (Config3);
2311 u8 cfg5 = RTL_R8 (Config5);
2313 wol->supported = WAKE_PHY | WAKE_MAGIC
2314 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2317 if (cfg3 & Cfg3_LinkUp)
2318 wol->wolopts |= WAKE_PHY;
2319 if (cfg3 & Cfg3_Magic)
2320 wol->wolopts |= WAKE_MAGIC;
2321 /* (KON)FIXME: See how netdev_set_wol() handles the
2322 following constants. */
2323 if (cfg5 & Cfg5_UWF)
2324 wol->wolopts |= WAKE_UCAST;
2325 if (cfg5 & Cfg5_MWF)
2326 wol->wolopts |= WAKE_MCAST;
2327 if (cfg5 & Cfg5_BWF)
2328 wol->wolopts |= WAKE_BCAST;
2330 spin_unlock_irq(&np->lock);
2334 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2335 that wol points to kernel memory and other threads or interrupts
2336 aren't messing with the 8139. */
2337 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2339 struct rtl8139_private *np = dev->priv;
2340 void *ioaddr = np->mmio_addr;
2344 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2345 ? (WAKE_PHY | WAKE_MAGIC
2346 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2348 if (wol->wolopts & ~support)
2351 spin_lock_irq(&np->lock);
2352 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2353 if (wol->wolopts & WAKE_PHY)
2354 cfg3 |= Cfg3_LinkUp;
2355 if (wol->wolopts & WAKE_MAGIC)
2357 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2358 RTL_W8 (Config3, cfg3);
2359 RTL_W8 (Cfg9346, Cfg9346_Lock);
2361 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2362 /* (KON)FIXME: These are untested. We may have to set the
2363 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2365 if (wol->wolopts & WAKE_UCAST)
2367 if (wol->wolopts & WAKE_MCAST)
2369 if (wol->wolopts & WAKE_BCAST)
2371 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2372 spin_unlock_irq(&np->lock);
2377 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2379 struct rtl8139_private *np = dev->priv;
2380 strcpy(info->driver, DRV_NAME);
2381 strcpy(info->version, DRV_VERSION);
2382 strcpy(info->bus_info, pci_name(np->pci_dev));
2383 info->regdump_len = np->regs_len;
2386 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2388 struct rtl8139_private *np = dev->priv;
2389 spin_lock_irq(&np->lock);
2390 mii_ethtool_gset(&np->mii, cmd);
2391 spin_unlock_irq(&np->lock);
2395 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2397 struct rtl8139_private *np = dev->priv;
2399 spin_lock_irq(&np->lock);
2400 rc = mii_ethtool_sset(&np->mii, cmd);
2401 spin_unlock_irq(&np->lock);
2405 static int rtl8139_nway_reset(struct net_device *dev)
2407 struct rtl8139_private *np = dev->priv;
2408 return mii_nway_restart(&np->mii);
2411 static u32 rtl8139_get_link(struct net_device *dev)
2413 struct rtl8139_private *np = dev->priv;
2414 return mii_link_ok(&np->mii);
2417 static u32 rtl8139_get_msglevel(struct net_device *dev)
2419 struct rtl8139_private *np = dev->priv;
2420 return np->msg_enable;
2423 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2425 struct rtl8139_private *np = dev->priv;
2426 np->msg_enable = datum;
2429 /* TODO: we are too slack to do reg dumping for pio, for now */
2430 #ifdef CONFIG_8139TOO_PIO
2431 #define rtl8139_get_regs_len NULL
2432 #define rtl8139_get_regs NULL
2434 static int rtl8139_get_regs_len(struct net_device *dev)
2436 struct rtl8139_private *np = dev->priv;
2437 return np->regs_len;
2440 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2442 struct rtl8139_private *np = dev->priv;
2444 regs->version = RTL_REGS_VER;
2446 spin_lock_irq(&np->lock);
2447 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2448 spin_unlock_irq(&np->lock);
2450 #endif /* CONFIG_8139TOO_MMIO */
2452 static int rtl8139_get_stats_count(struct net_device *dev)
2454 return RTL_NUM_STATS;
2457 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2459 struct rtl8139_private *np = dev->priv;
2461 data[0] = np->xstats.early_rx;
2462 data[1] = np->xstats.tx_buf_mapped;
2463 data[2] = np->xstats.tx_timeouts;
2464 data[3] = np->xstats.rx_lost_in_ring;
2467 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2469 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2472 static struct ethtool_ops rtl8139_ethtool_ops = {
2473 .get_drvinfo = rtl8139_get_drvinfo,
2474 .get_settings = rtl8139_get_settings,
2475 .set_settings = rtl8139_set_settings,
2476 .get_regs_len = rtl8139_get_regs_len,
2477 .get_regs = rtl8139_get_regs,
2478 .nway_reset = rtl8139_nway_reset,
2479 .get_link = rtl8139_get_link,
2480 .get_msglevel = rtl8139_get_msglevel,
2481 .set_msglevel = rtl8139_set_msglevel,
2482 .get_wol = rtl8139_get_wol,
2483 .set_wol = rtl8139_set_wol,
2484 .get_strings = rtl8139_get_strings,
2485 .get_stats_count = rtl8139_get_stats_count,
2486 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2489 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2491 struct rtl8139_private *np = dev->priv;
2494 if (!netif_running(dev))
2497 spin_lock_irq(&np->lock);
2498 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2499 spin_unlock_irq(&np->lock);
2505 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2507 struct rtl8139_private *tp = dev->priv;
2508 void *ioaddr = tp->mmio_addr;
2509 unsigned long flags;
2511 if (netif_running(dev)) {
2512 spin_lock_irqsave (&tp->lock, flags);
2513 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2514 RTL_W32 (RxMissed, 0);
2515 spin_unlock_irqrestore (&tp->lock, flags);
2521 /* Set or clear the multicast filter for this adaptor.
2522 This routine is not state sensitive and need not be SMP locked. */
2524 static void __set_rx_mode (struct net_device *dev)
2526 struct rtl8139_private *tp = dev->priv;
2527 void *ioaddr = tp->mmio_addr;
2528 u32 mc_filter[2]; /* Multicast hash filter */
2532 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2533 dev->name, dev->flags, RTL_R32 (RxConfig));
2535 /* Note: do not reorder, GCC is clever about common statements. */
2536 if (dev->flags & IFF_PROMISC) {
2537 /* Unconditionally log net taps. */
2538 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2541 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2543 mc_filter[1] = mc_filter[0] = 0xffffffff;
2544 } else if ((dev->mc_count > multicast_filter_limit)
2545 || (dev->flags & IFF_ALLMULTI)) {
2546 /* Too many to filter perfectly -- accept all multicasts. */
2547 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2548 mc_filter[1] = mc_filter[0] = 0xffffffff;
2550 struct dev_mc_list *mclist;
2551 rx_mode = AcceptBroadcast | AcceptMyPhys;
2552 mc_filter[1] = mc_filter[0] = 0;
2553 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2554 i++, mclist = mclist->next) {
2555 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2557 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2558 rx_mode |= AcceptMulticast;
2562 /* We can safely update without stopping the chip. */
2563 tmp = rtl8139_rx_config | rx_mode;
2564 if (tp->rx_config != tmp) {
2565 RTL_W32_F (RxConfig, tmp);
2566 tp->rx_config = tmp;
2568 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2569 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2572 static void rtl8139_set_rx_mode (struct net_device *dev)
2574 unsigned long flags;
2575 struct rtl8139_private *tp = dev->priv;
2577 spin_lock_irqsave (&tp->lock, flags);
2579 spin_unlock_irqrestore (&tp->lock, flags);
2584 static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
2586 struct net_device *dev = pci_get_drvdata (pdev);
2587 struct rtl8139_private *tp = dev->priv;
2588 void *ioaddr = tp->mmio_addr;
2589 unsigned long flags;
2591 pci_save_state (pdev);
2593 if (!netif_running (dev))
2596 netif_device_detach (dev);
2598 spin_lock_irqsave (&tp->lock, flags);
2600 /* Disable interrupts, stop Tx and Rx. */
2601 RTL_W16 (IntrMask, 0);
2602 RTL_W8 (ChipCmd, 0);
2604 /* Update the error counts. */
2605 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2606 RTL_W32 (RxMissed, 0);
2608 spin_unlock_irqrestore (&tp->lock, flags);
2610 pci_set_power_state (pdev, PCI_D3hot);
2616 static int rtl8139_resume (struct pci_dev *pdev)
2618 struct net_device *dev = pci_get_drvdata (pdev);
2620 pci_restore_state (pdev);
2621 if (!netif_running (dev))
2623 pci_set_power_state (pdev, PCI_D0);
2624 rtl8139_init_ring (dev);
2625 rtl8139_hw_start (dev);
2626 netif_device_attach (dev);
2630 #endif /* CONFIG_PM */
2633 static struct pci_driver rtl8139_pci_driver = {
2635 .id_table = rtl8139_pci_tbl,
2636 .probe = rtl8139_init_one,
2637 .remove = __devexit_p(rtl8139_remove_one),
2639 .suspend = rtl8139_suspend,
2640 .resume = rtl8139_resume,
2641 #endif /* CONFIG_PM */
2645 static int __init rtl8139_init_module (void)
2647 /* when we're a module, we always print a version message,
2648 * even if no 8139 board is found.
2651 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2654 return pci_module_init (&rtl8139_pci_driver);
2658 static void __exit rtl8139_cleanup_module (void)
2660 pci_unregister_driver (&rtl8139_pci_driver);
2664 module_init(rtl8139_init_module);
2665 module_exit(rtl8139_cleanup_module);