2 * Alchemy Semi Au1000 ethernet driver
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * ppopov@mvista.com or source@mvista.com
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/string.h>
26 #include <linux/timer.h>
27 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
40 #include <asm/mipsregs.h>
42 #include <asm/bitops.h>
44 #include <asm/au1000.h>
46 #include "au1000_eth.h"
48 #ifdef AU1000_ETH_DEBUG
49 static int au1000_debug = 10;
51 static int au1000_debug = 3;
55 static void *dma_alloc(size_t, dma_addr_t *);
56 static void dma_free(void *, size_t);
57 static void hard_stop(struct net_device *);
58 static void enable_rx_tx(struct net_device *dev);
59 static int __init au1000_probe1(long, int, int);
60 static int au1000_init(struct net_device *);
61 static int au1000_open(struct net_device *);
62 static int au1000_close(struct net_device *);
63 static int au1000_tx(struct sk_buff *, struct net_device *);
64 static int au1000_rx(struct net_device *);
65 static irqreturn_t au1000_interrupt(int, void *, struct pt_regs *);
66 static void au1000_tx_timeout(struct net_device *);
67 static int au1000_set_config(struct net_device *dev, struct ifmap *map);
68 static void set_rx_mode(struct net_device *);
69 static struct net_device_stats *au1000_get_stats(struct net_device *);
70 static inline void update_tx_stats(struct net_device *, u32, u32);
71 static inline void update_rx_stats(struct net_device *, u32);
72 static void au1000_timer(unsigned long);
73 static int au1000_ioctl(struct net_device *, struct ifreq *, int);
74 static int mdio_read(struct net_device *, int, int);
75 static void mdio_write(struct net_device *, int, int, u16);
76 static void dump_mii(struct net_device *dev, int phy_id);
79 extern void ack_rise_edge_irq(unsigned int);
80 extern int get_ethernet_addr(char *ethernet_addr);
81 extern inline void str2eaddr(unsigned char *ea, unsigned char *str);
82 extern inline unsigned char str2hexnum(unsigned char c);
83 extern char * __init prom_getcmdline(void);
88 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
89 * There are four receive and four transmit descriptors. These
90 * descriptors are not in memory; rather, they are just a set of
93 * Since the Au1000 has a coherent data cache, the receive and
94 * transmit buffers are allocated from the KSEG0 segment. The
95 * hardware registers, however, are still mapped at KSEG1 to
96 * make sure there's no out-of-order writes, and that all writes
97 * complete immediately.
102 * Base address and interrupt of the Au1xxx ethernet macs
107 } au1000_iflist[NUM_INTERFACES] = {
108 {AU1000_ETH0_BASE, AU1000_ETH0_IRQ},
109 {AU1000_ETH1_BASE, AU1000_ETH1_IRQ}
111 au1500_iflist[NUM_INTERFACES] = {
112 {AU1500_ETH0_BASE, AU1000_ETH0_IRQ},
113 {AU1500_ETH1_BASE, AU1000_ETH1_IRQ}
115 au1100_iflist[NUM_INTERFACES] = {
116 {AU1000_ETH0_BASE, AU1000_ETH0_IRQ},
120 static char version[] __devinitdata =
121 "au1000eth.c:1.0 ppopov@mvista.com\n";
123 /* These addresses are only used if yamon doesn't tell us what
124 * the mac address is, and the mac address is not passed on the
127 static unsigned char au1000_mac_addr[6] __devinitdata = {
128 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
131 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
132 #define RUN_AT(x) (jiffies + (x))
134 // For reading/writing 32-bit words from/to DMA memory
135 #define cpu_to_dma32 cpu_to_be32
136 #define dma32_to_cpu be32_to_cpu
140 * All of the PHY code really should be detached from the MAC
144 int bcm_5201_init(struct net_device *dev, int phy_addr)
148 /* Stop auto-negotiation */
149 //printk("bcm_5201_init\n");
150 data = mdio_read(dev, phy_addr, MII_CONTROL);
151 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
153 /* Set advertisement to 10/100 and Half/Full duplex
154 * (full capabilities) */
155 data = mdio_read(dev, phy_addr, MII_ANADV);
156 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
157 mdio_write(dev, phy_addr, MII_ANADV, data);
159 /* Restart auto-negotiation */
160 data = mdio_read(dev, phy_addr, MII_CONTROL);
161 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
162 mdio_write(dev, phy_addr, MII_CONTROL, data);
164 /* Enable TX LED instead of FDX */
165 data = mdio_read(dev, phy_addr, MII_INT);
166 data &= ~MII_FDX_LED;
167 mdio_write(dev, phy_addr, MII_INT, data);
169 /* Enable TX LED instead of FDX */
170 data = mdio_read(dev, phy_addr, MII_INT);
171 data &= ~MII_FDX_LED;
172 mdio_write(dev, phy_addr, MII_INT, data);
174 if (au1000_debug > 4) dump_mii(dev, phy_addr);
178 int bcm_5201_reset(struct net_device *dev, int phy_addr)
180 s16 mii_control, timeout;
182 //printk("bcm_5201_reset\n");
183 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
184 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
186 for (timeout = 100; timeout > 0; --timeout) {
187 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
188 if ((mii_control & MII_CNTL_RESET) == 0)
192 if (mii_control & MII_CNTL_RESET) {
193 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
200 bcm_5201_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
203 struct au1000_private *aup;
206 printk(KERN_ERR "bcm_5201_status error: NULL dev\n");
209 aup = (struct au1000_private *) dev->priv;
211 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
212 if (mii_data & MII_STAT_LINK) {
214 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
215 if (mii_data & MII_AUX_100) {
216 if (mii_data & MII_AUX_FDX) {
217 *speed = IF_PORT_100BASEFX;
218 dev->if_port = IF_PORT_100BASEFX;
221 *speed = IF_PORT_100BASETX;
222 dev->if_port = IF_PORT_100BASETX;
226 *speed = IF_PORT_10BASET;
227 dev->if_port = IF_PORT_10BASET;
234 dev->if_port = IF_PORT_UNKNOWN;
239 int lsi_80227_init(struct net_device *dev, int phy_addr)
241 if (au1000_debug > 4)
242 printk("lsi_80227_init\n");
244 /* restart auto-negotiation */
245 mdio_write(dev, phy_addr, 0, 0x3200);
249 /* set up LEDs to correct display */
250 mdio_write(dev, phy_addr, 17, 0xffc0);
252 if (au1000_debug > 4)
253 dump_mii(dev, phy_addr);
257 int lsi_80227_reset(struct net_device *dev, int phy_addr)
259 s16 mii_control, timeout;
261 if (au1000_debug > 4) {
262 printk("lsi_80227_reset\n");
263 dump_mii(dev, phy_addr);
266 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
267 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
269 for (timeout = 100; timeout > 0; --timeout) {
270 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
271 if ((mii_control & MII_CNTL_RESET) == 0)
275 if (mii_control & MII_CNTL_RESET) {
276 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
283 lsi_80227_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
286 struct au1000_private *aup;
289 printk(KERN_ERR "lsi_80227_status error: NULL dev\n");
292 aup = (struct au1000_private *) dev->priv;
294 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
295 if (mii_data & MII_STAT_LINK) {
297 mii_data = mdio_read(dev, aup->phy_addr, MII_LSI_STAT);
298 if (mii_data & MII_LSI_STAT_SPD) {
299 if (mii_data & MII_LSI_STAT_FDX) {
300 *speed = IF_PORT_100BASEFX;
301 dev->if_port = IF_PORT_100BASEFX;
304 *speed = IF_PORT_100BASETX;
305 dev->if_port = IF_PORT_100BASETX;
309 *speed = IF_PORT_10BASET;
310 dev->if_port = IF_PORT_10BASET;
317 dev->if_port = IF_PORT_UNKNOWN;
322 int am79c901_init(struct net_device *dev, int phy_addr)
324 printk("am79c901_init\n");
328 int am79c901_reset(struct net_device *dev, int phy_addr)
330 printk("am79c901_reset\n");
335 am79c901_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
340 struct phy_ops bcm_5201_ops = {
346 struct phy_ops am79c901_ops = {
352 struct phy_ops lsi_80227_ops = {
358 static struct mii_chip_info {
362 struct phy_ops *phy_ops;
363 } mii_chip_table[] = {
364 {"Broadcom BCM5201 10/100 BaseT PHY", 0x0040, 0x6212, &bcm_5201_ops },
365 {"AMD 79C901 HomePNA PHY", 0x0000, 0x35c8, &am79c901_ops },
366 {"LSI 80227 10/100 BaseT PHY", 0x0016, 0xf840, &lsi_80227_ops },
367 {"Broadcom BCM5221 10/100 BaseT PHY", 0x0040, 0x61e4, &bcm_5201_ops },
371 static int mdio_read(struct net_device *dev, int phy_id, int reg)
373 struct au1000_private *aup = (struct au1000_private *) dev->priv;
377 while (aup->mac->mii_control & MAC_MII_BUSY) {
379 if (--timedout == 0) {
380 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
386 mii_control = MAC_SET_MII_SELECT_REG(reg) |
387 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_READ;
389 aup->mac->mii_control = mii_control;
392 while (aup->mac->mii_control & MAC_MII_BUSY) {
394 if (--timedout == 0) {
395 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
400 return (int)aup->mac->mii_data;
403 static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 value)
405 struct au1000_private *aup = (struct au1000_private *) dev->priv;
409 while (aup->mac->mii_control & MAC_MII_BUSY) {
411 if (--timedout == 0) {
412 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
418 mii_control = MAC_SET_MII_SELECT_REG(reg) |
419 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_WRITE;
421 aup->mac->mii_data = value;
422 aup->mac->mii_control = mii_control;
426 static void dump_mii(struct net_device *dev, int phy_id)
430 for (i = 0; i < 7; i++) {
431 if ((val = mdio_read(dev, phy_id, i)) >= 0)
432 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
434 for (i = 16; i < 25; i++) {
435 if ((val = mdio_read(dev, phy_id, i)) >= 0)
436 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
440 static int __init mii_probe (struct net_device * dev)
442 struct au1000_private *aup = (struct au1000_private *) dev->priv;
447 /* search for total of 32 possible mii phy addresses */
448 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
450 u16 phy_id0, phy_id1;
453 mii_status = mdio_read(dev, phy_addr, MII_STATUS);
454 if (mii_status == 0xffff || mii_status == 0x0000)
455 /* the mii is not accessible, try next one */
458 phy_id0 = mdio_read(dev, phy_addr, MII_PHY_ID0);
459 phy_id1 = mdio_read(dev, phy_addr, MII_PHY_ID1);
461 /* search our mii table for the current mii */
462 for (i = 0; mii_chip_table[i].phy_id1; i++) {
463 if (phy_id0 == mii_chip_table[i].phy_id0 &&
464 phy_id1 == mii_chip_table[i].phy_id1) {
465 struct mii_phy * mii_phy;
467 printk(KERN_INFO "%s: %s at phy address %d\n",
468 dev->name, mii_chip_table[i].name,
470 mii_phy = kmalloc(sizeof(struct mii_phy),
473 mii_phy->chip_info = mii_chip_table+i;
474 mii_phy->phy_addr = phy_addr;
475 mii_phy->next = aup->mii;
477 mii_chip_table[i].phy_ops;
479 aup->phy_ops->phy_init(dev,phy_addr);
481 printk(KERN_ERR "%s: out of memory\n",
485 /* the current mii is on our mii_info_table,
492 if (aup->mii == NULL) {
493 printk(KERN_ERR "%s: No MII transceivers found!\n", dev->name);
498 aup->phy_addr = aup->mii->phy_addr;
499 printk(KERN_INFO "%s: Using %s as default\n",
500 dev->name, aup->mii->chip_info->name);
507 * Buffer allocation/deallocation routines. The buffer descriptor returned
508 * has the virtual and dma address of a buffer suitable for
509 * both, receive and transmit operations.
511 static db_dest_t *GetFreeDB(struct au1000_private *aup)
517 aup->pDBfree = pDB->pnext;
519 //printk("GetFreeDB: %x\n", pDB);
523 void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
525 db_dest_t *pDBfree = aup->pDBfree;
527 pDBfree->pnext = pDB;
533 DMA memory allocation, derived from pci_alloc_consistent.
534 However, the Au1000 data cache is coherent (when programmed
535 so), therefore we return KSEG0 address, not KSEG1.
537 static void *dma_alloc(size_t size, dma_addr_t * dma_handle)
540 int gfp = GFP_ATOMIC | GFP_DMA;
542 ret = (void *) __get_free_pages(gfp, get_order(size));
545 memset(ret, 0, size);
546 *dma_handle = virt_to_bus(ret);
547 ret = (void *)KSEG0ADDR(ret);
553 static void dma_free(void *vaddr, size_t size)
555 vaddr = (void *)KSEG0ADDR(vaddr);
556 free_pages((unsigned long) vaddr, get_order(size));
560 static void enable_rx_tx(struct net_device *dev)
562 struct au1000_private *aup = (struct au1000_private *) dev->priv;
564 if (au1000_debug > 4)
565 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
567 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
571 static void hard_stop(struct net_device *dev)
573 struct au1000_private *aup = (struct au1000_private *) dev->priv;
575 if (au1000_debug > 4)
576 printk(KERN_INFO "%s: hard stop\n", dev->name);
578 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
583 static void reset_mac(struct net_device *dev)
586 struct au1000_private *aup = (struct au1000_private *) dev->priv;
588 if (au1000_debug > 4)
589 printk(KERN_INFO "%s: reset mac, aup %x\n",
590 dev->name, (unsigned)aup);
592 spin_lock_irqsave(&aup->lock, flags);
593 del_timer(&aup->timer);
595 *aup->enable = MAC_EN_CLOCK_ENABLE;
600 spin_unlock_irqrestore(&aup->lock, flags);
605 * Setup the receive and transmit "rings". These pointers are the addresses
606 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
607 * these are not descriptors sitting in memory.
610 setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
614 for (i=0; i<NUM_RX_DMA; i++) {
615 aup->rx_dma_ring[i] =
616 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
618 for (i=0; i<NUM_TX_DMA; i++) {
619 aup->tx_dma_ring[i] =
620 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
624 static int __init au1000_init_module(void)
630 prid = read_c0_prid();
631 for (i=0; i<NUM_INTERFACES; i++) {
632 if ( (prid & 0xffff0000) == 0x00030000 ) {
633 base_addr = au1000_iflist[i].port;
634 irq = au1000_iflist[i].irq;
635 } else if ( (prid & 0xffff0000) == 0x01030000 ) {
636 base_addr = au1500_iflist[i].port;
637 irq = au1500_iflist[i].irq;
638 } else if ( (prid & 0xffff0000) == 0x02030000 ) {
639 base_addr = au1100_iflist[i].port;
640 irq = au1100_iflist[i].irq;
642 printk(KERN_ERR "au1000 eth: unknown Processor ID\n");
645 // check for valid entries, au1100 only has one entry
646 if (base_addr && irq) {
647 if (au1000_probe1(base_addr, irq, i) != 0)
655 au1000_probe1(long ioaddr, int irq, int port_num)
657 struct net_device *dev;
658 static unsigned version_printed = 0;
659 struct au1000_private *aup = NULL;
661 db_dest_t *pDB, *pDBfree;
665 if (!request_region(PHYSADDR(ioaddr), MAC_IOSIZE, "Au1000 ENET"))
668 if (version_printed++ == 0)
673 dev = alloc_etherdev(sizeof(struct au1000_private));
675 printk (KERN_ERR "au1000 eth: alloc_etherdev failed\n");
679 SET_MODULE_OWNER(dev);
681 printk("%s: Au1xxx ethernet found at 0x%lx, irq %d\n",
682 dev->name, ioaddr, irq);
686 /* Allocate the data buffers */
687 aup->vaddr = (u32)dma_alloc(MAX_BUF_SIZE *
688 (NUM_TX_BUFFS+NUM_RX_BUFFS), &aup->dma_addr);
692 /* aup->mac is the base address of the MAC's registers */
693 aup->mac = (volatile mac_reg_t *)((unsigned long)ioaddr);
694 /* Setup some variables for quick register address access */
696 case AU1000_ETH0_BASE:
697 case AU1500_ETH0_BASE:
698 /* check env variables first */
699 if (!get_ethernet_addr(ethaddr)) {
700 memcpy(au1000_mac_addr, ethaddr, sizeof(dev->dev_addr));
702 /* Check command line */
703 argptr = prom_getcmdline();
704 if ((pmac = strstr(argptr, "ethaddr=")) == NULL) {
705 printk(KERN_INFO "%s: No mac address found\n",
707 /* use the hard coded mac addresses */
709 str2eaddr(ethaddr, pmac + strlen("ethaddr="));
710 memcpy(au1000_mac_addr, ethaddr,
711 sizeof(dev->dev_addr));
714 if (ioaddr == AU1000_ETH0_BASE)
715 aup->enable = (volatile u32 *)
716 ((unsigned long)AU1000_MAC0_ENABLE);
718 aup->enable = (volatile u32 *)
719 ((unsigned long)AU1500_MAC0_ENABLE);
720 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(dev->dev_addr));
721 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
723 case AU1000_ETH1_BASE:
724 case AU1500_ETH1_BASE:
725 if (ioaddr == AU1000_ETH1_BASE)
726 aup->enable = (volatile u32 *)
727 ((unsigned long)AU1000_MAC1_ENABLE);
729 aup->enable = (volatile u32 *)
730 ((unsigned long)AU1500_MAC1_ENABLE);
731 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(dev->dev_addr));
732 dev->dev_addr[4] += 0x10;
733 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
736 printk(KERN_ERR "%s: bad ioaddr\n", dev->name);
741 aup->phy_addr = PHY_ADDRESS;
743 /* bring the device out of reset, otherwise probing the mii
745 *aup->enable = MAC_EN_CLOCK_ENABLE;
747 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 |
748 MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
751 retval = mii_probe(dev);
757 /* setup the data buffer descriptors and attach a buffer to each one */
759 for (i=0; i<(NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
760 pDB->pnext = pDBfree;
762 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
763 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
766 aup->pDBfree = pDBfree;
768 for (i=0; i<NUM_RX_DMA; i++) {
769 pDB = GetFreeDB(aup);
771 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
772 aup->rx_db_inuse[i] = pDB;
774 for (i=0; i<NUM_TX_DMA; i++) {
775 pDB = GetFreeDB(aup);
777 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
778 aup->tx_dma_ring[i]->len = 0;
779 aup->tx_db_inuse[i] = pDB;
782 spin_lock_init(&aup->lock);
783 dev->base_addr = ioaddr;
785 dev->open = au1000_open;
786 dev->hard_start_xmit = au1000_tx;
787 dev->stop = au1000_close;
788 dev->get_stats = au1000_get_stats;
789 dev->set_multicast_list = &set_rx_mode;
790 dev->do_ioctl = &au1000_ioctl;
791 dev->set_config = &au1000_set_config;
792 dev->tx_timeout = au1000_tx_timeout;
793 dev->watchdog_timeo = ETH_TX_TIMEOUT;
796 * The boot code uses the ethernet controller, so reset it to start
797 * fresh. au1000_init() expects that the device is in reset state.
801 retval = register_netdev(dev);
807 dma_free(aup->vaddr, MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS));
811 release_region(PHYSADDR(ioaddr), MAC_IOSIZE);
812 printk(KERN_ERR "%s: au1000_probe1 failed. Returns %d\n",
819 * Initialize the interface.
821 * When the device powers up, the clocks are disabled and the
822 * mac is in reset state. When the interface is closed, we
823 * do the same -- reset the device and disable the clocks to
824 * conserve power. Thus, whenever au1000_init() is called,
825 * the device should already be in reset state.
827 static int au1000_init(struct net_device *dev)
829 struct au1000_private *aup = (struct au1000_private *) dev->priv;
835 if (au1000_debug > 4) printk("%s: au1000_init\n", dev->name);
837 spin_lock_irqsave(&aup->lock, flags);
839 /* bring the device out of reset */
840 *aup->enable = MAC_EN_CLOCK_ENABLE;
842 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 |
843 MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
846 aup->mac->control = 0;
847 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
848 aup->tx_tail = aup->tx_head;
849 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
851 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
852 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
853 dev->dev_addr[1]<<8 | dev->dev_addr[0];
855 for (i=0; i<NUM_RX_DMA; i++) {
856 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
860 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
861 control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE;
862 #ifndef CONFIG_CPU_LITTLE_ENDIAN
863 control |= MAC_BIG_ENDIAN;
865 if (link && (dev->if_port == IF_PORT_100BASEFX)) {
866 control |= MAC_FULL_DUPLEX;
868 aup->mac->control = control;
871 spin_unlock_irqrestore(&aup->lock, flags);
875 static void au1000_timer(unsigned long data)
877 struct net_device *dev = (struct net_device *)data;
878 struct au1000_private *aup = (struct au1000_private *) dev->priv;
879 unsigned char if_port;
883 /* fatal error, don't restart the timer */
884 printk(KERN_ERR "au1000_timer error: NULL dev\n");
888 if_port = dev->if_port;
889 if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
891 if (!(dev->flags & IFF_RUNNING)) {
892 netif_carrier_on(dev);
893 dev->flags |= IFF_RUNNING;
894 printk(KERN_INFO "%s: link up\n", dev->name);
898 if (dev->flags & IFF_RUNNING) {
899 netif_carrier_off(dev);
900 dev->flags &= ~IFF_RUNNING;
902 printk(KERN_INFO "%s: link down\n", dev->name);
907 if (link && (dev->if_port != if_port) &&
908 (dev->if_port != IF_PORT_UNKNOWN)) {
910 if (dev->if_port == IF_PORT_100BASEFX) {
911 printk(KERN_INFO "%s: going to full duplex\n",
913 aup->mac->control |= MAC_FULL_DUPLEX;
917 aup->mac->control &= ~MAC_FULL_DUPLEX;
923 aup->timer.expires = RUN_AT((1*HZ));
924 aup->timer.data = (unsigned long)dev;
925 aup->timer.function = &au1000_timer; /* timer handler */
926 add_timer(&aup->timer);
930 static int au1000_open(struct net_device *dev)
933 struct au1000_private *aup = (struct au1000_private *) dev->priv;
935 if (au1000_debug > 4)
936 printk("%s: open: dev=%p\n", dev->name, dev);
938 if ((retval = au1000_init(dev))) {
939 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
940 free_irq(dev->irq, dev);
943 netif_start_queue(dev);
945 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
947 printk(KERN_ERR "%s: unable to get IRQ %d\n",
948 dev->name, dev->irq);
952 aup->timer.expires = RUN_AT((3*HZ));
953 aup->timer.data = (unsigned long)dev;
954 aup->timer.function = &au1000_timer; /* timer handler */
955 add_timer(&aup->timer);
957 if (au1000_debug > 4)
958 printk("%s: open: Initialization done.\n", dev->name);
963 static int au1000_close(struct net_device *dev)
966 struct au1000_private *aup = (struct au1000_private *) dev->priv;
968 if (au1000_debug > 4)
969 printk("%s: close: dev=%p\n", dev->name, dev);
971 spin_lock_irqsave(&aup->lock, flags);
973 /* stop the device */
974 if (netif_device_present(dev))
975 netif_stop_queue(dev);
977 /* disable the interrupt */
978 free_irq(dev->irq, dev);
979 spin_unlock_irqrestore(&aup->lock, flags);
985 static void __exit au1000_cleanup_module(void)
991 update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
993 struct au1000_private *aup = (struct au1000_private *) dev->priv;
994 struct net_device_stats *ps = &aup->stats;
997 ps->tx_bytes += pkt_len;
999 if (status & TX_FRAME_ABORTED) {
1000 if (dev->if_port == IF_PORT_100BASEFX) {
1001 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1002 /* any other tx errors are only valid
1003 * in half duplex mode */
1005 ps->tx_aborted_errors++;
1010 ps->tx_aborted_errors++;
1011 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1012 ps->tx_carrier_errors++;
1019 * Called from the interrupt service routine to acknowledge
1020 * the TX DONE bits. This is a must if the irq is setup as
1023 static void au1000_tx_ack(struct net_device *dev)
1025 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1026 volatile tx_dma_t *ptxd;
1028 ptxd = aup->tx_dma_ring[aup->tx_tail];
1030 while (ptxd->buff_stat & TX_T_DONE) {
1031 update_tx_stats(dev, ptxd->status, aup->tx_len[aup->tx_tail] & 0x3ff);
1032 ptxd->buff_stat &= ~TX_T_DONE;
1033 aup->tx_len[aup->tx_tail] = 0;
1037 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1038 ptxd = aup->tx_dma_ring[aup->tx_tail];
1042 netif_wake_queue(dev);
1049 * Au1000 transmit routine.
1051 static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1053 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1054 volatile tx_dma_t *ptxd;
1059 if (au1000_debug > 4)
1060 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1061 dev->name, (unsigned)aup, skb->len,
1062 skb->data, aup->tx_head);
1064 ptxd = aup->tx_dma_ring[aup->tx_head];
1065 buff_stat = ptxd->buff_stat;
1066 if (buff_stat & TX_DMA_ENABLE) {
1067 /* We've wrapped around and the transmitter is still busy */
1068 netif_stop_queue(dev);
1072 else if (buff_stat & TX_T_DONE) {
1073 update_tx_stats(dev, ptxd->status, aup->tx_len[aup->tx_head] & 0x3ff);
1074 aup->tx_len[aup->tx_head] = 0;
1080 netif_wake_queue(dev);
1083 pDB = aup->tx_db_inuse[aup->tx_head];
1084 memcpy((void *)pDB->vaddr, skb->data, skb->len);
1085 if (skb->len < MAC_MIN_PKT_SIZE) {
1086 for (i=skb->len; i<MAC_MIN_PKT_SIZE; i++) {
1087 ((char *)pDB->vaddr)[i] = 0;
1089 aup->tx_len[aup->tx_head] = MAC_MIN_PKT_SIZE;
1090 ptxd->len = MAC_MIN_PKT_SIZE;
1093 aup->tx_len[aup->tx_head] = skb->len;
1094 ptxd->len = skb->len;
1096 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1099 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1100 dev->trans_start = jiffies;
1105 static inline void update_rx_stats(struct net_device *dev, u32 status)
1107 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1108 struct net_device_stats *ps = &aup->stats;
1111 if (status & RX_MCAST_FRAME)
1114 if (status & RX_ERROR) {
1116 if (status & RX_MISSED_FRAME)
1117 ps->rx_missed_errors++;
1118 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1119 ps->rx_length_errors++;
1120 if (status & RX_CRC_ERROR)
1121 ps->rx_crc_errors++;
1122 if (status & RX_COLL)
1126 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1131 * Au1000 receive routine.
1133 static int au1000_rx(struct net_device *dev)
1135 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1136 struct sk_buff *skb;
1137 volatile rx_dma_t *prxd;
1138 u32 buff_stat, status;
1141 if (au1000_debug > 4)
1142 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1144 prxd = aup->rx_dma_ring[aup->rx_head];
1145 buff_stat = prxd->buff_stat;
1146 while (buff_stat & RX_T_DONE) {
1147 status = prxd->status;
1148 pDB = aup->rx_db_inuse[aup->rx_head];
1149 update_rx_stats(dev, status);
1150 if (!(status & RX_ERROR)) {
1153 skb = dev_alloc_skb((status & RX_FRAME_LEN_MASK) + 2);
1156 "%s: Memory squeeze, dropping packet.\n",
1158 aup->stats.rx_dropped++;
1162 skb_reserve(skb, 2); /* 16 byte IP header align */
1163 eth_copy_and_sum(skb, (unsigned char *)pDB->vaddr,
1164 status & RX_FRAME_LEN_MASK, 0);
1165 skb_put(skb, status & RX_FRAME_LEN_MASK);
1166 skb->protocol = eth_type_trans(skb, dev);
1167 netif_rx(skb); /* pass the packet to upper layers */
1170 if (au1000_debug > 4) {
1171 if (status & RX_MISSED_FRAME)
1172 printk("rx miss\n");
1173 if (status & RX_WDOG_TIMER)
1174 printk("rx wdog\n");
1175 if (status & RX_RUNT)
1176 printk("rx runt\n");
1177 if (status & RX_OVERLEN)
1178 printk("rx overlen\n");
1179 if (status & RX_COLL)
1180 printk("rx coll\n");
1181 if (status & RX_MII_ERROR)
1182 printk("rx mii error\n");
1183 if (status & RX_CRC_ERROR)
1184 printk("rx crc error\n");
1185 if (status & RX_LEN_ERROR)
1186 printk("rx len error\n");
1187 if (status & RX_U_CNTRL_FRAME)
1188 printk("rx u control frame\n");
1189 if (status & RX_MISSED_FRAME)
1190 printk("rx miss\n");
1193 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1194 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
1197 /* next descriptor */
1198 prxd = aup->rx_dma_ring[aup->rx_head];
1199 buff_stat = prxd->buff_stat;
1200 dev->last_rx = jiffies;
1207 * Au1000 interrupt service routine.
1209 irqreturn_t au1000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1211 struct net_device *dev = (struct net_device *) dev_id;
1214 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
1224 * The Tx ring has been full longer than the watchdog timeout
1225 * value. The transmitter must be hung?
1227 static void au1000_tx_timeout(struct net_device *dev)
1229 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
1232 dev->trans_start = jiffies;
1233 netif_wake_queue(dev);
1236 static void set_rx_mode(struct net_device *dev)
1238 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1240 if (au1000_debug > 4)
1241 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
1243 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1244 aup->mac->control |= MAC_PROMISCUOUS;
1245 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1246 } else if ((dev->flags & IFF_ALLMULTI) ||
1247 dev->mc_count > MULTICAST_FILTER_LIMIT) {
1248 aup->mac->control |= MAC_PASS_ALL_MULTI;
1249 aup->mac->control &= ~MAC_PROMISCUOUS;
1250 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
1253 struct dev_mc_list *mclist;
1254 u32 mc_filter[2]; /* Multicast hash filter */
1256 mc_filter[1] = mc_filter[0] = 0;
1257 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1258 i++, mclist = mclist->next) {
1259 set_bit(ether_crc_le(ETH_ALEN, mclist->dmi_addr)>>26,
1262 aup->mac->multi_hash_high = mc_filter[1];
1263 aup->mac->multi_hash_low = mc_filter[0];
1264 aup->mac->control &= ~MAC_PROMISCUOUS;
1265 aup->mac->control |= MAC_HASH_MODE;
1270 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1272 u16 *data = (u16 *)&rq->ifr_data;
1276 case SIOCGMIIPHY: /* Get the address of the PHY in use. */
1277 data[0] = PHY_ADDRESS;
1280 case SIOCGMIIREG: /* Read the specified MII register. */
1281 //data[3] = mdio_read(ioaddr, data[0], data[1]);
1284 case SIOCSMIIREG: /* Write the specified MII register */
1285 if (!capable(CAP_NET_ADMIN))
1288 //mdio_write(ioaddr, data[0], data[1], data[2]);
1297 static int au1000_set_config(struct net_device *dev, struct ifmap *map)
1299 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1302 if (au1000_debug > 4) {
1303 printk("%s: set_config called: dev->if_port %d map->port %x\n",
1304 dev->name, dev->if_port, map->port);
1308 case IF_PORT_UNKNOWN: /* use auto here */
1309 printk(KERN_INFO "%s: config phy for aneg\n",
1311 dev->if_port = map->port;
1312 /* Link Down: the timer will bring it up */
1313 netif_carrier_off(dev);
1315 /* read current control */
1316 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1317 control &= ~(MII_CNTL_FDX | MII_CNTL_F100);
1319 /* enable auto negotiation and reset the negotiation */
1320 mdio_write(dev, aup->phy_addr, MII_CONTROL,
1321 control | MII_CNTL_AUTO |
1326 case IF_PORT_10BASET: /* 10BaseT */
1327 printk(KERN_INFO "%s: config phy for 10BaseT\n",
1329 dev->if_port = map->port;
1331 /* Link Down: the timer will bring it up */
1332 netif_carrier_off(dev);
1334 /* set Speed to 10Mbps, Half Duplex */
1335 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1336 control &= ~(MII_CNTL_F100 | MII_CNTL_AUTO |
1339 /* disable auto negotiation and force 10M/HD mode*/
1340 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1343 case IF_PORT_100BASET: /* 100BaseT */
1344 case IF_PORT_100BASETX: /* 100BaseTx */
1345 printk(KERN_INFO "%s: config phy for 100BaseTX\n",
1347 dev->if_port = map->port;
1349 /* Link Down: the timer will bring it up */
1350 netif_carrier_off(dev);
1352 /* set Speed to 100Mbps, Half Duplex */
1353 /* disable auto negotiation and enable 100MBit Mode */
1354 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1355 printk("read control %x\n", control);
1356 control &= ~(MII_CNTL_AUTO | MII_CNTL_FDX);
1357 control |= MII_CNTL_F100;
1358 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1361 case IF_PORT_100BASEFX: /* 100BaseFx */
1362 printk(KERN_INFO "%s: config phy for 100BaseFX\n",
1364 dev->if_port = map->port;
1366 /* Link Down: the timer will bring it up */
1367 netif_carrier_off(dev);
1369 /* set Speed to 100Mbps, Full Duplex */
1370 /* disable auto negotiation and enable 100MBit Mode */
1371 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1372 control &= ~MII_CNTL_AUTO;
1373 control |= MII_CNTL_F100 | MII_CNTL_FDX;
1374 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1376 case IF_PORT_10BASE2: /* 10Base2 */
1377 case IF_PORT_AUI: /* AUI */
1378 /* These Modes are not supported (are they?)*/
1379 printk(KERN_ERR "%s: 10Base2/AUI not supported",
1385 printk(KERN_ERR "%s: Invalid media selected",
1392 static struct net_device_stats *au1000_get_stats(struct net_device *dev)
1394 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1396 if (au1000_debug > 4)
1397 printk("%s: au1000_get_stats: dev=%p\n", dev->name, dev);
1399 if (netif_device_present(dev)) {
1405 module_init(au1000_init_module);
1406 module_exit(au1000_cleanup_module);