drivers/net/b44.c

   1 /* b44.c: Broadcom 4400 device driver.
   2  *
   3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   4  * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
   5  *
   6  * Distribute under GPL.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/types.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/mii.h>
  16 #include <linux/if_ether.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/pci.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/version.h>
  22
  23 #include <asm/uaccess.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26
  27 #include "b44.h"
  28
  29 #define DRV_MODULE_NAME         "b44"
  30 #define PFX DRV_MODULE_NAME     ": "
  31 #define DRV_MODULE_VERSION      "0.95"
  32 #define DRV_MODULE_RELDATE      "Aug 3, 2004"
  33
  34 #define B44_DEF_MSG_ENABLE        \
  35         (NETIF_MSG_DRV          | \
  36          NETIF_MSG_PROBE        | \
  37          NETIF_MSG_LINK         | \
  38          NETIF_MSG_TIMER        | \
  39          NETIF_MSG_IFDOWN       | \
  40          NETIF_MSG_IFUP         | \
  41          NETIF_MSG_RX_ERR       | \
  42          NETIF_MSG_TX_ERR)
  43
  44 /* length of time before we decide the hardware is borked,
  45  * and dev->tx_timeout() should be called to fix the problem
  46  */
  47 #define B44_TX_TIMEOUT                  (5 * HZ)
  48
  49 /* hardware minimum and maximum for a single frame's data payload */
  50 #define B44_MIN_MTU                     60
  51 #define B44_MAX_MTU                     1500
  52
  53 #define B44_RX_RING_SIZE                512
  54 #define B44_DEF_RX_RING_PENDING         200
  55 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
  56                                  B44_RX_RING_SIZE)
  57 #define B44_TX_RING_SIZE                512
  58 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
  59 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
  60                                  B44_TX_RING_SIZE)
  61 #define B44_DMA_MASK 0x3fffffff
  62
  63 #define TX_RING_GAP(BP) \
  64         (B44_TX_RING_SIZE - (BP)->tx_pending)
  65 #define TX_BUFFS_AVAIL(BP)                                              \
  66         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
  67           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
  68           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
  69 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
  70
  71 #define RX_PKT_BUF_SZ           (1536 + bp->rx_offset + 64)
  72 #define TX_PKT_BUF_SZ           (B44_MAX_MTU + ETH_HLEN + 8)
  73
  74 /* minimum number of free TX descriptors required to wake up TX process */
  75 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
  76
  77 static char version[] __devinitdata =
  78         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  79
  80 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
  81 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  82 MODULE_LICENSE("GPL");
  83 MODULE_VERSION(DRV_MODULE_VERSION);
  84
  85 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
  86 module_param(b44_debug, int, 0);
  87 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  88 MODULE_VERSION(DRV_MODULE_VERSION);
  89
  90 static struct pci_device_id b44_pci_tbl[] = {
  91         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
  92           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  93         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
  94           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  95         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  96           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  97         { }     /* terminate list with empty entry */
  98 };
  99
 100 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
 101
 102 static void b44_halt(struct b44 *);
 103 static void b44_init_rings(struct b44 *);
 104 static void b44_init_hw(struct b44 *);
 105 static int b44_poll(struct net_device *dev, int *budget);
 106 #ifdef CONFIG_NET_POLL_CONTROLLER
 107 static void b44_poll_controller(struct net_device *dev);
 108 #endif
 109
 110 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
 111 {
 112         return readl(bp->regs + reg);
 113 }
 114
 115 static inline void bw32(const struct b44 *bp,
 116                         unsigned long reg, unsigned long val)
 117 {
 118         writel(val, bp->regs + reg);
 119 }
 120
 121 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 122                         u32 bit, unsigned long timeout, const int clear)
 123 {
 124         unsigned long i;
 125
 126         for (i = 0; i < timeout; i++) {
 127                 u32 val = br32(bp, reg);
 128
 129                 if (clear && !(val & bit))
 130                         break;
 131                 if (!clear && (val & bit))
 132                         break;
 133                 udelay(10);
 134         }
 135         if (i == timeout) {
 136                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
 137                        "%lx to %s.\n",
 138                        bp->dev->name,
 139                        bit, reg,
 140                        (clear ? "clear" : "set"));
 141                 return -ENODEV;
 142         }
 143         return 0;
 144 }
 145
 146 /* Sonics SiliconBackplane support routines.  ROFL, you should see all the
 147  * buzz words used on this company's website :-)
 148  *
 149  * All of these routines must be invoked with bp->lock held and
 150  * interrupts disabled.
 151  */
 152
 153 #define SB_PCI_DMA             0x40000000      /* Client Mode PCI memory access space (1 GB) */
 154 #define BCM4400_PCI_CORE_ADDR  0x18002000      /* Address of PCI core on BCM4400 cards */
 155
 156 static u32 ssb_get_core_rev(struct b44 *bp)
 157 {
 158         return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
 159 }
 160
 161 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
 162 {
 163         u32 bar_orig, pci_rev, val;
 164
 165         pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
 166         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
 167         pci_rev = ssb_get_core_rev(bp);
 168
 169         val = br32(bp, B44_SBINTVEC);
 170         val |= cores;
 171         bw32(bp, B44_SBINTVEC, val);
 172
 173         val = br32(bp, SSB_PCI_TRANS_2);
 174         val |= SSB_PCI_PREF | SSB_PCI_BURST;
 175         bw32(bp, SSB_PCI_TRANS_2, val);
 176
 177         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
 178
 179         return pci_rev;
 180 }
 181
 182 static void ssb_core_disable(struct b44 *bp)
 183 {
 184         if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
 185                 return;
 186
 187         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
 188         b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
 189         b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
 190         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 191                             SBTMSLOW_REJECT | SBTMSLOW_RESET));
 192         br32(bp, B44_SBTMSLOW);
 193         udelay(1);
 194         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 195         br32(bp, B44_SBTMSLOW);
 196         udelay(1);
 197 }
 198
 199 static void ssb_core_reset(struct b44 *bp)
 200 {
 201         u32 val;
 202
 203         ssb_core_disable(bp);
 204         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 205         br32(bp, B44_SBTMSLOW);
 206         udelay(1);
 207
 208         /* Clear SERR if set, this is a hw bug workaround.  */
 209         if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 210                 bw32(bp, B44_SBTMSHIGH, 0);
 211
 212         val = br32(bp, B44_SBIMSTATE);
 213         if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 214                 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 215
 216         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 217         br32(bp, B44_SBTMSLOW);
 218         udelay(1);
 219
 220         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 221         br32(bp, B44_SBTMSLOW);
 222         udelay(1);
 223 }
 224
 225 static int ssb_core_unit(struct b44 *bp)
 226 {
 227 #if 0
 228         u32 val = br32(bp, B44_SBADMATCH0);
 229         u32 base;
 230
 231         type = val & SBADMATCH0_TYPE_MASK;
 232         switch (type) {
 233         case 0:
 234                 base = val & SBADMATCH0_BS0_MASK;
 235                 break;
 236
 237         case 1:
 238                 base = val & SBADMATCH0_BS1_MASK;
 239                 break;
 240
 241         case 2:
 242         default:
 243                 base = val & SBADMATCH0_BS2_MASK;
 244                 break;
 245         };
 246 #endif
 247         return 0;
 248 }
 249
 250 static int ssb_is_core_up(struct b44 *bp)
 251 {
 252         return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 253                 == SBTMSLOW_CLOCK);
 254 }
 255
 256 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 257 {
 258         u32 val;
 259
 260         val  = ((u32) data[2]) << 24;
 261         val |= ((u32) data[3]) << 16;
 262         val |= ((u32) data[4]) <<  8;
 263         val |= ((u32) data[5]) <<  0;
 264         bw32(bp, B44_CAM_DATA_LO, val);
 265         val = (CAM_DATA_HI_VALID |
 266                (((u32) data[0]) << 8) |
 267                (((u32) data[1]) << 0));
 268         bw32(bp, B44_CAM_DATA_HI, val);
 269         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 270                             (index << CAM_CTRL_INDEX_SHIFT)));
 271         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 272 }
 273
 274 static inline void __b44_disable_ints(struct b44 *bp)
 275 {
 276         bw32(bp, B44_IMASK, 0);
 277 }
 278
 279 static void b44_disable_ints(struct b44 *bp)
 280 {
 281         __b44_disable_ints(bp);
 282
 283         /* Flush posted writes. */
 284         br32(bp, B44_IMASK);
 285 }
 286
 287 static void b44_enable_ints(struct b44 *bp)
 288 {
 289         bw32(bp, B44_IMASK, bp->imask);
 290 }
 291
 292 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 293 {
 294         int err;
 295
 296         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 297         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 298                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 299                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 300                              (reg << MDIO_DATA_RA_SHIFT) |
 301                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 302         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 303         *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 304
 305         return err;
 306 }
 307
 308 static int b44_writephy(struct b44 *bp, int reg, u32 val)
 309 {
 310         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 311         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 312                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 313                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 314                              (reg << MDIO_DATA_RA_SHIFT) |
 315                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 316                              (val & MDIO_DATA_DATA)));
 317         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 318 }
 319
 320 /* miilib interface */
 321 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
 322  * due to code existing before miilib use was added to this driver.
 323  * Someone should remove this artificial driver limitation in
 324  * b44_{read,write}phy.  bp->phy_addr itself is fine (and needed).
 325  */
 326 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
 327 {
 328         u32 val;
 329         struct b44 *bp = netdev_priv(dev);
 330         int rc = b44_readphy(bp, location, &val);
 331         if (rc)
 332                 return 0xffffffff;
 333         return val;
 334 }
 335
 336 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
 337                          int val)
 338 {
 339         struct b44 *bp = netdev_priv(dev);
 340         b44_writephy(bp, location, val);
 341 }
 342
 343 static int b44_phy_reset(struct b44 *bp)
 344 {
 345         u32 val;
 346         int err;
 347
 348         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 349         if (err)
 350                 return err;
 351         udelay(100);
 352         err = b44_readphy(bp, MII_BMCR, &val);
 353         if (!err) {
 354                 if (val & BMCR_RESET) {
 355                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
 356                                bp->dev->name);
 357                         err = -ENODEV;
 358                 }
 359         }
 360
 361         return 0;
 362 }
 363
 364 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
 365 {
 366         u32 val;
 367
 368         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 369         bp->flags |= pause_flags;
 370
 371         val = br32(bp, B44_RXCONFIG);
 372         if (pause_flags & B44_FLAG_RX_PAUSE)
 373                 val |= RXCONFIG_FLOW;
 374         else
 375                 val &= ~RXCONFIG_FLOW;
 376         bw32(bp, B44_RXCONFIG, val);
 377
 378         val = br32(bp, B44_MAC_FLOW);
 379         if (pause_flags & B44_FLAG_TX_PAUSE)
 380                 val |= (MAC_FLOW_PAUSE_ENAB |
 381                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 382         else
 383                 val &= ~MAC_FLOW_PAUSE_ENAB;
 384         bw32(bp, B44_MAC_FLOW, val);
 385 }
 386
 387 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 388 {
 389         u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
 390                                       B44_FLAG_RX_PAUSE);
 391
 392         if (local & ADVERTISE_PAUSE_CAP) {
 393                 if (local & ADVERTISE_PAUSE_ASYM) {
 394                         if (remote & LPA_PAUSE_CAP)
 395                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 396                                                B44_FLAG_RX_PAUSE);
 397                         else if (remote & LPA_PAUSE_ASYM)
 398                                 pause_enab |= B44_FLAG_RX_PAUSE;
 399                 } else {
 400                         if (remote & LPA_PAUSE_CAP)
 401                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 402                                                B44_FLAG_RX_PAUSE);
 403                 }
 404         } else if (local & ADVERTISE_PAUSE_ASYM) {
 405                 if ((remote & LPA_PAUSE_CAP) &&
 406                     (remote & LPA_PAUSE_ASYM))
 407                         pause_enab |= B44_FLAG_TX_PAUSE;
 408         }
 409
 410         __b44_set_flow_ctrl(bp, pause_enab);
 411 }
 412
 413 static int b44_setup_phy(struct b44 *bp)
 414 {
 415         u32 val;
 416         int err;
 417
 418         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 419                 goto out;
 420         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 421                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
 422                 goto out;
 423         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
 424                 goto out;
 425         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
 426                                 val | MII_TLEDCTRL_ENABLE)) != 0)
 427                 goto out;
 428
 429         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
 430                 u32 adv = ADVERTISE_CSMA;
 431
 432                 if (bp->flags & B44_FLAG_ADV_10HALF)
 433                         adv |= ADVERTISE_10HALF;
 434                 if (bp->flags & B44_FLAG_ADV_10FULL)
 435                         adv |= ADVERTISE_10FULL;
 436                 if (bp->flags & B44_FLAG_ADV_100HALF)
 437                         adv |= ADVERTISE_100HALF;
 438                 if (bp->flags & B44_FLAG_ADV_100FULL)
 439                         adv |= ADVERTISE_100FULL;
 440
 441                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
 442                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 443
 444                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
 445                         goto out;
 446                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
 447                                                        BMCR_ANRESTART))) != 0)
 448                         goto out;
 449         } else {
 450                 u32 bmcr;
 451
 452                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
 453                         goto out;
 454                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
 455                 if (bp->flags & B44_FLAG_100_BASE_T)
 456                         bmcr |= BMCR_SPEED100;
 457                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
 458                         bmcr |= BMCR_FULLDPLX;
 459                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
 460                         goto out;
 461
 462                 /* Since we will not be negotiating there is no safe way
 463                  * to determine if the link partner supports flow control
 464                  * or not.  So just disable it completely in this case.
 465                  */
 466                 b44_set_flow_ctrl(bp, 0, 0);
 467         }
 468
 469 out:
 470         return err;
 471 }
 472
 473 static void b44_stats_update(struct b44 *bp)
 474 {
 475         unsigned long reg;
 476         u32 *val;
 477
 478         val = &bp->hw_stats.tx_good_octets;
 479         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 480                 *val++ += br32(bp, reg);
 481         }
 482         val = &bp->hw_stats.rx_good_octets;
 483         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 484                 *val++ += br32(bp, reg);
 485         }
 486 }
 487
 488 static void b44_link_report(struct b44 *bp)
 489 {
 490         if (!netif_carrier_ok(bp->dev)) {
 491                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
 492         } else {
 493                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
 494                        bp->dev->name,
 495                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
 496                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
 497
 498                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
 499                        "%s for RX.\n",
 500                        bp->dev->name,
 501                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
 502                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
 503         }
 504 }
 505
 506 static void b44_check_phy(struct b44 *bp)
 507 {
 508         u32 bmsr, aux;
 509
 510         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 511             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 512             (bmsr != 0xffff)) {
 513                 if (aux & MII_AUXCTRL_SPEED)
 514                         bp->flags |= B44_FLAG_100_BASE_T;
 515                 else
 516                         bp->flags &= ~B44_FLAG_100_BASE_T;
 517                 if (aux & MII_AUXCTRL_DUPLEX)
 518                         bp->flags |= B44_FLAG_FULL_DUPLEX;
 519                 else
 520                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
 521
 522                 if (!netif_carrier_ok(bp->dev) &&
 523                     (bmsr & BMSR_LSTATUS)) {
 524                         u32 val = br32(bp, B44_TX_CTRL);
 525                         u32 local_adv, remote_adv;
 526
 527                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 528                                 val |= TX_CTRL_DUPLEX;
 529                         else
 530                                 val &= ~TX_CTRL_DUPLEX;
 531                         bw32(bp, B44_TX_CTRL, val);
 532
 533                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 534                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 535                             !b44_readphy(bp, MII_LPA, &remote_adv))
 536                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
 537
 538                         /* Link now up */
 539                         netif_carrier_on(bp->dev);
 540                         b44_link_report(bp);
 541                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
 542                         /* Link now down */
 543                         netif_carrier_off(bp->dev);
 544                         b44_link_report(bp);
 545                 }
 546
 547                 if (bmsr & BMSR_RFAULT)
 548                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
 549                                bp->dev->name);
 550                 if (bmsr & BMSR_JCD)
 551                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
 552                                bp->dev->name);
 553         }
 554 }
 555
 556 static void b44_timer(unsigned long __opaque)
 557 {
 558         struct b44 *bp = (struct b44 *) __opaque;
 559
 560         spin_lock_irq(&bp->lock);
 561
 562         b44_check_phy(bp);
 563
 564         b44_stats_update(bp);
 565
 566         spin_unlock_irq(&bp->lock);
 567
 568         bp->timer.expires = jiffies + HZ;
 569         add_timer(&bp->timer);
 570 }
 571
 572 static void b44_tx(struct b44 *bp)
 573 {
 574         u32 cur, cons;
 575
 576         cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 577         cur /= sizeof(struct dma_desc);
 578
 579         /* XXX needs updating when NETIF_F_SG is supported */
 580         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
 581                 struct ring_info *rp = &bp->tx_buffers[cons];
 582                 struct sk_buff *skb = rp->skb;
 583
 584                 if (unlikely(skb == NULL))
 585                         BUG();
 586
 587                 pci_unmap_single(bp->pdev,
 588                                  pci_unmap_addr(rp, mapping),
 589                                  skb->len,
 590                                  PCI_DMA_TODEVICE);
 591                 rp->skb = NULL;
 592                 dev_kfree_skb_irq(skb);
 593         }
 594
 595         bp->tx_cons = cons;
 596         if (netif_queue_stopped(bp->dev) &&
 597             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 598                 netif_wake_queue(bp->dev);
 599
 600         bw32(bp, B44_GPTIMER, 0);
 601 }
 602
 603 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 604  * before the DMA address you give it.  So we allocate 30 more bytes
 605  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 606  * point the chip at 30 bytes past where the rx_header will go.
 607  */
 608 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 609 {
 610         struct dma_desc *dp;
 611         struct ring_info *src_map, *map;
 612         struct rx_header *rh;
 613         struct sk_buff *skb;
 614         dma_addr_t mapping;
 615         int dest_idx;
 616         u32 ctrl;
 617
 618         src_map = NULL;
 619         if (src_idx >= 0)
 620                 src_map = &bp->rx_buffers[src_idx];
 621         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 622         map = &bp->rx_buffers[dest_idx];
 623         skb = dev_alloc_skb(RX_PKT_BUF_SZ);
 624         if (skb == NULL)
 625                 return -ENOMEM;
 626
 627         mapping = pci_map_single(bp->pdev, skb->data,
 628                                  RX_PKT_BUF_SZ,
 629                                  PCI_DMA_FROMDEVICE);
 630
 631         /* Hardware bug work-around, the chip is unable to do PCI DMA
 632            to/from anything above 1GB :-( */
 633         if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
 634                 /* Sigh... */
 635                 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 636                 dev_kfree_skb_any(skb);
 637                 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
 638                 if (skb == NULL)
 639                         return -ENOMEM;
 640                 mapping = pci_map_single(bp->pdev, skb->data,
 641                                          RX_PKT_BUF_SZ,
 642                                          PCI_DMA_FROMDEVICE);
 643                 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
 644                         pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 645                         dev_kfree_skb_any(skb);
 646                         return -ENOMEM;
 647                 }
 648         }
 649
 650         skb->dev = bp->dev;
 651         skb_reserve(skb, bp->rx_offset);
 652
 653         rh = (struct rx_header *)
 654                 (skb->data - bp->rx_offset);
 655         rh->len = 0;
 656         rh->flags = 0;
 657
 658         map->skb = skb;
 659         pci_unmap_addr_set(map, mapping, mapping);
 660
 661         if (src_map != NULL)
 662                 src_map->skb = NULL;
 663
 664         ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
 665         if (dest_idx == (B44_RX_RING_SIZE - 1))
 666                 ctrl |= DESC_CTRL_EOT;
 667
 668         dp = &bp->rx_ring[dest_idx];
 669         dp->ctrl = cpu_to_le32(ctrl);
 670         dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
 671
 672         return RX_PKT_BUF_SZ;
 673 }
 674
 675 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 676 {
 677         struct dma_desc *src_desc, *dest_desc;
 678         struct ring_info *src_map, *dest_map;
 679         struct rx_header *rh;
 680         int dest_idx;
 681         u32 ctrl;
 682
 683         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 684         dest_desc = &bp->rx_ring[dest_idx];
 685         dest_map = &bp->rx_buffers[dest_idx];
 686         src_desc = &bp->rx_ring[src_idx];
 687         src_map = &bp->rx_buffers[src_idx];
 688
 689         dest_map->skb = src_map->skb;
 690         rh = (struct rx_header *) src_map->skb->data;
 691         rh->len = 0;
 692         rh->flags = 0;
 693         pci_unmap_addr_set(dest_map, mapping,
 694                            pci_unmap_addr(src_map, mapping));
 695
 696         ctrl = src_desc->ctrl;
 697         if (dest_idx == (B44_RX_RING_SIZE - 1))
 698                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
 699         else
 700                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
 701
 702         dest_desc->ctrl = ctrl;
 703         dest_desc->addr = src_desc->addr;
 704         src_map->skb = NULL;
 705
 706         pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
 707                                        RX_PKT_BUF_SZ,
 708                                        PCI_DMA_FROMDEVICE);
 709 }
 710
 711 static int b44_rx(struct b44 *bp, int budget)
 712 {
 713         int received;
 714         u32 cons, prod;
 715
 716         received = 0;
 717         prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 718         prod /= sizeof(struct dma_desc);
 719         cons = bp->rx_cons;
 720
 721         while (cons != prod && budget > 0) {
 722                 struct ring_info *rp = &bp->rx_buffers[cons];
 723                 struct sk_buff *skb = rp->skb;
 724                 dma_addr_t map = pci_unmap_addr(rp, mapping);
 725                 struct rx_header *rh;
 726                 u16 len;
 727
 728                 pci_dma_sync_single_for_cpu(bp->pdev, map,
 729                                             RX_PKT_BUF_SZ,
 730                                             PCI_DMA_FROMDEVICE);
 731                 rh = (struct rx_header *) skb->data;
 732                 len = cpu_to_le16(rh->len);
 733                 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
 734                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
 735                 drop_it:
 736                         b44_recycle_rx(bp, cons, bp->rx_prod);
 737                 drop_it_no_recycle:
 738                         bp->stats.rx_dropped++;
 739                         goto next_pkt;
 740                 }
 741
 742                 if (len == 0) {
 743                         int i = 0;
 744
 745                         do {
 746                                 udelay(2);
 747                                 barrier();
 748                                 len = cpu_to_le16(rh->len);
 749                         } while (len == 0 && i++ < 5);
 750                         if (len == 0)
 751                                 goto drop_it;
 752                 }
 753
 754                 /* Omit CRC. */
 755                 len -= 4;
 756
 757                 if (len > RX_COPY_THRESHOLD) {
 758                         int skb_size;
 759                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 760                         if (skb_size < 0)
 761                                 goto drop_it;
 762                         pci_unmap_single(bp->pdev, map,
 763                                          skb_size, PCI_DMA_FROMDEVICE);
 764                         /* Leave out rx_header */
 765                         skb_put(skb, len+bp->rx_offset);
 766                         skb_pull(skb,bp->rx_offset);
 767                 } else {
 768                         struct sk_buff *copy_skb;
 769
 770                         b44_recycle_rx(bp, cons, bp->rx_prod);
 771                         copy_skb = dev_alloc_skb(len + 2);
 772                         if (copy_skb == NULL)
 773                                 goto drop_it_no_recycle;
 774
 775                         copy_skb->dev = bp->dev;
 776                         skb_reserve(copy_skb, 2);
 777                         skb_put(copy_skb, len);
 778                         /* DMA sync done above, copy just the actual packet */
 779                         memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
 780
 781                         skb = copy_skb;
 782                 }
 783                 skb->ip_summed = CHECKSUM_NONE;
 784                 skb->protocol = eth_type_trans(skb, bp->dev);
 785                 netif_receive_skb(skb);
 786                 bp->dev->last_rx = jiffies;
 787                 received++;
 788                 budget--;
 789         next_pkt:
 790                 bp->rx_prod = (bp->rx_prod + 1) &
 791                         (B44_RX_RING_SIZE - 1);
 792                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
 793         }
 794
 795         bp->rx_cons = cons;
 796         bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 797
 798         return received;
 799 }
 800
 801 static int b44_poll(struct net_device *netdev, int *budget)
 802 {
 803         struct b44 *bp = netdev_priv(netdev);
 804         int done;
 805
 806         spin_lock_irq(&bp->lock);
 807
 808         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 809                 /* spin_lock(&bp->tx_lock); */
 810                 b44_tx(bp);
 811                 /* spin_unlock(&bp->tx_lock); */
 812         }
 813         spin_unlock_irq(&bp->lock);
 814
 815         done = 1;
 816         if (bp->istat & ISTAT_RX) {
 817                 int orig_budget = *budget;
 818                 int work_done;
 819
 820                 if (orig_budget > netdev->quota)
 821                         orig_budget = netdev->quota;
 822
 823                 work_done = b44_rx(bp, orig_budget);
 824
 825                 *budget -= work_done;
 826                 netdev->quota -= work_done;
 827
 828                 if (work_done >= orig_budget)
 829                         done = 0;
 830         }
 831
 832         if (bp->istat & ISTAT_ERRORS) {
 833                 spin_lock_irq(&bp->lock);
 834                 b44_halt(bp);
 835                 b44_init_rings(bp);
 836                 b44_init_hw(bp);
 837                 netif_wake_queue(bp->dev);
 838                 spin_unlock_irq(&bp->lock);
 839                 done = 1;
 840         }
 841
 842         if (done) {
 843                 netif_rx_complete(netdev);
 844                 b44_enable_ints(bp);
 845         }
 846
 847         return (done ? 0 : 1);
 848 }
 849
 850 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 851 {
 852         struct net_device *dev = dev_id;
 853         struct b44 *bp = netdev_priv(dev);
 854         unsigned long flags;
 855         u32 istat, imask;
 856         int handled = 0;
 857
 858         spin_lock_irqsave(&bp->lock, flags);
 859
 860         istat = br32(bp, B44_ISTAT);
 861         imask = br32(bp, B44_IMASK);
 862
 863         /* ??? What the fuck is the purpose of the interrupt mask
 864          * ??? register if we have to mask it out by hand anyways?
 865          */
 866         istat &= imask;
 867         if (istat) {
 868                 handled = 1;
 869                 if (netif_rx_schedule_prep(dev)) {
 870                         /* NOTE: These writes are posted by the readback of
 871                          *       the ISTAT register below.
 872                          */
 873                         bp->istat = istat;
 874                         __b44_disable_ints(bp);
 875                         __netif_rx_schedule(dev);
 876                 } else {
 877                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
 878                                dev->name);
 879                 }
 880
 881                 bw32(bp, B44_ISTAT, istat);
 882                 br32(bp, B44_ISTAT);
 883         }
 884         spin_unlock_irqrestore(&bp->lock, flags);
 885         return IRQ_RETVAL(handled);
 886 }
 887
 888 static void b44_tx_timeout(struct net_device *dev)
 889 {
 890         struct b44 *bp = netdev_priv(dev);
 891
 892         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 893                dev->name);
 894
 895         spin_lock_irq(&bp->lock);
 896
 897         b44_halt(bp);
 898         b44_init_rings(bp);
 899         b44_init_hw(bp);
 900
 901         spin_unlock_irq(&bp->lock);
 902
 903         b44_enable_ints(bp);
 904
 905         netif_wake_queue(dev);
 906 }
 907
 908 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
 909 {
 910         struct b44 *bp = netdev_priv(dev);
 911         dma_addr_t mapping;
 912         u32 len, entry, ctrl;
 913
 914         len = skb->len;
 915         spin_lock_irq(&bp->lock);
 916
 917         /* This is a hard error, log it. */
 918         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
 919                 netif_stop_queue(dev);
 920                 spin_unlock_irq(&bp->lock);
 921                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
 922                        dev->name);
 923                 return 1;
 924         }
 925
 926         entry = bp->tx_prod;
 927         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
 928         if(mapping+len > B44_DMA_MASK) {
 929                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 930                 pci_unmap_single(bp->pdev, mapping, len,PCI_DMA_TODEVICE);
 931                 memcpy(bp->tx_bufs+entry*TX_PKT_BUF_SZ,skb->data,skb->len);
 932                 mapping = pci_map_single(bp->pdev, bp->tx_bufs+entry*TX_PKT_BUF_SZ, len, PCI_DMA_TODEVICE);
 933         }
 934
 935         bp->tx_buffers[entry].skb = skb;
 936         pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
 937
 938         ctrl  = (len & DESC_CTRL_LEN);
 939         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
 940         if (entry == (B44_TX_RING_SIZE - 1))
 941                 ctrl |= DESC_CTRL_EOT;
 942
 943         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
 944         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
 945
 946         entry = NEXT_TX(entry);
 947
 948         bp->tx_prod = entry;
 949
 950         wmb();
 951
 952         bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 953         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
 954                 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 955         if (bp->flags & B44_FLAG_REORDER_BUG)
 956                 br32(bp, B44_DMATX_PTR);
 957
 958         if (TX_BUFFS_AVAIL(bp) < 1)
 959                 netif_stop_queue(dev);
 960
 961         spin_unlock_irq(&bp->lock);
 962
 963         dev->trans_start = jiffies;
 964
 965         return 0;
 966 }
 967
 968 static int b44_change_mtu(struct net_device *dev, int new_mtu)
 969 {
 970         struct b44 *bp = netdev_priv(dev);
 971
 972         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
 973                 return -EINVAL;
 974
 975         if (!netif_running(dev)) {
 976                 /* We'll just catch it later when the
 977                  * device is up'd.
 978                  */
 979                 dev->mtu = new_mtu;
 980                 return 0;
 981         }
 982
 983         spin_lock_irq(&bp->lock);
 984         b44_halt(bp);
 985         dev->mtu = new_mtu;
 986         b44_init_rings(bp);
 987         b44_init_hw(bp);
 988         spin_unlock_irq(&bp->lock);
 989
 990         b44_enable_ints(bp);
 991
 992         return 0;
 993 }
 994
 995 /* Free up pending packets in all rx/tx rings.
 996  *
 997  * The chip has been shut down and the driver detached from
 998  * the networking, so no interrupts or new tx packets will
 999  * end up in the driver.  bp->lock is not held and we are not
1000  * in an interrupt context and thus may sleep.
1001  */
1002 static void b44_free_rings(struct b44 *bp)
1003 {
1004         struct ring_info *rp;
1005         int i;
1006
1007         for (i = 0; i < B44_RX_RING_SIZE; i++) {
1008                 rp = &bp->rx_buffers[i];
1009
1010                 if (rp->skb == NULL)
1011                         continue;
1012                 pci_unmap_single(bp->pdev,
1013                                  pci_unmap_addr(rp, mapping),
1014                                  RX_PKT_BUF_SZ,
1015                                  PCI_DMA_FROMDEVICE);
1016                 dev_kfree_skb_any(rp->skb);
1017                 rp->skb = NULL;
1018         }
1019
1020         /* XXX needs changes once NETIF_F_SG is set... */
1021         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1022                 rp = &bp->tx_buffers[i];
1023
1024                 if (rp->skb == NULL)
1025                         continue;
1026                 pci_unmap_single(bp->pdev,
1027                                  pci_unmap_addr(rp, mapping),
1028                                  rp->skb->len,
1029                                  PCI_DMA_TODEVICE);
1030                 dev_kfree_skb_any(rp->skb);
1031                 rp->skb = NULL;
1032         }
1033 }
1034
1035 /* Initialize tx/rx rings for packet processing.
1036  *
1037  * The chip has been shut down and the driver detached from
1038  * the networking, so no interrupts or new tx packets will
1039  * end up in the driver.  bp->lock is not held and we are not
1040  * in an interrupt context and thus may sleep.
1041  */
1042 static void b44_init_rings(struct b44 *bp)
1043 {
1044         int i;
1045
1046         b44_free_rings(bp);
1047
1048         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1049         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1050
1051         for (i = 0; i < bp->rx_pending; i++) {
1052                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1053                         break;
1054         }
1055 }
1056
1057 /*
1058  * Must not be invoked with interrupt sources disabled and
1059  * the hardware shutdown down.
1060  */
1061 static void b44_free_consistent(struct b44 *bp)
1062 {
1063         if (bp->rx_buffers) {
1064                 kfree(bp->rx_buffers);
1065                 bp->rx_buffers = NULL;
1066         }
1067         if (bp->tx_buffers) {
1068                 kfree(bp->tx_buffers);
1069                 bp->tx_buffers = NULL;
1070         }
1071         if (bp->rx_ring) {
1072                 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1073                                     bp->rx_ring, bp->rx_ring_dma);
1074                 bp->rx_ring = NULL;
1075         }
1076         if (bp->tx_ring) {
1077                 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1078                                     bp->tx_ring, bp->tx_ring_dma);
1079                 bp->tx_ring = NULL;
1080         }
1081         if (bp->tx_bufs) {
1082                 pci_free_consistent(bp->pdev, B44_TX_RING_SIZE * TX_PKT_BUF_SZ,
1083                                     bp->tx_bufs, bp->tx_bufs_dma);
1084                 bp->tx_bufs = NULL;
1085         }
1086 }
1087
1088 /*
1089  * Must not be invoked with interrupt sources disabled and
1090  * the hardware shutdown down.  Can sleep.
1091  */
1092 static int b44_alloc_consistent(struct b44 *bp)
1093 {
1094         int size;
1095
1096         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1097         bp->rx_buffers = kmalloc(size, GFP_KERNEL);
1098         if (!bp->rx_buffers)
1099                 goto out_err;
1100         memset(bp->rx_buffers, 0, size);
1101
1102         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1103         bp->tx_buffers = kmalloc(size, GFP_KERNEL);
1104         if (!bp->tx_buffers)
1105                 goto out_err;
1106         memset(bp->tx_buffers, 0, size);
1107
1108         size = B44_TX_RING_SIZE * TX_PKT_BUF_SZ;
1109         bp->tx_bufs = pci_alloc_consistent(bp->pdev, size, &bp->tx_bufs_dma);
1110         if (!bp->tx_bufs)
1111                 goto out_err;
1112         memset(bp->tx_bufs, 0, size);
1113
1114         size = DMA_TABLE_BYTES;
1115         bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1116         if (!bp->rx_ring)
1117                 goto out_err;
1118
1119         bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1120         if (!bp->tx_ring)
1121                 goto out_err;
1122
1123         return 0;
1124
1125 out_err:
1126         b44_free_consistent(bp);
1127         return -ENOMEM;
1128 }
1129
1130 /* bp->lock is held. */
1131 static void b44_clear_stats(struct b44 *bp)
1132 {
1133         unsigned long reg;
1134
1135         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1136         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1137                 br32(bp, reg);
1138         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1139                 br32(bp, reg);
1140 }
1141
1142 /* bp->lock is held. */
1143 static void b44_chip_reset(struct b44 *bp)
1144 {
1145         if (ssb_is_core_up(bp)) {
1146                 bw32(bp, B44_RCV_LAZY, 0);
1147                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1148                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1149                 bw32(bp, B44_DMATX_CTRL, 0);
1150                 bp->tx_prod = bp->tx_cons = 0;
1151                 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1152                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1153                                      100, 0);
1154                 }
1155                 bw32(bp, B44_DMARX_CTRL, 0);
1156                 bp->rx_prod = bp->rx_cons = 0;
1157         } else {
1158                 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1159                                    SBINTVEC_ENET0 :
1160                                    SBINTVEC_ENET1));
1161         }
1162
1163         ssb_core_reset(bp);
1164
1165         b44_clear_stats(bp);
1166
1167         /* Make PHY accessible. */
1168         bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1169                              (0x0d & MDIO_CTRL_MAXF_MASK)));
1170         br32(bp, B44_MDIO_CTRL);
1171
1172         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1173                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1174                 br32(bp, B44_ENET_CTRL);
1175                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1176         } else {
1177                 u32 val = br32(bp, B44_DEVCTRL);
1178
1179                 if (val & DEVCTRL_EPR) {
1180                         bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1181                         br32(bp, B44_DEVCTRL);
1182                         udelay(100);
1183                 }
1184                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1185         }
1186 }
1187
1188 /* bp->lock is held. */
1189 static void b44_halt(struct b44 *bp)
1190 {
1191         b44_disable_ints(bp);
1192         b44_chip_reset(bp);
1193 }
1194
1195 /* bp->lock is held. */
1196 static void __b44_set_mac_addr(struct b44 *bp)
1197 {
1198         bw32(bp, B44_CAM_CTRL, 0);
1199         if (!(bp->dev->flags & IFF_PROMISC)) {
1200                 u32 val;
1201
1202                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1203                 val = br32(bp, B44_CAM_CTRL);
1204                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1205         }
1206 }
1207
1208 static int b44_set_mac_addr(struct net_device *dev, void *p)
1209 {
1210         struct b44 *bp = netdev_priv(dev);
1211         struct sockaddr *addr = p;
1212
1213         if (netif_running(dev))
1214                 return -EBUSY;
1215
1216         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1217
1218         spin_lock_irq(&bp->lock);
1219         __b44_set_mac_addr(bp);
1220         spin_unlock_irq(&bp->lock);
1221
1222         return 0;
1223 }
1224
1225 /* Called at device open time to get the chip ready for
1226  * packet processing.  Invoked with bp->lock held.
1227  */
1228 static void __b44_set_rx_mode(struct net_device *);
1229 static void b44_init_hw(struct b44 *bp)
1230 {
1231         u32 val;
1232
1233         b44_chip_reset(bp);
1234         b44_phy_reset(bp);
1235         b44_setup_phy(bp);
1236
1237         /* Enable CRC32, set proper LED modes and power on PHY */
1238         bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1239         bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1240
1241         /* This sets the MAC address too.  */
1242         __b44_set_rx_mode(bp->dev);
1243
1244         /* MTU + eth header + possible VLAN tag + struct rx_header */
1245         bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1246         bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1247
1248         bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1249         bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1250         bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1251         bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1252                               (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1253         bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1254
1255         bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1256         bp->rx_prod = bp->rx_pending;
1257
1258         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1259
1260         val = br32(bp, B44_ENET_CTRL);
1261         bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1262 }
1263
1264 static int b44_open(struct net_device *dev)
1265 {
1266         struct b44 *bp = netdev_priv(dev);
1267         int err;
1268
1269         err = b44_alloc_consistent(bp);
1270         if (err)
1271                 return err;
1272
1273         err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1274         if (err)
1275                 goto err_out_free;
1276
1277         spin_lock_irq(&bp->lock);
1278
1279         b44_init_rings(bp);
1280         b44_init_hw(bp);
1281         bp->flags |= B44_FLAG_INIT_COMPLETE;
1282
1283         spin_unlock_irq(&bp->lock);
1284
1285         init_timer(&bp->timer);
1286         bp->timer.expires = jiffies + HZ;
1287         bp->timer.data = (unsigned long) bp;
1288         bp->timer.function = b44_timer;
1289         add_timer(&bp->timer);
1290
1291         b44_enable_ints(bp);
1292
1293         return 0;
1294
1295 err_out_free:
1296         b44_free_consistent(bp);
1297         return err;
1298 }
1299
1300 #if 0
1301 /*static*/ void b44_dump_state(struct b44 *bp)
1302 {
1303         u32 val32, val32_2, val32_3, val32_4, val32_5;
1304         u16 val16;
1305
1306         pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1307         printk("DEBUG: PCI status [%04x] \n", val16);
1308
1309 }
1310 #endif
1311
1312 #ifdef CONFIG_NET_POLL_CONTROLLER
1313 /*
1314  * Polling receive - used by netconsole and other diagnostic tools
1315  * to allow network i/o with interrupts disabled.
1316  */
1317 static void b44_poll_controller(struct net_device *dev)
1318 {
1319         disable_irq(dev->irq);
1320         b44_interrupt(dev->irq, dev, NULL);
1321         enable_irq(dev->irq);
1322 }
1323 #endif
1324
1325 static int b44_close(struct net_device *dev)
1326 {
1327         struct b44 *bp = netdev_priv(dev);
1328
1329         netif_stop_queue(dev);
1330
1331         del_timer_sync(&bp->timer);
1332
1333         spin_lock_irq(&bp->lock);
1334
1335 #if 0
1336         b44_dump_state(bp);
1337 #endif
1338         b44_halt(bp);
1339         b44_free_rings(bp);
1340         bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1341         netif_carrier_off(bp->dev);
1342
1343         spin_unlock_irq(&bp->lock);
1344
1345         free_irq(dev->irq, dev);
1346
1347         b44_free_consistent(bp);
1348
1349         return 0;
1350 }
1351
1352 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1353 {
1354         struct b44 *bp = netdev_priv(dev);
1355         struct net_device_stats *nstat = &bp->stats;
1356         struct b44_hw_stats *hwstat = &bp->hw_stats;
1357
1358         /* Convert HW stats into netdevice stats. */
1359         nstat->rx_packets = hwstat->rx_pkts;
1360         nstat->tx_packets = hwstat->tx_pkts;
1361         nstat->rx_bytes   = hwstat->rx_octets;
1362         nstat->tx_bytes   = hwstat->tx_octets;
1363         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1364                              hwstat->tx_oversize_pkts +
1365                              hwstat->tx_underruns +
1366                              hwstat->tx_excessive_cols +
1367                              hwstat->tx_late_cols);
1368         nstat->multicast  = hwstat->tx_multicast_pkts;
1369         nstat->collisions = hwstat->tx_total_cols;
1370
1371         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1372                                    hwstat->rx_undersize);
1373         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1374         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1375         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1376         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1377                                    hwstat->rx_oversize_pkts +
1378                                    hwstat->rx_missed_pkts +
1379                                    hwstat->rx_crc_align_errs +
1380                                    hwstat->rx_undersize +
1381                                    hwstat->rx_crc_errs +
1382                                    hwstat->rx_align_errs +
1383                                    hwstat->rx_symbol_errs);
1384
1385         nstat->tx_aborted_errors = hwstat->tx_underruns;
1386 #if 0
1387         /* Carrier lost counter seems to be broken for some devices */
1388         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1389 #endif
1390
1391         return nstat;
1392 }
1393
1394 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1395 {
1396         struct dev_mc_list *mclist;
1397         int i, num_ents;
1398
1399         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1400         mclist = dev->mc_list;
1401         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1402                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1403         }
1404         return i+1;
1405 }
1406
1407 static void __b44_set_rx_mode(struct net_device *dev)
1408 {
1409         struct b44 *bp = netdev_priv(dev);
1410         u32 val;
1411         int i=0;
1412         unsigned char zero[6] = {0,0,0,0,0,0};
1413
1414         val = br32(bp, B44_RXCONFIG);
1415         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1416         if (dev->flags & IFF_PROMISC) {
1417                 val |= RXCONFIG_PROMISC;
1418                 bw32(bp, B44_RXCONFIG, val);
1419         } else {
1420                 __b44_set_mac_addr(bp);
1421
1422                 if (dev->flags & IFF_ALLMULTI)
1423                         val |= RXCONFIG_ALLMULTI;
1424                 else
1425                         i=__b44_load_mcast(bp, dev);
1426
1427                 for(;i<64;i++) {
1428                         __b44_cam_write(bp, zero, i);
1429                 }
1430                 bw32(bp, B44_RXCONFIG, val);
1431                 val = br32(bp, B44_CAM_CTRL);
1432                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1433         }
1434 }
1435
1436 static void b44_set_rx_mode(struct net_device *dev)
1437 {
1438         struct b44 *bp = netdev_priv(dev);
1439
1440         spin_lock_irq(&bp->lock);
1441         __b44_set_rx_mode(dev);
1442         spin_unlock_irq(&bp->lock);
1443 }
1444
1445 static u32 b44_get_msglevel(struct net_device *dev)
1446 {
1447         struct b44 *bp = netdev_priv(dev);
1448         return bp->msg_enable;
1449 }
1450
1451 static void b44_set_msglevel(struct net_device *dev, u32 value)
1452 {
1453         struct b44 *bp = netdev_priv(dev);
1454         bp->msg_enable = value;
1455 }
1456
1457 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1458 {
1459         struct b44 *bp = netdev_priv(dev);
1460         struct pci_dev *pci_dev = bp->pdev;
1461
1462         strcpy (info->driver, DRV_MODULE_NAME);
1463         strcpy (info->version, DRV_MODULE_VERSION);
1464         strcpy (info->bus_info, pci_name(pci_dev));
1465 }
1466
1467 static int b44_nway_reset(struct net_device *dev)
1468 {
1469         struct b44 *bp = netdev_priv(dev);
1470         u32 bmcr;
1471         int r;
1472
1473         spin_lock_irq(&bp->lock);
1474         b44_readphy(bp, MII_BMCR, &bmcr);
1475         b44_readphy(bp, MII_BMCR, &bmcr);
1476         r = -EINVAL;
1477         if (bmcr & BMCR_ANENABLE) {
1478                 b44_writephy(bp, MII_BMCR,
1479                              bmcr | BMCR_ANRESTART);
1480                 r = 0;
1481         }
1482         spin_unlock_irq(&bp->lock);
1483
1484         return r;
1485 }
1486
1487 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1488 {
1489         struct b44 *bp = netdev_priv(dev);
1490
1491         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1492                 return -EAGAIN;
1493         cmd->supported = (SUPPORTED_Autoneg);
1494         cmd->supported |= (SUPPORTED_100baseT_Half |
1495                           SUPPORTED_100baseT_Full |
1496                           SUPPORTED_10baseT_Half |
1497                           SUPPORTED_10baseT_Full |
1498                           SUPPORTED_MII);
1499
1500         cmd->advertising = 0;
1501         if (bp->flags & B44_FLAG_ADV_10HALF)
1502                 cmd->advertising |= ADVERTISE_10HALF;
1503         if (bp->flags & B44_FLAG_ADV_10FULL)
1504                 cmd->advertising |= ADVERTISE_10FULL;
1505         if (bp->flags & B44_FLAG_ADV_100HALF)
1506                 cmd->advertising |= ADVERTISE_100HALF;
1507         if (bp->flags & B44_FLAG_ADV_100FULL)
1508                 cmd->advertising |= ADVERTISE_100FULL;
1509         cmd->advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1510         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1511                 SPEED_100 : SPEED_10;
1512         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1513                 DUPLEX_FULL : DUPLEX_HALF;
1514         cmd->port = 0;
1515         cmd->phy_address = bp->phy_addr;
1516         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1517                 XCVR_INTERNAL : XCVR_EXTERNAL;
1518         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1519                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1520         cmd->maxtxpkt = 0;
1521         cmd->maxrxpkt = 0;
1522         return 0;
1523 }
1524
1525 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1526 {
1527         struct b44 *bp = netdev_priv(dev);
1528
1529         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1530                 return -EAGAIN;
1531
1532         /* We do not support gigabit. */
1533         if (cmd->autoneg == AUTONEG_ENABLE) {
1534                 if (cmd->advertising &
1535                     (ADVERTISED_1000baseT_Half |
1536                      ADVERTISED_1000baseT_Full))
1537                         return -EINVAL;
1538         } else if ((cmd->speed != SPEED_100 &&
1539                     cmd->speed != SPEED_10) ||
1540                    (cmd->duplex != DUPLEX_HALF &&
1541                     cmd->duplex != DUPLEX_FULL)) {
1542                         return -EINVAL;
1543         }
1544
1545         spin_lock_irq(&bp->lock);
1546
1547         if (cmd->autoneg == AUTONEG_ENABLE) {
1548                 bp->flags &= ~B44_FLAG_FORCE_LINK;
1549                 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1550                                B44_FLAG_ADV_10FULL |
1551                                B44_FLAG_ADV_100HALF |
1552                                B44_FLAG_ADV_100FULL);
1553                 if (cmd->advertising & ADVERTISE_10HALF)
1554                         bp->flags |= B44_FLAG_ADV_10HALF;
1555                 if (cmd->advertising & ADVERTISE_10FULL)
1556                         bp->flags |= B44_FLAG_ADV_10FULL;
1557                 if (cmd->advertising & ADVERTISE_100HALF)
1558                         bp->flags |= B44_FLAG_ADV_100HALF;
1559                 if (cmd->advertising & ADVERTISE_100FULL)
1560                         bp->flags |= B44_FLAG_ADV_100FULL;
1561         } else {
1562                 bp->flags |= B44_FLAG_FORCE_LINK;
1563                 if (cmd->speed == SPEED_100)
1564                         bp->flags |= B44_FLAG_100_BASE_T;
1565                 if (cmd->duplex == DUPLEX_FULL)
1566                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1567         }
1568
1569         b44_setup_phy(bp);
1570
1571         spin_unlock_irq(&bp->lock);
1572
1573         return 0;
1574 }
1575
1576 static void b44_get_ringparam(struct net_device *dev,
1577                               struct ethtool_ringparam *ering)
1578 {
1579         struct b44 *bp = netdev_priv(dev);
1580
1581         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1582         ering->rx_pending = bp->rx_pending;
1583
1584         /* XXX ethtool lacks a tx_max_pending, oops... */
1585 }
1586
1587 static int b44_set_ringparam(struct net_device *dev,
1588                              struct ethtool_ringparam *ering)
1589 {
1590         struct b44 *bp = netdev_priv(dev);
1591
1592         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1593             (ering->rx_mini_pending != 0) ||
1594             (ering->rx_jumbo_pending != 0) ||
1595             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1596                 return -EINVAL;
1597
1598         spin_lock_irq(&bp->lock);
1599
1600         bp->rx_pending = ering->rx_pending;
1601         bp->tx_pending = ering->tx_pending;
1602
1603         b44_halt(bp);
1604         b44_init_rings(bp);
1605         b44_init_hw(bp);
1606         netif_wake_queue(bp->dev);
1607         spin_unlock_irq(&bp->lock);
1608
1609         b44_enable_ints(bp);
1610
1611         return 0;
1612 }
1613
1614 static void b44_get_pauseparam(struct net_device *dev,
1615                                 struct ethtool_pauseparam *epause)
1616 {
1617         struct b44 *bp = netdev_priv(dev);
1618
1619         epause->autoneg =
1620                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1621         epause->rx_pause =
1622                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1623         epause->tx_pause =
1624                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1625 }
1626
1627 static int b44_set_pauseparam(struct net_device *dev,
1628                                 struct ethtool_pauseparam *epause)
1629 {
1630         struct b44 *bp = netdev_priv(dev);
1631
1632         spin_lock_irq(&bp->lock);
1633         if (epause->autoneg)
1634                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1635         else
1636                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1637         if (epause->rx_pause)
1638                 bp->flags |= B44_FLAG_RX_PAUSE;
1639         else
1640                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1641         if (epause->tx_pause)
1642                 bp->flags |= B44_FLAG_TX_PAUSE;
1643         else
1644                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1645         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1646                 b44_halt(bp);
1647                 b44_init_rings(bp);
1648                 b44_init_hw(bp);
1649         } else {
1650                 __b44_set_flow_ctrl(bp, bp->flags);
1651         }
1652         spin_unlock_irq(&bp->lock);
1653
1654         b44_enable_ints(bp);
1655
1656         return 0;
1657 }
1658
1659 static struct ethtool_ops b44_ethtool_ops = {
1660         .get_drvinfo            = b44_get_drvinfo,
1661         .get_settings           = b44_get_settings,
1662         .set_settings           = b44_set_settings,
1663         .nway_reset             = b44_nway_reset,
1664         .get_link               = ethtool_op_get_link,
1665         .get_ringparam          = b44_get_ringparam,
1666         .set_ringparam          = b44_set_ringparam,
1667         .get_pauseparam         = b44_get_pauseparam,
1668         .set_pauseparam         = b44_set_pauseparam,
1669         .get_msglevel           = b44_get_msglevel,
1670         .set_msglevel           = b44_set_msglevel,
1671 };
1672
1673 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1674 {
1675         struct mii_ioctl_data *data = if_mii(ifr);
1676         struct b44 *bp = netdev_priv(dev);
1677         int err;
1678
1679         spin_lock_irq(&bp->lock);
1680         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1681         spin_unlock_irq(&bp->lock);
1682
1683         return err;
1684 }
1685
1686 /* Read 128-bytes of EEPROM. */
1687 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1688 {
1689         long i;
1690         u16 *ptr = (u16 *) data;
1691
1692         for (i = 0; i < 128; i += 2)
1693                 ptr[i / 2] = readw(bp->regs + 4096 + i);
1694
1695         return 0;
1696 }
1697
1698 static int __devinit b44_get_invariants(struct b44 *bp)
1699 {
1700         u8 eeprom[128];
1701         int err;
1702
1703         err = b44_read_eeprom(bp, &eeprom[0]);
1704         if (err)
1705                 goto out;
1706
1707         bp->dev->dev_addr[0] = eeprom[79];
1708         bp->dev->dev_addr[1] = eeprom[78];
1709         bp->dev->dev_addr[2] = eeprom[81];
1710         bp->dev->dev_addr[3] = eeprom[80];
1711         bp->dev->dev_addr[4] = eeprom[83];
1712         bp->dev->dev_addr[5] = eeprom[82];
1713
1714         bp->phy_addr = eeprom[90] & 0x1f;
1715
1716         /* With this, plus the rx_header prepended to the data by the
1717          * hardware, we'll land the ethernet header on a 2-byte boundary.
1718          */
1719         bp->rx_offset = 30;
1720
1721         bp->imask = IMASK_DEF;
1722
1723         bp->core_unit = ssb_core_unit(bp);
1724         bp->dma_offset = SB_PCI_DMA;
1725
1726         /* XXX - really required?
1727            bp->flags |= B44_FLAG_BUGGY_TXPTR;
1728          */
1729 out:
1730         return err;
1731 }
1732
1733 static int __devinit b44_init_one(struct pci_dev *pdev,
1734                                   const struct pci_device_id *ent)
1735 {
1736         static int b44_version_printed = 0;
1737         unsigned long b44reg_base, b44reg_len;
1738         struct net_device *dev;
1739         struct b44 *bp;
1740         int err, i;
1741
1742         if (b44_version_printed++ == 0)
1743                 printk(KERN_INFO "%s", version);
1744
1745         err = pci_enable_device(pdev);
1746         if (err) {
1747                 printk(KERN_ERR PFX "Cannot enable PCI device, "
1748                        "aborting.\n");
1749                 return err;
1750         }
1751
1752         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1753                 printk(KERN_ERR PFX "Cannot find proper PCI device "
1754                        "base address, aborting.\n");
1755                 err = -ENODEV;
1756                 goto err_out_disable_pdev;
1757         }
1758
1759         err = pci_request_regions(pdev, DRV_MODULE_NAME);
1760         if (err) {
1761                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1762                        "aborting.\n");
1763                 goto err_out_disable_pdev;
1764         }
1765
1766         pci_set_master(pdev);
1767
1768         err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1769         if (err) {
1770                 printk(KERN_ERR PFX "No usable DMA configuration, "
1771                        "aborting.\n");
1772                 goto err_out_free_res;
1773         }
1774
1775         err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1776         if (err) {
1777           printk(KERN_ERR PFX "No usable DMA configuration, "
1778                  "aborting.\n");
1779           goto err_out_free_res;
1780         }
1781
1782         b44reg_base = pci_resource_start(pdev, 0);
1783         b44reg_len = pci_resource_len(pdev, 0);
1784
1785         dev = alloc_etherdev(sizeof(*bp));
1786         if (!dev) {
1787                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1788                 err = -ENOMEM;
1789                 goto err_out_free_res;
1790         }
1791
1792         SET_MODULE_OWNER(dev);
1793         SET_NETDEV_DEV(dev,&pdev->dev);
1794
1795         /* No interesting netdevice features in this card... */
1796         dev->features |= 0;
1797
1798         bp = netdev_priv(dev);
1799         bp->pdev = pdev;
1800         bp->dev = dev;
1801         if (b44_debug >= 0)
1802                 bp->msg_enable = (1 << b44_debug) - 1;
1803         else
1804                 bp->msg_enable = B44_DEF_MSG_ENABLE;
1805
1806         spin_lock_init(&bp->lock);
1807
1808         bp->regs = ioremap(b44reg_base, b44reg_len);
1809         if (bp->regs == 0UL) {
1810                 printk(KERN_ERR PFX "Cannot map device registers, "
1811                        "aborting.\n");
1812                 err = -ENOMEM;
1813                 goto err_out_free_dev;
1814         }
1815
1816         bp->rx_pending = B44_DEF_RX_RING_PENDING;
1817         bp->tx_pending = B44_DEF_TX_RING_PENDING;
1818
1819         dev->open = b44_open;
1820         dev->stop = b44_close;
1821         dev->hard_start_xmit = b44_start_xmit;
1822         dev->get_stats = b44_get_stats;
1823         dev->set_multicast_list = b44_set_rx_mode;
1824         dev->set_mac_address = b44_set_mac_addr;
1825         dev->do_ioctl = b44_ioctl;
1826         dev->tx_timeout = b44_tx_timeout;
1827         dev->poll = b44_poll;
1828         dev->weight = 64;
1829         dev->watchdog_timeo = B44_TX_TIMEOUT;
1830 #ifdef CONFIG_NET_POLL_CONTROLLER
1831         dev->poll_controller = b44_poll_controller;
1832 #endif
1833         dev->change_mtu = b44_change_mtu;
1834         dev->irq = pdev->irq;
1835         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1836
1837         err = b44_get_invariants(bp);
1838         if (err) {
1839                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1840                        "aborting.\n");
1841                 goto err_out_iounmap;
1842         }
1843
1844         bp->mii_if.dev = dev;
1845         bp->mii_if.mdio_read = b44_mii_read;
1846         bp->mii_if.mdio_write = b44_mii_write;
1847         bp->mii_if.phy_id = bp->phy_addr;
1848         bp->mii_if.phy_id_mask = 0x1f;
1849         bp->mii_if.reg_num_mask = 0x1f;
1850
1851         /* By default, advertise all speed/duplex settings. */
1852         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1853                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1854
1855         /* By default, auto-negotiate PAUSE. */
1856         bp->flags |= B44_FLAG_PAUSE_AUTO;
1857
1858         err = register_netdev(dev);
1859         if (err) {
1860                 printk(KERN_ERR PFX "Cannot register net device, "
1861                        "aborting.\n");
1862                 goto err_out_iounmap;
1863         }
1864
1865         pci_set_drvdata(pdev, dev);
1866
1867         pci_save_state(bp->pdev);
1868
1869         printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1870         for (i = 0; i < 6; i++)
1871                 printk("%2.2x%c", dev->dev_addr[i],
1872                        i == 5 ? '\n' : ':');
1873
1874         return 0;
1875
1876 err_out_iounmap:
1877         iounmap(bp->regs);
1878
1879 err_out_free_dev:
1880         free_netdev(dev);
1881
1882 err_out_free_res:
1883         pci_release_regions(pdev);
1884
1885 err_out_disable_pdev:
1886         pci_disable_device(pdev);
1887         pci_set_drvdata(pdev, NULL);
1888         return err;
1889 }
1890
1891 static void __devexit b44_remove_one(struct pci_dev *pdev)
1892 {
1893         struct net_device *dev = pci_get_drvdata(pdev);
1894
1895         if (dev) {
1896                 struct b44 *bp = netdev_priv(dev);
1897
1898                 unregister_netdev(dev);
1899                 iounmap(bp->regs);
1900                 free_netdev(dev);
1901                 pci_release_regions(pdev);
1902                 pci_disable_device(pdev);
1903                 pci_set_drvdata(pdev, NULL);
1904         }
1905 }
1906
1907 static int b44_suspend(struct pci_dev *pdev, u32 state)
1908 {
1909         struct net_device *dev = pci_get_drvdata(pdev);
1910         struct b44 *bp = netdev_priv(dev);
1911
1912         if (!netif_running(dev))
1913                  return 0;
1914
1915         del_timer_sync(&bp->timer);
1916
1917         spin_lock_irq(&bp->lock);
1918
1919         b44_halt(bp);
1920         netif_carrier_off(bp->dev);
1921         netif_device_detach(bp->dev);
1922         b44_free_rings(bp);
1923
1924         spin_unlock_irq(&bp->lock);
1925         return 0;
1926 }
1927
1928 static int b44_resume(struct pci_dev *pdev)
1929 {
1930         struct net_device *dev = pci_get_drvdata(pdev);
1931         struct b44 *bp = netdev_priv(dev);
1932
1933         pci_restore_state(pdev);
1934
1935         if (!netif_running(dev))
1936                 return 0;
1937
1938         spin_lock_irq(&bp->lock);
1939
1940         b44_init_rings(bp);
1941         b44_init_hw(bp);
1942         netif_device_attach(bp->dev);
1943         spin_unlock_irq(&bp->lock);
1944
1945         bp->timer.expires = jiffies + HZ;
1946         add_timer(&bp->timer);
1947
1948         b44_enable_ints(bp);
1949         return 0;
1950 }
1951
1952 static struct pci_driver b44_driver = {
1953         .name           = DRV_MODULE_NAME,
1954         .id_table       = b44_pci_tbl,
1955         .probe          = b44_init_one,
1956         .remove         = __devexit_p(b44_remove_one),
1957         .suspend        = b44_suspend,
1958         .resume         = b44_resume,
1959 };
1960
1961 static int __init b44_init(void)
1962 {
1963         return pci_module_init(&b44_driver);
1964 }
1965
1966 static void __exit b44_cleanup(void)
1967 {
1968         pci_unregister_driver(&b44_driver);
1969 }
1970
1971 module_init(b44_init);
1972 module_exit(b44_cleanup);
1973