1 /* b44.c: Broadcom 4400 device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
6 * Distribute under GPL.
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/types.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/mii.h>
16 #include <linux/if_ether.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/version.h>
23 #include <asm/uaccess.h>
29 #define DRV_MODULE_NAME "b44"
30 #define PFX DRV_MODULE_NAME ": "
31 #define DRV_MODULE_VERSION "0.95"
32 #define DRV_MODULE_RELDATE "Aug 3, 2004"
34 #define B44_DEF_MSG_ENABLE \
44 /* length of time before we decide the hardware is borked,
45 * and dev->tx_timeout() should be called to fix the problem
47 #define B44_TX_TIMEOUT (5 * HZ)
49 /* hardware minimum and maximum for a single frame's data payload */
50 #define B44_MIN_MTU 60
51 #define B44_MAX_MTU 1500
53 #define B44_RX_RING_SIZE 512
54 #define B44_DEF_RX_RING_PENDING 200
55 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
57 #define B44_TX_RING_SIZE 512
58 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
59 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
61 #define B44_DMA_MASK 0x3fffffff
63 #define TX_RING_GAP(BP) \
64 (B44_TX_RING_SIZE - (BP)->tx_pending)
65 #define TX_BUFFS_AVAIL(BP) \
66 (((BP)->tx_cons <= (BP)->tx_prod) ? \
67 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
68 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
69 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
71 #define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
72 #define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
74 /* minimum number of free TX descriptors required to wake up TX process */
75 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
77 static char version[] __devinitdata =
78 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
81 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
85 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
86 module_param(b44_debug, int, 0);
87 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
88 MODULE_VERSION(DRV_MODULE_VERSION);
90 static struct pci_device_id b44_pci_tbl[] = {
91 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
93 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
95 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
97 { } /* terminate list with empty entry */
100 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
102 static void b44_halt(struct b44 *);
103 static void b44_init_rings(struct b44 *);
104 static void b44_init_hw(struct b44 *);
105 static int b44_poll(struct net_device *dev, int *budget);
106 #ifdef CONFIG_NET_POLL_CONTROLLER
107 static void b44_poll_controller(struct net_device *dev);
110 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
112 return readl(bp->regs + reg);
115 static inline void bw32(const struct b44 *bp,
116 unsigned long reg, unsigned long val)
118 writel(val, bp->regs + reg);
121 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
122 u32 bit, unsigned long timeout, const int clear)
126 for (i = 0; i < timeout; i++) {
127 u32 val = br32(bp, reg);
129 if (clear && !(val & bit))
131 if (!clear && (val & bit))
136 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
140 (clear ? "clear" : "set"));
146 /* Sonics SiliconBackplane support routines. ROFL, you should see all the
147 * buzz words used on this company's website :-)
149 * All of these routines must be invoked with bp->lock held and
150 * interrupts disabled.
153 #define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
154 #define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
156 static u32 ssb_get_core_rev(struct b44 *bp)
158 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
161 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
163 u32 bar_orig, pci_rev, val;
165 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
166 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
167 pci_rev = ssb_get_core_rev(bp);
169 val = br32(bp, B44_SBINTVEC);
171 bw32(bp, B44_SBINTVEC, val);
173 val = br32(bp, SSB_PCI_TRANS_2);
174 val |= SSB_PCI_PREF | SSB_PCI_BURST;
175 bw32(bp, SSB_PCI_TRANS_2, val);
177 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
182 static void ssb_core_disable(struct b44 *bp)
184 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
187 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
188 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
189 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
190 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
191 SBTMSLOW_REJECT | SBTMSLOW_RESET));
192 br32(bp, B44_SBTMSLOW);
194 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
195 br32(bp, B44_SBTMSLOW);
199 static void ssb_core_reset(struct b44 *bp)
203 ssb_core_disable(bp);
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
205 br32(bp, B44_SBTMSLOW);
208 /* Clear SERR if set, this is a hw bug workaround. */
209 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
210 bw32(bp, B44_SBTMSHIGH, 0);
212 val = br32(bp, B44_SBIMSTATE);
213 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
214 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
216 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
217 br32(bp, B44_SBTMSLOW);
220 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
221 br32(bp, B44_SBTMSLOW);
225 static int ssb_core_unit(struct b44 *bp)
228 u32 val = br32(bp, B44_SBADMATCH0);
231 type = val & SBADMATCH0_TYPE_MASK;
234 base = val & SBADMATCH0_BS0_MASK;
238 base = val & SBADMATCH0_BS1_MASK;
243 base = val & SBADMATCH0_BS2_MASK;
250 static int ssb_is_core_up(struct b44 *bp)
252 return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
256 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
260 val = ((u32) data[2]) << 24;
261 val |= ((u32) data[3]) << 16;
262 val |= ((u32) data[4]) << 8;
263 val |= ((u32) data[5]) << 0;
264 bw32(bp, B44_CAM_DATA_LO, val);
265 val = (CAM_DATA_HI_VALID |
266 (((u32) data[0]) << 8) |
267 (((u32) data[1]) << 0));
268 bw32(bp, B44_CAM_DATA_HI, val);
269 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
270 (index << CAM_CTRL_INDEX_SHIFT)));
271 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
274 static inline void __b44_disable_ints(struct b44 *bp)
276 bw32(bp, B44_IMASK, 0);
279 static void b44_disable_ints(struct b44 *bp)
281 __b44_disable_ints(bp);
283 /* Flush posted writes. */
287 static void b44_enable_ints(struct b44 *bp)
289 bw32(bp, B44_IMASK, bp->imask);
292 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
296 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
297 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
298 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
299 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
300 (reg << MDIO_DATA_RA_SHIFT) |
301 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
302 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
303 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
308 static int b44_writephy(struct b44 *bp, int reg, u32 val)
310 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
311 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
312 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
313 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
314 (reg << MDIO_DATA_RA_SHIFT) |
315 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
316 (val & MDIO_DATA_DATA)));
317 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
320 /* miilib interface */
321 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
322 * due to code existing before miilib use was added to this driver.
323 * Someone should remove this artificial driver limitation in
324 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
326 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
329 struct b44 *bp = netdev_priv(dev);
330 int rc = b44_readphy(bp, location, &val);
336 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
339 struct b44 *bp = netdev_priv(dev);
340 b44_writephy(bp, location, val);
343 static int b44_phy_reset(struct b44 *bp)
348 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
352 err = b44_readphy(bp, MII_BMCR, &val);
354 if (val & BMCR_RESET) {
355 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
364 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
368 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
369 bp->flags |= pause_flags;
371 val = br32(bp, B44_RXCONFIG);
372 if (pause_flags & B44_FLAG_RX_PAUSE)
373 val |= RXCONFIG_FLOW;
375 val &= ~RXCONFIG_FLOW;
376 bw32(bp, B44_RXCONFIG, val);
378 val = br32(bp, B44_MAC_FLOW);
379 if (pause_flags & B44_FLAG_TX_PAUSE)
380 val |= (MAC_FLOW_PAUSE_ENAB |
381 (0xc0 & MAC_FLOW_RX_HI_WATER));
383 val &= ~MAC_FLOW_PAUSE_ENAB;
384 bw32(bp, B44_MAC_FLOW, val);
387 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
389 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
392 if (local & ADVERTISE_PAUSE_CAP) {
393 if (local & ADVERTISE_PAUSE_ASYM) {
394 if (remote & LPA_PAUSE_CAP)
395 pause_enab |= (B44_FLAG_TX_PAUSE |
397 else if (remote & LPA_PAUSE_ASYM)
398 pause_enab |= B44_FLAG_RX_PAUSE;
400 if (remote & LPA_PAUSE_CAP)
401 pause_enab |= (B44_FLAG_TX_PAUSE |
404 } else if (local & ADVERTISE_PAUSE_ASYM) {
405 if ((remote & LPA_PAUSE_CAP) &&
406 (remote & LPA_PAUSE_ASYM))
407 pause_enab |= B44_FLAG_TX_PAUSE;
410 __b44_set_flow_ctrl(bp, pause_enab);
413 static int b44_setup_phy(struct b44 *bp)
418 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
420 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
421 val & MII_ALEDCTRL_ALLMSK)) != 0)
423 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
425 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
426 val | MII_TLEDCTRL_ENABLE)) != 0)
429 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
430 u32 adv = ADVERTISE_CSMA;
432 if (bp->flags & B44_FLAG_ADV_10HALF)
433 adv |= ADVERTISE_10HALF;
434 if (bp->flags & B44_FLAG_ADV_10FULL)
435 adv |= ADVERTISE_10FULL;
436 if (bp->flags & B44_FLAG_ADV_100HALF)
437 adv |= ADVERTISE_100HALF;
438 if (bp->flags & B44_FLAG_ADV_100FULL)
439 adv |= ADVERTISE_100FULL;
441 if (bp->flags & B44_FLAG_PAUSE_AUTO)
442 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
444 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
446 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
447 BMCR_ANRESTART))) != 0)
452 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
454 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
455 if (bp->flags & B44_FLAG_100_BASE_T)
456 bmcr |= BMCR_SPEED100;
457 if (bp->flags & B44_FLAG_FULL_DUPLEX)
458 bmcr |= BMCR_FULLDPLX;
459 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
462 /* Since we will not be negotiating there is no safe way
463 * to determine if the link partner supports flow control
464 * or not. So just disable it completely in this case.
466 b44_set_flow_ctrl(bp, 0, 0);
473 static void b44_stats_update(struct b44 *bp)
478 val = &bp->hw_stats.tx_good_octets;
479 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
480 *val++ += br32(bp, reg);
482 val = &bp->hw_stats.rx_good_octets;
483 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
484 *val++ += br32(bp, reg);
488 static void b44_link_report(struct b44 *bp)
490 if (!netif_carrier_ok(bp->dev)) {
491 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
493 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
495 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
496 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
498 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
501 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
502 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
506 static void b44_check_phy(struct b44 *bp)
510 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
511 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
513 if (aux & MII_AUXCTRL_SPEED)
514 bp->flags |= B44_FLAG_100_BASE_T;
516 bp->flags &= ~B44_FLAG_100_BASE_T;
517 if (aux & MII_AUXCTRL_DUPLEX)
518 bp->flags |= B44_FLAG_FULL_DUPLEX;
520 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
522 if (!netif_carrier_ok(bp->dev) &&
523 (bmsr & BMSR_LSTATUS)) {
524 u32 val = br32(bp, B44_TX_CTRL);
525 u32 local_adv, remote_adv;
527 if (bp->flags & B44_FLAG_FULL_DUPLEX)
528 val |= TX_CTRL_DUPLEX;
530 val &= ~TX_CTRL_DUPLEX;
531 bw32(bp, B44_TX_CTRL, val);
533 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
534 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
535 !b44_readphy(bp, MII_LPA, &remote_adv))
536 b44_set_flow_ctrl(bp, local_adv, remote_adv);
539 netif_carrier_on(bp->dev);
541 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
543 netif_carrier_off(bp->dev);
547 if (bmsr & BMSR_RFAULT)
548 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
551 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
556 static void b44_timer(unsigned long __opaque)
558 struct b44 *bp = (struct b44 *) __opaque;
560 spin_lock_irq(&bp->lock);
564 b44_stats_update(bp);
566 spin_unlock_irq(&bp->lock);
568 bp->timer.expires = jiffies + HZ;
569 add_timer(&bp->timer);
572 static void b44_tx(struct b44 *bp)
576 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
577 cur /= sizeof(struct dma_desc);
579 /* XXX needs updating when NETIF_F_SG is supported */
580 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
581 struct ring_info *rp = &bp->tx_buffers[cons];
582 struct sk_buff *skb = rp->skb;
584 if (unlikely(skb == NULL))
587 pci_unmap_single(bp->pdev,
588 pci_unmap_addr(rp, mapping),
592 dev_kfree_skb_irq(skb);
596 if (netif_queue_stopped(bp->dev) &&
597 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
598 netif_wake_queue(bp->dev);
600 bw32(bp, B44_GPTIMER, 0);
603 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
604 * before the DMA address you give it. So we allocate 30 more bytes
605 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
606 * point the chip at 30 bytes past where the rx_header will go.
608 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
611 struct ring_info *src_map, *map;
612 struct rx_header *rh;
620 src_map = &bp->rx_buffers[src_idx];
621 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
622 map = &bp->rx_buffers[dest_idx];
623 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
627 mapping = pci_map_single(bp->pdev, skb->data,
631 /* Hardware bug work-around, the chip is unable to do PCI DMA
632 to/from anything above 1GB :-( */
633 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
635 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
636 dev_kfree_skb_any(skb);
637 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
640 mapping = pci_map_single(bp->pdev, skb->data,
643 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
644 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
645 dev_kfree_skb_any(skb);
651 skb_reserve(skb, bp->rx_offset);
653 rh = (struct rx_header *)
654 (skb->data - bp->rx_offset);
659 pci_unmap_addr_set(map, mapping, mapping);
664 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
665 if (dest_idx == (B44_RX_RING_SIZE - 1))
666 ctrl |= DESC_CTRL_EOT;
668 dp = &bp->rx_ring[dest_idx];
669 dp->ctrl = cpu_to_le32(ctrl);
670 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
672 return RX_PKT_BUF_SZ;
675 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
677 struct dma_desc *src_desc, *dest_desc;
678 struct ring_info *src_map, *dest_map;
679 struct rx_header *rh;
683 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
684 dest_desc = &bp->rx_ring[dest_idx];
685 dest_map = &bp->rx_buffers[dest_idx];
686 src_desc = &bp->rx_ring[src_idx];
687 src_map = &bp->rx_buffers[src_idx];
689 dest_map->skb = src_map->skb;
690 rh = (struct rx_header *) src_map->skb->data;
693 pci_unmap_addr_set(dest_map, mapping,
694 pci_unmap_addr(src_map, mapping));
696 ctrl = src_desc->ctrl;
697 if (dest_idx == (B44_RX_RING_SIZE - 1))
698 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
700 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
702 dest_desc->ctrl = ctrl;
703 dest_desc->addr = src_desc->addr;
706 pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
711 static int b44_rx(struct b44 *bp, int budget)
717 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
718 prod /= sizeof(struct dma_desc);
721 while (cons != prod && budget > 0) {
722 struct ring_info *rp = &bp->rx_buffers[cons];
723 struct sk_buff *skb = rp->skb;
724 dma_addr_t map = pci_unmap_addr(rp, mapping);
725 struct rx_header *rh;
728 pci_dma_sync_single_for_cpu(bp->pdev, map,
731 rh = (struct rx_header *) skb->data;
732 len = cpu_to_le16(rh->len);
733 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
734 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
736 b44_recycle_rx(bp, cons, bp->rx_prod);
738 bp->stats.rx_dropped++;
748 len = cpu_to_le16(rh->len);
749 } while (len == 0 && i++ < 5);
757 if (len > RX_COPY_THRESHOLD) {
759 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
762 pci_unmap_single(bp->pdev, map,
763 skb_size, PCI_DMA_FROMDEVICE);
764 /* Leave out rx_header */
765 skb_put(skb, len+bp->rx_offset);
766 skb_pull(skb,bp->rx_offset);
768 struct sk_buff *copy_skb;
770 b44_recycle_rx(bp, cons, bp->rx_prod);
771 copy_skb = dev_alloc_skb(len + 2);
772 if (copy_skb == NULL)
773 goto drop_it_no_recycle;
775 copy_skb->dev = bp->dev;
776 skb_reserve(copy_skb, 2);
777 skb_put(copy_skb, len);
778 /* DMA sync done above, copy just the actual packet */
779 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
783 skb->ip_summed = CHECKSUM_NONE;
784 skb->protocol = eth_type_trans(skb, bp->dev);
785 netif_receive_skb(skb);
786 bp->dev->last_rx = jiffies;
790 bp->rx_prod = (bp->rx_prod + 1) &
791 (B44_RX_RING_SIZE - 1);
792 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
796 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
801 static int b44_poll(struct net_device *netdev, int *budget)
803 struct b44 *bp = netdev_priv(netdev);
806 spin_lock_irq(&bp->lock);
808 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
809 /* spin_lock(&bp->tx_lock); */
811 /* spin_unlock(&bp->tx_lock); */
813 spin_unlock_irq(&bp->lock);
816 if (bp->istat & ISTAT_RX) {
817 int orig_budget = *budget;
820 if (orig_budget > netdev->quota)
821 orig_budget = netdev->quota;
823 work_done = b44_rx(bp, orig_budget);
825 *budget -= work_done;
826 netdev->quota -= work_done;
828 if (work_done >= orig_budget)
832 if (bp->istat & ISTAT_ERRORS) {
833 spin_lock_irq(&bp->lock);
837 netif_wake_queue(bp->dev);
838 spin_unlock_irq(&bp->lock);
843 netif_rx_complete(netdev);
847 return (done ? 0 : 1);
850 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
852 struct net_device *dev = dev_id;
853 struct b44 *bp = netdev_priv(dev);
858 spin_lock_irqsave(&bp->lock, flags);
860 istat = br32(bp, B44_ISTAT);
861 imask = br32(bp, B44_IMASK);
863 /* ??? What the fuck is the purpose of the interrupt mask
864 * ??? register if we have to mask it out by hand anyways?
869 if (netif_rx_schedule_prep(dev)) {
870 /* NOTE: These writes are posted by the readback of
871 * the ISTAT register below.
874 __b44_disable_ints(bp);
875 __netif_rx_schedule(dev);
877 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
881 bw32(bp, B44_ISTAT, istat);
884 spin_unlock_irqrestore(&bp->lock, flags);
885 return IRQ_RETVAL(handled);
888 static void b44_tx_timeout(struct net_device *dev)
890 struct b44 *bp = netdev_priv(dev);
892 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
895 spin_lock_irq(&bp->lock);
901 spin_unlock_irq(&bp->lock);
905 netif_wake_queue(dev);
908 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
910 struct b44 *bp = netdev_priv(dev);
911 struct sk_buff *bounce_skb;
913 u32 len, entry, ctrl;
916 spin_lock_irq(&bp->lock);
918 /* This is a hard error, log it. */
919 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
920 netif_stop_queue(dev);
921 spin_unlock_irq(&bp->lock);
922 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
927 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
928 if(mapping+len > B44_DMA_MASK) {
929 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
930 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
932 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
935 return NETDEV_TX_BUSY;
937 mapping = pci_map_single(bp->pdev, bounce_skb->data,
938 len, PCI_DMA_TODEVICE);
939 if(mapping+len > B44_DMA_MASK) {
940 pci_unmap_single(bp->pdev, mapping,
941 len, PCI_DMA_TODEVICE);
942 dev_kfree_skb_any(bounce_skb);
943 return NETDEV_TX_BUSY;
946 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
947 dev_kfree_skb_any(skb);
952 bp->tx_buffers[entry].skb = skb;
953 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
955 ctrl = (len & DESC_CTRL_LEN);
956 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
957 if (entry == (B44_TX_RING_SIZE - 1))
958 ctrl |= DESC_CTRL_EOT;
960 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
961 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
963 entry = NEXT_TX(entry);
969 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
970 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
971 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
972 if (bp->flags & B44_FLAG_REORDER_BUG)
973 br32(bp, B44_DMATX_PTR);
975 if (TX_BUFFS_AVAIL(bp) < 1)
976 netif_stop_queue(dev);
978 spin_unlock_irq(&bp->lock);
980 dev->trans_start = jiffies;
985 static int b44_change_mtu(struct net_device *dev, int new_mtu)
987 struct b44 *bp = netdev_priv(dev);
989 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
992 if (!netif_running(dev)) {
993 /* We'll just catch it later when the
1000 spin_lock_irq(&bp->lock);
1005 spin_unlock_irq(&bp->lock);
1007 b44_enable_ints(bp);
1012 /* Free up pending packets in all rx/tx rings.
1014 * The chip has been shut down and the driver detached from
1015 * the networking, so no interrupts or new tx packets will
1016 * end up in the driver. bp->lock is not held and we are not
1017 * in an interrupt context and thus may sleep.
1019 static void b44_free_rings(struct b44 *bp)
1021 struct ring_info *rp;
1024 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1025 rp = &bp->rx_buffers[i];
1027 if (rp->skb == NULL)
1029 pci_unmap_single(bp->pdev,
1030 pci_unmap_addr(rp, mapping),
1032 PCI_DMA_FROMDEVICE);
1033 dev_kfree_skb_any(rp->skb);
1037 /* XXX needs changes once NETIF_F_SG is set... */
1038 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1039 rp = &bp->tx_buffers[i];
1041 if (rp->skb == NULL)
1043 pci_unmap_single(bp->pdev,
1044 pci_unmap_addr(rp, mapping),
1047 dev_kfree_skb_any(rp->skb);
1052 /* Initialize tx/rx rings for packet processing.
1054 * The chip has been shut down and the driver detached from
1055 * the networking, so no interrupts or new tx packets will
1056 * end up in the driver. bp->lock is not held and we are not
1057 * in an interrupt context and thus may sleep.
1059 static void b44_init_rings(struct b44 *bp)
1065 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1066 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1068 for (i = 0; i < bp->rx_pending; i++) {
1069 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1075 * Must not be invoked with interrupt sources disabled and
1076 * the hardware shutdown down.
1078 static void b44_free_consistent(struct b44 *bp)
1080 if (bp->rx_buffers) {
1081 kfree(bp->rx_buffers);
1082 bp->rx_buffers = NULL;
1084 if (bp->tx_buffers) {
1085 kfree(bp->tx_buffers);
1086 bp->tx_buffers = NULL;
1089 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1090 bp->rx_ring, bp->rx_ring_dma);
1094 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1095 bp->tx_ring, bp->tx_ring_dma);
1101 * Must not be invoked with interrupt sources disabled and
1102 * the hardware shutdown down. Can sleep.
1104 static int b44_alloc_consistent(struct b44 *bp)
1108 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1109 bp->rx_buffers = kmalloc(size, GFP_KERNEL);
1110 if (!bp->rx_buffers)
1112 memset(bp->rx_buffers, 0, size);
1114 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1115 bp->tx_buffers = kmalloc(size, GFP_KERNEL);
1116 if (!bp->tx_buffers)
1118 memset(bp->tx_buffers, 0, size);
1120 size = DMA_TABLE_BYTES;
1121 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1125 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1132 b44_free_consistent(bp);
1136 /* bp->lock is held. */
1137 static void b44_clear_stats(struct b44 *bp)
1141 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1142 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1144 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1148 /* bp->lock is held. */
1149 static void b44_chip_reset(struct b44 *bp)
1151 if (ssb_is_core_up(bp)) {
1152 bw32(bp, B44_RCV_LAZY, 0);
1153 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1154 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1155 bw32(bp, B44_DMATX_CTRL, 0);
1156 bp->tx_prod = bp->tx_cons = 0;
1157 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1158 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1161 bw32(bp, B44_DMARX_CTRL, 0);
1162 bp->rx_prod = bp->rx_cons = 0;
1164 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1171 b44_clear_stats(bp);
1173 /* Make PHY accessible. */
1174 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1175 (0x0d & MDIO_CTRL_MAXF_MASK)));
1176 br32(bp, B44_MDIO_CTRL);
1178 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1179 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1180 br32(bp, B44_ENET_CTRL);
1181 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1183 u32 val = br32(bp, B44_DEVCTRL);
1185 if (val & DEVCTRL_EPR) {
1186 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1187 br32(bp, B44_DEVCTRL);
1190 bp->flags |= B44_FLAG_INTERNAL_PHY;
1194 /* bp->lock is held. */
1195 static void b44_halt(struct b44 *bp)
1197 b44_disable_ints(bp);
1201 /* bp->lock is held. */
1202 static void __b44_set_mac_addr(struct b44 *bp)
1204 bw32(bp, B44_CAM_CTRL, 0);
1205 if (!(bp->dev->flags & IFF_PROMISC)) {
1208 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1209 val = br32(bp, B44_CAM_CTRL);
1210 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1214 static int b44_set_mac_addr(struct net_device *dev, void *p)
1216 struct b44 *bp = netdev_priv(dev);
1217 struct sockaddr *addr = p;
1219 if (netif_running(dev))
1222 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1224 spin_lock_irq(&bp->lock);
1225 __b44_set_mac_addr(bp);
1226 spin_unlock_irq(&bp->lock);
1231 /* Called at device open time to get the chip ready for
1232 * packet processing. Invoked with bp->lock held.
1234 static void __b44_set_rx_mode(struct net_device *);
1235 static void b44_init_hw(struct b44 *bp)
1243 /* Enable CRC32, set proper LED modes and power on PHY */
1244 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1245 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1247 /* This sets the MAC address too. */
1248 __b44_set_rx_mode(bp->dev);
1250 /* MTU + eth header + possible VLAN tag + struct rx_header */
1251 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1252 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1254 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1255 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1256 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1257 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1258 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1259 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1261 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1262 bp->rx_prod = bp->rx_pending;
1264 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1266 val = br32(bp, B44_ENET_CTRL);
1267 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1270 static int b44_open(struct net_device *dev)
1272 struct b44 *bp = netdev_priv(dev);
1275 err = b44_alloc_consistent(bp);
1279 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1283 spin_lock_irq(&bp->lock);
1287 bp->flags |= B44_FLAG_INIT_COMPLETE;
1289 spin_unlock_irq(&bp->lock);
1291 init_timer(&bp->timer);
1292 bp->timer.expires = jiffies + HZ;
1293 bp->timer.data = (unsigned long) bp;
1294 bp->timer.function = b44_timer;
1295 add_timer(&bp->timer);
1297 b44_enable_ints(bp);
1302 b44_free_consistent(bp);
1307 /*static*/ void b44_dump_state(struct b44 *bp)
1309 u32 val32, val32_2, val32_3, val32_4, val32_5;
1312 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1313 printk("DEBUG: PCI status [%04x] \n", val16);
1318 #ifdef CONFIG_NET_POLL_CONTROLLER
1320 * Polling receive - used by netconsole and other diagnostic tools
1321 * to allow network i/o with interrupts disabled.
1323 static void b44_poll_controller(struct net_device *dev)
1325 disable_irq(dev->irq);
1326 b44_interrupt(dev->irq, dev, NULL);
1327 enable_irq(dev->irq);
1331 static int b44_close(struct net_device *dev)
1333 struct b44 *bp = netdev_priv(dev);
1335 netif_stop_queue(dev);
1337 del_timer_sync(&bp->timer);
1339 spin_lock_irq(&bp->lock);
1346 bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1347 netif_carrier_off(bp->dev);
1349 spin_unlock_irq(&bp->lock);
1351 free_irq(dev->irq, dev);
1353 b44_free_consistent(bp);
1358 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1360 struct b44 *bp = netdev_priv(dev);
1361 struct net_device_stats *nstat = &bp->stats;
1362 struct b44_hw_stats *hwstat = &bp->hw_stats;
1364 /* Convert HW stats into netdevice stats. */
1365 nstat->rx_packets = hwstat->rx_pkts;
1366 nstat->tx_packets = hwstat->tx_pkts;
1367 nstat->rx_bytes = hwstat->rx_octets;
1368 nstat->tx_bytes = hwstat->tx_octets;
1369 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1370 hwstat->tx_oversize_pkts +
1371 hwstat->tx_underruns +
1372 hwstat->tx_excessive_cols +
1373 hwstat->tx_late_cols);
1374 nstat->multicast = hwstat->tx_multicast_pkts;
1375 nstat->collisions = hwstat->tx_total_cols;
1377 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1378 hwstat->rx_undersize);
1379 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1380 nstat->rx_frame_errors = hwstat->rx_align_errs;
1381 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1382 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1383 hwstat->rx_oversize_pkts +
1384 hwstat->rx_missed_pkts +
1385 hwstat->rx_crc_align_errs +
1386 hwstat->rx_undersize +
1387 hwstat->rx_crc_errs +
1388 hwstat->rx_align_errs +
1389 hwstat->rx_symbol_errs);
1391 nstat->tx_aborted_errors = hwstat->tx_underruns;
1393 /* Carrier lost counter seems to be broken for some devices */
1394 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1400 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1402 struct dev_mc_list *mclist;
1405 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1406 mclist = dev->mc_list;
1407 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1408 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1413 static void __b44_set_rx_mode(struct net_device *dev)
1415 struct b44 *bp = netdev_priv(dev);
1418 unsigned char zero[6] = {0,0,0,0,0,0};
1420 val = br32(bp, B44_RXCONFIG);
1421 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1422 if (dev->flags & IFF_PROMISC) {
1423 val |= RXCONFIG_PROMISC;
1424 bw32(bp, B44_RXCONFIG, val);
1426 __b44_set_mac_addr(bp);
1428 if (dev->flags & IFF_ALLMULTI)
1429 val |= RXCONFIG_ALLMULTI;
1431 i=__b44_load_mcast(bp, dev);
1434 __b44_cam_write(bp, zero, i);
1436 bw32(bp, B44_RXCONFIG, val);
1437 val = br32(bp, B44_CAM_CTRL);
1438 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1442 static void b44_set_rx_mode(struct net_device *dev)
1444 struct b44 *bp = netdev_priv(dev);
1446 spin_lock_irq(&bp->lock);
1447 __b44_set_rx_mode(dev);
1448 spin_unlock_irq(&bp->lock);
1451 static u32 b44_get_msglevel(struct net_device *dev)
1453 struct b44 *bp = netdev_priv(dev);
1454 return bp->msg_enable;
1457 static void b44_set_msglevel(struct net_device *dev, u32 value)
1459 struct b44 *bp = netdev_priv(dev);
1460 bp->msg_enable = value;
1463 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1465 struct b44 *bp = netdev_priv(dev);
1466 struct pci_dev *pci_dev = bp->pdev;
1468 strcpy (info->driver, DRV_MODULE_NAME);
1469 strcpy (info->version, DRV_MODULE_VERSION);
1470 strcpy (info->bus_info, pci_name(pci_dev));
1473 static int b44_nway_reset(struct net_device *dev)
1475 struct b44 *bp = netdev_priv(dev);
1479 spin_lock_irq(&bp->lock);
1480 b44_readphy(bp, MII_BMCR, &bmcr);
1481 b44_readphy(bp, MII_BMCR, &bmcr);
1483 if (bmcr & BMCR_ANENABLE) {
1484 b44_writephy(bp, MII_BMCR,
1485 bmcr | BMCR_ANRESTART);
1488 spin_unlock_irq(&bp->lock);
1493 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1495 struct b44 *bp = netdev_priv(dev);
1497 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1499 cmd->supported = (SUPPORTED_Autoneg);
1500 cmd->supported |= (SUPPORTED_100baseT_Half |
1501 SUPPORTED_100baseT_Full |
1502 SUPPORTED_10baseT_Half |
1503 SUPPORTED_10baseT_Full |
1506 cmd->advertising = 0;
1507 if (bp->flags & B44_FLAG_ADV_10HALF)
1508 cmd->advertising |= ADVERTISE_10HALF;
1509 if (bp->flags & B44_FLAG_ADV_10FULL)
1510 cmd->advertising |= ADVERTISE_10FULL;
1511 if (bp->flags & B44_FLAG_ADV_100HALF)
1512 cmd->advertising |= ADVERTISE_100HALF;
1513 if (bp->flags & B44_FLAG_ADV_100FULL)
1514 cmd->advertising |= ADVERTISE_100FULL;
1515 cmd->advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1516 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1517 SPEED_100 : SPEED_10;
1518 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1519 DUPLEX_FULL : DUPLEX_HALF;
1521 cmd->phy_address = bp->phy_addr;
1522 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1523 XCVR_INTERNAL : XCVR_EXTERNAL;
1524 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1525 AUTONEG_DISABLE : AUTONEG_ENABLE;
1531 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1533 struct b44 *bp = netdev_priv(dev);
1535 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1538 /* We do not support gigabit. */
1539 if (cmd->autoneg == AUTONEG_ENABLE) {
1540 if (cmd->advertising &
1541 (ADVERTISED_1000baseT_Half |
1542 ADVERTISED_1000baseT_Full))
1544 } else if ((cmd->speed != SPEED_100 &&
1545 cmd->speed != SPEED_10) ||
1546 (cmd->duplex != DUPLEX_HALF &&
1547 cmd->duplex != DUPLEX_FULL)) {
1551 spin_lock_irq(&bp->lock);
1553 if (cmd->autoneg == AUTONEG_ENABLE) {
1554 bp->flags &= ~B44_FLAG_FORCE_LINK;
1555 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1556 B44_FLAG_ADV_10FULL |
1557 B44_FLAG_ADV_100HALF |
1558 B44_FLAG_ADV_100FULL);
1559 if (cmd->advertising & ADVERTISE_10HALF)
1560 bp->flags |= B44_FLAG_ADV_10HALF;
1561 if (cmd->advertising & ADVERTISE_10FULL)
1562 bp->flags |= B44_FLAG_ADV_10FULL;
1563 if (cmd->advertising & ADVERTISE_100HALF)
1564 bp->flags |= B44_FLAG_ADV_100HALF;
1565 if (cmd->advertising & ADVERTISE_100FULL)
1566 bp->flags |= B44_FLAG_ADV_100FULL;
1568 bp->flags |= B44_FLAG_FORCE_LINK;
1569 if (cmd->speed == SPEED_100)
1570 bp->flags |= B44_FLAG_100_BASE_T;
1571 if (cmd->duplex == DUPLEX_FULL)
1572 bp->flags |= B44_FLAG_FULL_DUPLEX;
1577 spin_unlock_irq(&bp->lock);
1582 static void b44_get_ringparam(struct net_device *dev,
1583 struct ethtool_ringparam *ering)
1585 struct b44 *bp = netdev_priv(dev);
1587 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1588 ering->rx_pending = bp->rx_pending;
1590 /* XXX ethtool lacks a tx_max_pending, oops... */
1593 static int b44_set_ringparam(struct net_device *dev,
1594 struct ethtool_ringparam *ering)
1596 struct b44 *bp = netdev_priv(dev);
1598 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1599 (ering->rx_mini_pending != 0) ||
1600 (ering->rx_jumbo_pending != 0) ||
1601 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1604 spin_lock_irq(&bp->lock);
1606 bp->rx_pending = ering->rx_pending;
1607 bp->tx_pending = ering->tx_pending;
1612 netif_wake_queue(bp->dev);
1613 spin_unlock_irq(&bp->lock);
1615 b44_enable_ints(bp);
1620 static void b44_get_pauseparam(struct net_device *dev,
1621 struct ethtool_pauseparam *epause)
1623 struct b44 *bp = netdev_priv(dev);
1626 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1628 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1630 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1633 static int b44_set_pauseparam(struct net_device *dev,
1634 struct ethtool_pauseparam *epause)
1636 struct b44 *bp = netdev_priv(dev);
1638 spin_lock_irq(&bp->lock);
1639 if (epause->autoneg)
1640 bp->flags |= B44_FLAG_PAUSE_AUTO;
1642 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1643 if (epause->rx_pause)
1644 bp->flags |= B44_FLAG_RX_PAUSE;
1646 bp->flags &= ~B44_FLAG_RX_PAUSE;
1647 if (epause->tx_pause)
1648 bp->flags |= B44_FLAG_TX_PAUSE;
1650 bp->flags &= ~B44_FLAG_TX_PAUSE;
1651 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1656 __b44_set_flow_ctrl(bp, bp->flags);
1658 spin_unlock_irq(&bp->lock);
1660 b44_enable_ints(bp);
1665 static struct ethtool_ops b44_ethtool_ops = {
1666 .get_drvinfo = b44_get_drvinfo,
1667 .get_settings = b44_get_settings,
1668 .set_settings = b44_set_settings,
1669 .nway_reset = b44_nway_reset,
1670 .get_link = ethtool_op_get_link,
1671 .get_ringparam = b44_get_ringparam,
1672 .set_ringparam = b44_set_ringparam,
1673 .get_pauseparam = b44_get_pauseparam,
1674 .set_pauseparam = b44_set_pauseparam,
1675 .get_msglevel = b44_get_msglevel,
1676 .set_msglevel = b44_set_msglevel,
1679 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1681 struct mii_ioctl_data *data = if_mii(ifr);
1682 struct b44 *bp = netdev_priv(dev);
1685 spin_lock_irq(&bp->lock);
1686 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1687 spin_unlock_irq(&bp->lock);
1692 /* Read 128-bytes of EEPROM. */
1693 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1696 u16 *ptr = (u16 *) data;
1698 for (i = 0; i < 128; i += 2)
1699 ptr[i / 2] = readw(bp->regs + 4096 + i);
1704 static int __devinit b44_get_invariants(struct b44 *bp)
1709 err = b44_read_eeprom(bp, &eeprom[0]);
1713 bp->dev->dev_addr[0] = eeprom[79];
1714 bp->dev->dev_addr[1] = eeprom[78];
1715 bp->dev->dev_addr[2] = eeprom[81];
1716 bp->dev->dev_addr[3] = eeprom[80];
1717 bp->dev->dev_addr[4] = eeprom[83];
1718 bp->dev->dev_addr[5] = eeprom[82];
1720 bp->phy_addr = eeprom[90] & 0x1f;
1722 /* With this, plus the rx_header prepended to the data by the
1723 * hardware, we'll land the ethernet header on a 2-byte boundary.
1727 bp->imask = IMASK_DEF;
1729 bp->core_unit = ssb_core_unit(bp);
1730 bp->dma_offset = SB_PCI_DMA;
1732 /* XXX - really required?
1733 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1739 static int __devinit b44_init_one(struct pci_dev *pdev,
1740 const struct pci_device_id *ent)
1742 static int b44_version_printed = 0;
1743 unsigned long b44reg_base, b44reg_len;
1744 struct net_device *dev;
1748 if (b44_version_printed++ == 0)
1749 printk(KERN_INFO "%s", version);
1751 err = pci_enable_device(pdev);
1753 printk(KERN_ERR PFX "Cannot enable PCI device, "
1758 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1759 printk(KERN_ERR PFX "Cannot find proper PCI device "
1760 "base address, aborting.\n");
1762 goto err_out_disable_pdev;
1765 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1767 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1769 goto err_out_disable_pdev;
1772 pci_set_master(pdev);
1774 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1776 printk(KERN_ERR PFX "No usable DMA configuration, "
1778 goto err_out_free_res;
1781 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1783 printk(KERN_ERR PFX "No usable DMA configuration, "
1785 goto err_out_free_res;
1788 b44reg_base = pci_resource_start(pdev, 0);
1789 b44reg_len = pci_resource_len(pdev, 0);
1791 dev = alloc_etherdev(sizeof(*bp));
1793 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1795 goto err_out_free_res;
1798 SET_MODULE_OWNER(dev);
1799 SET_NETDEV_DEV(dev,&pdev->dev);
1801 /* No interesting netdevice features in this card... */
1804 bp = netdev_priv(dev);
1808 bp->msg_enable = (1 << b44_debug) - 1;
1810 bp->msg_enable = B44_DEF_MSG_ENABLE;
1812 spin_lock_init(&bp->lock);
1814 bp->regs = ioremap(b44reg_base, b44reg_len);
1815 if (bp->regs == 0UL) {
1816 printk(KERN_ERR PFX "Cannot map device registers, "
1819 goto err_out_free_dev;
1822 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1823 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1825 dev->open = b44_open;
1826 dev->stop = b44_close;
1827 dev->hard_start_xmit = b44_start_xmit;
1828 dev->get_stats = b44_get_stats;
1829 dev->set_multicast_list = b44_set_rx_mode;
1830 dev->set_mac_address = b44_set_mac_addr;
1831 dev->do_ioctl = b44_ioctl;
1832 dev->tx_timeout = b44_tx_timeout;
1833 dev->poll = b44_poll;
1835 dev->watchdog_timeo = B44_TX_TIMEOUT;
1836 #ifdef CONFIG_NET_POLL_CONTROLLER
1837 dev->poll_controller = b44_poll_controller;
1839 dev->change_mtu = b44_change_mtu;
1840 dev->irq = pdev->irq;
1841 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1843 err = b44_get_invariants(bp);
1845 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1847 goto err_out_iounmap;
1850 bp->mii_if.dev = dev;
1851 bp->mii_if.mdio_read = b44_mii_read;
1852 bp->mii_if.mdio_write = b44_mii_write;
1853 bp->mii_if.phy_id = bp->phy_addr;
1854 bp->mii_if.phy_id_mask = 0x1f;
1855 bp->mii_if.reg_num_mask = 0x1f;
1857 /* By default, advertise all speed/duplex settings. */
1858 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1859 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1861 /* By default, auto-negotiate PAUSE. */
1862 bp->flags |= B44_FLAG_PAUSE_AUTO;
1864 err = register_netdev(dev);
1866 printk(KERN_ERR PFX "Cannot register net device, "
1868 goto err_out_iounmap;
1871 pci_set_drvdata(pdev, dev);
1873 pci_save_state(bp->pdev);
1875 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1876 for (i = 0; i < 6; i++)
1877 printk("%2.2x%c", dev->dev_addr[i],
1878 i == 5 ? '\n' : ':');
1889 pci_release_regions(pdev);
1891 err_out_disable_pdev:
1892 pci_disable_device(pdev);
1893 pci_set_drvdata(pdev, NULL);
1897 static void __devexit b44_remove_one(struct pci_dev *pdev)
1899 struct net_device *dev = pci_get_drvdata(pdev);
1902 struct b44 *bp = netdev_priv(dev);
1904 unregister_netdev(dev);
1907 pci_release_regions(pdev);
1908 pci_disable_device(pdev);
1909 pci_set_drvdata(pdev, NULL);
1913 static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
1915 struct net_device *dev = pci_get_drvdata(pdev);
1916 struct b44 *bp = netdev_priv(dev);
1918 if (!netif_running(dev))
1921 del_timer_sync(&bp->timer);
1923 spin_lock_irq(&bp->lock);
1926 netif_carrier_off(bp->dev);
1927 netif_device_detach(bp->dev);
1930 spin_unlock_irq(&bp->lock);
1934 static int b44_resume(struct pci_dev *pdev)
1936 struct net_device *dev = pci_get_drvdata(pdev);
1937 struct b44 *bp = netdev_priv(dev);
1939 pci_restore_state(pdev);
1941 if (!netif_running(dev))
1944 spin_lock_irq(&bp->lock);
1948 netif_device_attach(bp->dev);
1949 spin_unlock_irq(&bp->lock);
1951 bp->timer.expires = jiffies + HZ;
1952 add_timer(&bp->timer);
1954 b44_enable_ints(bp);
1958 static struct pci_driver b44_driver = {
1959 .name = DRV_MODULE_NAME,
1960 .id_table = b44_pci_tbl,
1961 .probe = b44_init_one,
1962 .remove = __devexit_p(b44_remove_one),
1963 .suspend = b44_suspend,
1964 .resume = b44_resume,
1967 static int __init b44_init(void)
1969 return pci_module_init(&b44_driver);
1972 static void __exit b44_cleanup(void)
1974 pci_unregister_driver(&b44_driver);
1977 module_init(b44_init);
1978 module_exit(b44_cleanup);