1 /******************************************************************************/
3 /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2006 Broadcom */
5 /* All rights reserved. */
7 /* This program is free software; you can redistribute it and/or modify */
8 /* it under the terms of the GNU General Public License as published by */
9 /* the Free Software Foundation, located in the file LICENSE. */
12 /******************************************************************************/
18 /******************************************************************************/
19 /* Local functions. */
20 /******************************************************************************/
22 LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
23 LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
25 static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice);
26 static LM_VOID LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice);
28 LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice);
29 LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice);
31 static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice);
32 static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice);
33 STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice,
34 LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd);
35 #ifdef INCLUDE_TBI_SUPPORT
36 STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice);
37 STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice);
39 STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice);
40 STATIC LM_VOID LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice);
41 STATIC LM_STATUS LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice);
42 STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid);
43 LM_VOID LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2);
44 STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
45 LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize);
46 STATIC LM_STATUS LM_DisableChip(PLM_DEVICE_BLOCK pDevice);
47 STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice);
48 STATIC LM_STATUS LM_DisableFW(PLM_DEVICE_BLOCK pDevice);
49 STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
51 STATIC LM_VOID LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice,
53 STATIC LM_VOID LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice,
55 STATIC LM_VOID LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice,
57 STATIC void LM_GetPhyId(LM_DEVICE_BLOCK *pDevice);
59 /******************************************************************************/
60 /* External functions. */
61 /******************************************************************************/
63 LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice);
64 #ifdef INCLUDE_TCP_SEG_SUPPORT
65 LM_STATUS LM_LoadStkOffLdFirmware(PLM_DEVICE_BLOCK pDevice);
66 LM_UINT32 LM_GetStkOffLdFirmwareSize(PLM_DEVICE_BLOCK pDevice);
70 LM_RegRd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
72 #ifdef PCIX_TARGET_WORKAROUND
73 if (pDevice->Flags & UNDI_FIX_FLAG)
75 return (LM_RegRdInd(pDevice, Register));
80 return (REG_RD_OFFSET(pDevice, Register));
84 /* Mainly used to flush posted write before delaying */
86 LM_RegRdBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
90 #ifdef PCIX_TARGET_WORKAROUND
91 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG)
98 if (pDevice->Flags & REG_RD_BACK_FLAG)
101 dummy = REG_RD_OFFSET(pDevice, Register);
106 LM_RegWr(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32,
109 #ifdef PCIX_TARGET_WORKAROUND
110 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG)
112 LM_RegWrInd(pDevice, Register, Value32);
119 REG_WR_OFFSET(pDevice, Register, Value32);
120 if (ReadBack && (pDevice->Flags & REG_RD_BACK_FLAG))
122 dummy = REG_RD_OFFSET(pDevice, Register);
127 /******************************************************************************/
131 /******************************************************************************/
134 PLM_DEVICE_BLOCK pDevice,
135 LM_UINT32 Register) {
138 MM_ACQUIRE_UNDI_LOCK(pDevice);
139 MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
140 MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32);
141 MM_RELEASE_UNDI_LOCK(pDevice);
143 return MM_SWAP_LE32(Value32);
148 /******************************************************************************/
152 /******************************************************************************/
155 PLM_DEVICE_BLOCK pDevice,
159 MM_ACQUIRE_UNDI_LOCK(pDevice);
160 MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
161 MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, MM_SWAP_LE32(Value32));
162 MM_RELEASE_UNDI_LOCK(pDevice);
167 /******************************************************************************/
171 /******************************************************************************/
174 PLM_DEVICE_BLOCK pDevice,
178 MM_ACQUIRE_UNDI_LOCK(pDevice);
179 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
180 MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
181 MM_RELEASE_UNDI_LOCK(pDevice);
183 return MM_SWAP_LE32(Value32);
188 /******************************************************************************/
192 /******************************************************************************/
195 PLM_DEVICE_BLOCK pDevice,
198 MM_ACQUIRE_UNDI_LOCK(pDevice);
199 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
200 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, MM_SWAP_LE32(Value32));
201 MM_RELEASE_UNDI_LOCK(pDevice);
205 /******************************************************************************/
209 /******************************************************************************/
212 PLM_DEVICE_BLOCK pDevice) {
215 PT3_RCV_BD pRcvBd = 0;
216 LM_UINT32 StdBdAdded = 0;
217 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
218 LM_UINT32 JumboBdAdded = 0;
219 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
220 LM_UINT32 ConIdx, Idx;
223 Lmstatus = LM_STATUS_SUCCESS;
225 if (pDevice->Flags & RX_BD_LIMIT_64_FLAG)
227 ConIdx = pDevice->pStatusBlkVirt->RcvStdConIdx;
228 Diff = (pDevice->RxStdProdIdx - ConIdx) &
229 T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
232 if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container))
234 pDevice->QueueAgain = TRUE;
236 return LM_STATUS_SUCCESS;
240 pDevice->QueueAgain = FALSE;
242 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
244 switch(pPacket->u.Rx.RcvProdRing) {
245 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
246 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
247 /* Initialize the buffer descriptor. */
248 Idx = pDevice->RxJumboProdIdx;
249 pRcvBd = &pDevice->pRxJumboBdVirt[Idx];
251 pPacket->u.Rx.RcvRingProdIdx = Idx;
252 pDevice->RxJumboRing[Idx] = pPacket;
253 /* Update the producer index. */
254 pDevice->RxJumboProdIdx = (Idx + 1) &
255 T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
259 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
261 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
262 /* Initialize the buffer descriptor. */
263 Idx = pDevice->RxStdProdIdx;
264 pRcvBd = &pDevice->pRxStdBdVirt[Idx];
266 pPacket->u.Rx.RcvRingProdIdx = Idx;
267 pDevice->RxStdRing[Idx] = pPacket;
268 /* Update the producer index. */
269 pDevice->RxStdProdIdx = (Idx + 1) &
270 T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
275 case T3_UNKNOWN_RCV_PROD_RING:
277 Lmstatus = LM_STATUS_FAILURE;
281 /* Bail out if there is any error. */
282 if(Lmstatus != LM_STATUS_SUCCESS)
287 /* Initialize the receive buffer pointer */
288 MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
290 /* The opaque field may point to an offset from a fix addr. */
291 pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
292 MM_UINT_PTR(pDevice->pPacketDescBase));
294 if ((pDevice->Flags & RX_BD_LIMIT_64_FLAG) &&
295 ((Diff + StdBdAdded) >= 63))
297 if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container))
299 pDevice->QueueAgain = TRUE;
303 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
307 /* Update the procedure index. */
310 MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low,
311 pDevice->RxStdProdIdx);
312 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
314 MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low);
317 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
320 MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low,
321 pDevice->RxJumboProdIdx);
322 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
324 MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low);
327 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
330 } /* LM_QueueRxPackets */
335 #define EEPROM_CMD_TIMEOUT 100000
336 #define NVRAM_CMD_TIMEOUT 100000
339 /******************************************************************************/
343 /******************************************************************************/
344 STATIC LM_STATUS LM_NVRAM_AcquireLock( PLM_DEVICE_BLOCK pDevice )
350 status = LM_STATUS_SUCCESS;
352 /* Request access to the flash interface. */
353 REG_WR( pDevice, Nvram.SwArb, SW_ARB_REQ_SET1 );
356 * The worst case wait time for Nvram arbitration
357 * using serial eprom is about 45 msec on a 5704
358 * with the other channel loading boot code.
360 for( i = 0; i < NVRAM_CMD_TIMEOUT; i++ )
362 value32 = REG_RD( pDevice, Nvram.SwArb );
363 if( value32 & SW_ARB_GNT1 )
372 } /* LM_NVRAM_AcquireLock */
376 /******************************************************************************/
380 /******************************************************************************/
381 STATIC LM_STATUS LM_NVRAM_ReleaseLock( PLM_DEVICE_BLOCK pDevice )
383 /* Relinquish nvram interface. */
384 REG_WR( pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 );
385 REG_RD_BACK( pDevice, Nvram.SwArb );
387 return LM_STATUS_SUCCESS;
388 } /* LM_NVRAM_ReleaseLock */
392 /******************************************************************************/
396 /******************************************************************************/
398 LM_EEPROM_ExecuteCommand( PLM_DEVICE_BLOCK pDevice, LM_UINT32 cmd )
404 status = LM_STATUS_SUCCESS;
406 REG_WR( pDevice, Grc.EepromAddr, cmd );
408 for( i = 0; i < EEPROM_CMD_TIMEOUT; i++ )
410 value32 = REG_RD( pDevice, Grc.EepromAddr );
411 if( value32 & SEEPROM_ADDR_COMPLETE )
418 if( i == EEPROM_CMD_TIMEOUT )
420 printk( KERN_WARNING "EEPROM command (0x%x) timed out!\n", cmd );
421 status = LM_STATUS_FAILURE;
425 } /* LM_EEPROM_ExecuteCommand */
429 /******************************************************************************/
433 /******************************************************************************/
435 LM_NVRAM_ExecuteCommand( PLM_DEVICE_BLOCK pDevice, LM_UINT32 cmd )
441 status = LM_STATUS_SUCCESS;
443 REG_WR( pDevice, Nvram.Cmd, cmd );
444 REG_RD_BACK( pDevice, Nvram.Cmd );
447 /* Wait for the command to complete. */
448 for( i = 0; i < NVRAM_CMD_TIMEOUT; i++ )
450 value32 = REG_RD( pDevice, Nvram.Cmd );
451 if( value32 & NVRAM_CMD_DONE )
458 if( i == NVRAM_CMD_TIMEOUT )
460 printk( KERN_WARNING "NVRAM command (0x%x) timed out!\n", cmd );
461 status = LM_STATUS_FAILURE;
465 } /* LM_NVRAM_ExecuteCommand */
469 /******************************************************************************/
473 /******************************************************************************/
475 LM_EEPROM_Read_UINT32( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
483 Dev = offset / pDevice->flashinfo.chipsize;
484 Addr = offset % pDevice->flashinfo.chipsize;
486 value32 = REG_RD( pDevice, Grc.EepromAddr );
487 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
488 SEEPROM_ADDR_RW_MASK);
489 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
490 SEEPROM_ADDR_START | SEEPROM_ADDR_READ;
492 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
493 if( status == LM_STATUS_SUCCESS )
495 value32 = REG_RD( pDevice, Grc.EepromData );
497 /* The endianess of the eeprom and flash interface is different */
498 *data = MM_SWAP_LE32( value32 );
502 } /* LM_EEPROM_Read_UINT32 */
506 /******************************************************************************/
510 /******************************************************************************/
512 LM_NVRAM_Read_UINT32( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
520 if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
521 pDevice->flashinfo.buffered == TRUE )
524 * One supported flash part has 9 address bits to address a
525 * particular page and another 9 address bits to address a
526 * particular byte within that page.
530 pagenmbr = offset / pDevice->flashinfo.pagesize;
531 pagenmbr = pagenmbr << ATMEL_AT45DB0X1B_PAGE_POS;
533 physaddr = pagenmbr + (offset % pDevice->flashinfo.pagesize);
540 REG_WR( pDevice, Nvram.Addr, physaddr );
542 ctrlreg = NVRAM_CMD_DONE | NVRAM_CMD_DO_IT |
543 NVRAM_CMD_LAST | NVRAM_CMD_FIRST | NVRAM_CMD_RD;
545 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
546 if( status == LM_STATUS_SUCCESS )
548 value32 = REG_RD( pDevice, Nvram.ReadData );
551 * Data is swapped so that the byte stream is the same
552 * in big and little endian systems. Caller will do
553 * additional swapping depending on how it wants to
556 *data = MM_SWAP_BE32( value32 );
560 } /* LM_NVRAM_Read_UINT32 */
564 /******************************************************************************/
568 /******************************************************************************/
570 LM_NVRAM_ReadBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
571 LM_UINT8 * data, LM_UINT32 size )
578 status = LM_STATUS_SUCCESS;
582 /* Make sure the read is word aligned. */
583 value32 = offset & 0x3;
586 bytecnt = sizeof(LM_UINT32) - value32;
588 srcptr = (LM_UINT8 *)(&value32) + value32;
592 bytecnt = sizeof(LM_UINT32);
593 srcptr = (LM_UINT8 *)(&value32);
601 if( T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
602 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701 )
604 status = LM_NVRAM_Read_UINT32( pDevice, offset, &value32 );
608 status = LM_EEPROM_Read_UINT32( pDevice, offset, &value32 );
611 if( status != LM_STATUS_SUCCESS )
616 memcpy( data, srcptr, bytecnt );
618 offset += sizeof(LM_UINT32);
624 } /* LM_NVRAM_ReadBlock */
628 /******************************************************************************/
632 /******************************************************************************/
634 LM_EEPROM_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
641 * Initialize the chipsize to the largest EEPROM size we support.
642 * This will intentionally restrict our sizing operations to the
645 pDevice->flashinfo.chipsize = ATMEL_AT24C512_CHIP_SIZE;
649 /* If anything fails, use the smallest chip as the default chip size. */
650 cursize = ATMEL_AT24C64_CHIP_SIZE;
652 status = LM_NvramRead(pDevice, 0, &value32);
653 if( status != LM_STATUS_SUCCESS )
658 value32 = MM_SWAP_BE32(value32);
659 if( value32 != 0x669955aa )
665 * Size the chip by reading offsets at increasing powers of two.
666 * When we encounter our validation signature, we know the addressing
667 * has wrapped around, and thus have our chip size.
669 while( cursize < ATMEL_AT24C64_CHIP_SIZE )
671 status = LM_NvramRead(pDevice, cursize, &value32);
672 if( status != LM_STATUS_SUCCESS )
674 cursize = ATMEL_AT24C64_CHIP_SIZE;
678 value32 = MM_SWAP_BE32(value32);
679 if( value32 == 0x669955aa )
689 pDevice->flashinfo.pagesize = cursize;
692 } /* LM_EEPROM_ReadSize */
694 /******************************************************************************/
698 /******************************************************************************/
700 LM_FLASH_Atmel_Buffered_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
706 /* Temporarily replace the read command with a "read ID" command. */
707 config3 = REG_RD( pDevice, Nvram.Config3 );
708 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
709 value32 |= NVRAM_READ_COMMAND(0x57);
710 REG_WR( pDevice, Nvram.Config3, value32 );
712 REG_WR( pDevice, Nvram.Addr, 0x0 );
714 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
716 /* Restore the original read command. */
717 REG_WR( pDevice, Nvram.Config3, config3 );
718 if( status == LM_STATUS_SUCCESS )
720 switch( value32 & 0x3c )
723 *size = (1 * (1<<20))/8;
726 *size = (2 * (1<<20))/8;
729 *size = (4 * (1<<20))/8;
732 *size = (8 * (1<<20))/8;
738 } /* LM_FLASH_Atmel_Buffered_ReadSize */
742 /******************************************************************************/
746 /******************************************************************************/
748 LM_FLASH_ST_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
756 /* We need to get the size through pass-thru mode. */
757 config1 = REG_RD( pDevice, Nvram.Config1 );
758 value32 = config1 | FLASH_PASS_THRU_MODE;
759 REG_WR( pDevice, Nvram.Config1, value32 );
761 /* Issue the "read ID" command. */
762 REG_WR( pDevice, Nvram.WriteData, 0x9f );
764 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_FIRST | NVRAM_CMD_WR;
765 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
766 if( status == LM_STATUS_FAILURE )
771 /* Read in the "read ID" response. */
772 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
774 /* Discard the first three bytes. */
775 for( i = 0; i < 2; i++ )
777 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
778 if( status == LM_STATUS_FAILURE )
783 value32 = REG_RD(pDevice, Nvram.ReadData);
786 ctrlreg |= NVRAM_CMD_LAST;
788 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
789 if( status == LM_STATUS_SUCCESS )
791 value32 = REG_RD(pDevice, Nvram.ReadData) & 0xff;
795 *size = (1 * (1<<20)) / 8;
798 *size = (2 * (1<<20)) / 8;
801 *size = (4 * (1<<20)) / 8;
804 *size = (8 * (1<<20)) / 8;
811 /* Restore the previous flash mode. */
812 REG_WR( pDevice, Nvram.Config1, config1 );
815 } /* LM_FLASH_ST_ReadSize */
819 /******************************************************************************/
823 /******************************************************************************/
825 LM_FLASH_Saifun_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
831 /* Temporarily replace the read command with a "read ID" command. */
832 config3 = REG_RD( pDevice, Nvram.Config3 );
833 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
834 value32 |= NVRAM_READ_COMMAND(0xab);
835 REG_WR( pDevice, Nvram.Config3, value32 );
837 REG_WR( pDevice, Nvram.Addr, 0x0 );
839 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
841 /* Restore the original read command. */
842 REG_WR( pDevice, Nvram.Config3, config3 );
844 if( status == LM_STATUS_SUCCESS )
846 switch( value32 & 0xff )
849 *size = (512 * (1<<10)/8);
852 *size = (1 * (1<<20)/8);
855 *size = (2 * (1<<20)/8);
861 } /* LM_FLASH_Saifun_ReadSize */
865 /******************************************************************************/
869 /******************************************************************************/
871 LM_FLASH_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
876 status = LM_NVRAM_AcquireLock( pDevice );
877 if( status == LM_STATUS_FAILURE )
882 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
884 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
886 value32 = REG_RD( pDevice, Nvram.NvmAccess );
887 value32 |= NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE;
888 REG_WR( pDevice, Nvram.NvmAccess, value32 );
892 switch( pDevice->flashinfo.jedecnum )
895 status = LM_FLASH_ST_ReadSize( pDevice, size );
898 if( pDevice->flashinfo.buffered == TRUE )
900 status = LM_FLASH_Atmel_Buffered_ReadSize( pDevice, size );
904 status = LM_STATUS_FAILURE;
908 status = LM_FLASH_Saifun_ReadSize( pDevice, size );
912 status = LM_STATUS_FAILURE;
915 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
917 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
919 value32 = REG_RD( pDevice, Nvram.NvmAccess );
920 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
921 REG_WR( pDevice, Nvram.NvmAccess, value32 );
925 LM_NVRAM_ReleaseLock( pDevice );
928 } /* LM_FLASH_ReadSize */
930 STATIC LM_VOID LM_NVRAM_Detect_570X( PLM_DEVICE_BLOCK pDevice )
934 value32 = REG_RD(pDevice, Nvram.Config1);
936 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
938 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
943 * 5705 and older products do not have bits 24 and 25 defined.
944 * If we've gotten here, then we can guarantee the flash is
945 * an Atmel AT45DB011DB.
947 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
948 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
949 pDevice->flashinfo.pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
950 pDevice->flashinfo.buffered = TRUE;
952 } /* LM_NVRAM_Detect_570X */
954 STATIC LM_VOID LM_NVRAM_Detect_5750( PLM_DEVICE_BLOCK pDevice )
958 value32 = REG_RD(pDevice, Nvram.Config1);
960 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
962 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
966 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
968 switch( value32 & FLASH_PART_5750_TYPEMASK )
970 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
971 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
972 pDevice->flashinfo.pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
973 pDevice->flashinfo.buffered = TRUE;
975 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
976 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
977 pDevice->flashinfo.pagesize = ATMEL_AT25F512_PAGE_SIZE;
978 pDevice->flashinfo.buffered = FALSE;
980 case FLASH_VENDOR_ST:
981 pDevice->flashinfo.jedecnum = JEDEC_ST;
982 pDevice->flashinfo.pagesize = ST_M45PEX0_PAGE_SIZE;
983 pDevice->flashinfo.buffered = TRUE;
985 case FLASH_VENDOR_SAIFUN:
986 pDevice->flashinfo.jedecnum = JEDEC_SAIFUN;
987 pDevice->flashinfo.pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
988 pDevice->flashinfo.buffered = FALSE;
990 case FLASH_VENDOR_SST_SMALL:
991 case FLASH_VENDOR_SST_LARGE:
992 pDevice->flashinfo.jedecnum = JEDEC_SST;
993 pDevice->flashinfo.pagesize = SST_25VF0X0_PAGE_SIZE;
994 pDevice->flashinfo.buffered = FALSE;
997 printk( KERN_ALERT "bcm5700 : Unknown NVRAM type.\n" );
998 pDevice->flashinfo.jedecnum = 0;
999 pDevice->flashinfo.romtype = 0;
1000 pDevice->flashinfo.buffered = FALSE;
1001 pDevice->flashinfo.pagesize = 0;
1003 } /* LM_NVRAM_Detect_5750 */
1005 STATIC LM_VOID LM_NVRAM_Detect_5752( PLM_DEVICE_BLOCK pDevice )
1012 value32 = REG_RD(pDevice, Nvram.Config1);
1014 if(value32 & BIT_27)
1015 pDevice->Flags |= PROTECTED_NVRAM_FLAG;
1017 switch( value32 & FLASH_PART_5752_TYPEMASK )
1019 case FLASH_PART_5752_EEPROM_ATMEL_64K:
1020 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
1021 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
1022 pDevice->flashinfo.buffered = FALSE;
1023 pDevice->flashinfo.chipsize = (64 * (1<<10)/8);
1027 case FLASH_PART_5752_EEPROM_ATMEL_376K:
1028 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
1029 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
1030 pDevice->flashinfo.buffered = FALSE;
1031 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
1035 case FLASH_PART_5752_FLASH_ATMEL_AT45DB041:
1036 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
1037 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1038 pDevice->flashinfo.buffered = TRUE;
1039 pDevice->flashinfo.chipsize = (4 * (1<<20)) / 8;
1043 case FLASH_PART_5752_FLASH_ATMEL_AT25F512:
1044 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
1045 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1046 pDevice->flashinfo.buffered = FALSE;
1047 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
1051 case FLASH_PART_5752_FLASH_ST_M25P10A:
1052 pDevice->flashinfo.jedecnum = JEDEC_ST;
1053 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1054 pDevice->flashinfo.buffered = TRUE;
1055 pDevice->flashinfo.chipsize = (1 * (1<<20)) / 8;
1058 case FLASH_PART_5752_FLASH_ST_M25P05A:
1059 pDevice->flashinfo.jedecnum = JEDEC_ST;
1060 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1061 pDevice->flashinfo.buffered = TRUE;
1062 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
1066 case FLASH_PART_5752_FLASH_ST_M45PE10:
1067 pDevice->flashinfo.jedecnum = JEDEC_ST;
1068 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1069 pDevice->flashinfo.buffered = TRUE;
1070 pDevice->flashinfo.chipsize = (1 * (1<<20)) / 8;
1074 case FLASH_PART_5752_FLASH_ST_M45PE20:
1075 pDevice->flashinfo.jedecnum = JEDEC_ST;
1076 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1077 pDevice->flashinfo.buffered = TRUE;
1078 pDevice->flashinfo.chipsize = (2 * (1<<20)) / 8;
1082 case FLASH_PART_5752_FLASH_ST_M45PE40:
1083 pDevice->flashinfo.jedecnum = JEDEC_ST;
1084 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1085 pDevice->flashinfo.buffered = TRUE;
1086 pDevice->flashinfo.chipsize = (4 * (1<<20)) / 8;
1090 printk( KERN_ALERT "bcm5700 : Unknown NVRAM type.\n" );
1093 if( pDevice->flashinfo.romtype == ROM_TYPE_FLASH )
1095 switch( value32 & FLASH_PART_5752_PAGEMASK )
1097 case FLASH_PART_5752_PAGE_SIZE_256B:
1098 pDevice->flashinfo.pagesize = 256;
1100 case FLASH_PART_5752_PAGE_SIZE_512B:
1101 pDevice->flashinfo.pagesize = 512;
1103 case FLASH_PART_5752_PAGE_SIZE_1K:
1104 pDevice->flashinfo.pagesize = 1024;
1106 case FLASH_PART_5752_PAGE_SIZE_2K:
1107 pDevice->flashinfo.pagesize = 2048;
1109 case FLASH_PART_5752_PAGE_SIZE_4K:
1110 pDevice->flashinfo.pagesize = 4096;
1112 case FLASH_PART_5752_PAGE_SIZE_264B:
1113 pDevice->flashinfo.pagesize = 264;
1116 printk( KERN_ALERT "bcm5700 : Unknown NVRAM page size.\n" );
1121 if( supported != TRUE )
1123 printk( KERN_ALERT "Flash type unsupported!!!\n" );
1124 pDevice->flashinfo.jedecnum = 0;
1125 pDevice->flashinfo.romtype = 0;
1126 pDevice->flashinfo.buffered = FALSE;
1127 pDevice->flashinfo.pagesize = 0;
1131 } /* LM_NVRAM_Detect_5752 */
1134 /******************************************************************************/
1138 /******************************************************************************/
1139 STATIC LM_VOID LM_NVRAM_Init( PLM_DEVICE_BLOCK pDevice )
1143 pDevice->NvramSize = 0;
1145 /* Intialize clock period and state machine. */
1146 Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) |
1147 SEEPROM_ADDR_FSM_RESET;
1148 REG_WR(pDevice, Grc.EepromAddr, Value32);
1149 REG_RD_BACK(pDevice, Grc.EepromAddr);
1153 /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
1154 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
1155 REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
1157 switch( T3_ASIC_REV(pDevice->ChipRevId) )
1159 case T3_ASIC_REV_5700:
1160 case T3_ASIC_REV_5701:
1161 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
1163 case T3_ASIC_REV_5752:
1164 LM_NVRAM_Detect_5752(pDevice);
1166 case T3_ASIC_REV_5714_A0:
1167 case T3_ASIC_REV_5780:
1168 case T3_ASIC_REV_5714:
1169 case T3_ASIC_REV_5750:
1170 LM_NVRAM_Detect_5750(pDevice);
1173 LM_NVRAM_Detect_570X(pDevice);
1176 /* Set the 5701 compatibility mode if we are using EEPROM. */
1177 if( T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
1178 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701 &&
1179 pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1181 Value32 = REG_RD(pDevice, Nvram.Config1);
1183 if( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1185 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1187 REG_WR(pDevice, Nvram.NvmAccess,
1188 REG_RD(pDevice, Nvram.NvmAccess) | ACCESS_EN);
1192 /* Use the new interface to read EEPROM. */
1193 Value32 &= ~FLASH_COMPAT_BYPASS;
1195 REG_WR(pDevice, Nvram.Config1, Value32);
1197 if( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1199 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1201 REG_WR(pDevice, Nvram.NvmAccess,
1202 REG_RD(pDevice, Nvram.NvmAccess) & ~ACCESS_EN);
1207 if( !(T3_ASIC_5752(pDevice->ChipRevId)) )
1209 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1211 /* The only EEPROM we support is an ATMEL */
1212 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
1213 pDevice->flashinfo.pagesize = 0;
1214 pDevice->flashinfo.buffered = FALSE;
1216 LM_EEPROM_ReadSize( pDevice, &pDevice->flashinfo.chipsize );
1220 LM_FLASH_ReadSize( pDevice, &pDevice->flashinfo.chipsize );
1221 pDevice->Flags |= FLASH_DETECTED_FLAG;
1225 pDevice->NvramSize = pDevice->flashinfo.chipsize;
1227 //printk(KERN_ALERT "*nvram:size=0x%x jnum=0x%x page=0x%x buff=0x%x \n",pDevice->NvramSize,pDevice->flashinfo.jedecnum,pDevice->flashinfo.pagesize,pDevice->flashinfo.buffered);
1229 } /* LM_NVRAM_Init */
1233 /******************************************************************************/
1237 /******************************************************************************/
1239 LM_NvramRead( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset, LM_UINT32 * data )
1244 if( offset >= pDevice->flashinfo.chipsize )
1246 return LM_STATUS_FAILURE;
1249 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1250 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 )
1252 status = LM_EEPROM_Read_UINT32( pDevice, offset, data );
1256 status = LM_NVRAM_AcquireLock( pDevice );
1257 if( status == LM_STATUS_FAILURE )
1262 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1264 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1266 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1267 value32 |= NVRAM_ACCESS_ENABLE;
1268 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1272 status = LM_NVRAM_Read_UINT32(pDevice, offset, data);
1274 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1276 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1278 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1279 value32 &= ~NVRAM_ACCESS_ENABLE;
1280 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1284 LM_NVRAM_ReleaseLock( pDevice );
1288 } /* LM_NvramRead */
1292 #ifdef ETHTOOL_SEEPROM
1294 /******************************************************************************/
1298 /******************************************************************************/
1300 LM_EEPROM_WriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1301 LM_UINT8 * data, LM_UINT32 size )
1312 if( offset > pDevice->flashinfo.chipsize )
1314 return LM_STATUS_FAILURE;
1317 status = LM_STATUS_SUCCESS;
1327 * If our initial offset does not fall on a word boundary, we
1328 * have to do a read / modify / write to preserve the
1329 * preceding bits we are not interested in.
1331 status = LM_EEPROM_Read_UINT32(pDevice, offset & ~0x3, &subword1);
1332 if( status == LM_STATUS_FAILURE )
1338 if( (offset + size) & 0x3 )
1341 * Likewise, if our ending offset does not fall on a word
1342 * boundary, we have to do a read / modify / write to
1343 * preserve the trailing bits we are not interested in.
1345 status = LM_EEPROM_Read_UINT32( pDevice, (offset + size) & ~0x3,
1347 if( status == LM_STATUS_FAILURE )
1353 /* Enable EEPROM write. */
1354 if( pDevice->Flags & EEPROM_WP_FLAG )
1356 REG_WR( pDevice, Grc.LocalCtrl,
1357 pDevice->GrcLocalCtrl | GRC_MISC_LOCAL_CTRL_GPIO_OE1 );
1358 REG_RD_BACK( pDevice, Grc.LocalCtrl );
1361 value32 = REG_RD( pDevice, Grc.LocalCtrl );
1362 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1364 return LM_STATUS_FAILURE;
1370 value32 = offset & 0x3;
1374 * We have to read / modify / write the data to
1375 * preserve the flash contents preceding the offset.
1379 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1380 bytecnt = sizeof(LM_UINT32) - value32;
1383 else if( size < sizeof(LM_UINT32) )
1385 dstptr = (LM_UINT8 *)(&value32);
1391 dstptr = (LM_UINT8 *)(&value32);
1392 bytecnt = sizeof(LM_UINT32);
1395 if( size < bytecnt )
1400 memcpy( dstptr, (void *)data, bytecnt );
1406 * Swap the data so that the byte stream will be
1407 * written the same in little and big endian systems.
1409 value32 = MM_SWAP_LE32(value32);
1411 /* Set the write value to the eeprom */
1412 REG_WR( pDevice, Grc.EepromData, value32 );
1414 Dev = offset / pDevice->flashinfo.chipsize;
1415 Addr = offset % pDevice->flashinfo.chipsize;
1417 value32 = REG_RD( pDevice, Grc.EepromAddr );
1418 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
1419 SEEPROM_ADDR_RW_MASK);
1420 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
1421 SEEPROM_ADDR_START | SEEPROM_ADDR_WRITE;
1423 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
1424 if( status != LM_STATUS_SUCCESS )
1429 offset += sizeof(LM_UINT32);
1432 /* Write-protect EEPROM. */
1433 if( pDevice->Flags & EEPROM_WP_FLAG )
1435 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
1436 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
1437 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
1438 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1443 } /* LM_EEPROM_WriteBlock */
1447 /******************************************************************************/
1451 /******************************************************************************/
1453 LM_NVRAM_WriteBlockUnBuffered( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1454 LM_UINT8 * data, LM_UINT32 size )
1465 /* Cache the pagesize. */
1466 pagesize = pDevice->flashinfo.pagesize;
1468 if( pDevice->flashinfo.jedecnum == JEDEC_SAIFUN )
1470 /* Config2 = 0x500d8 */
1471 /* Config3 = 0x3840253 */
1472 /* Write1 = 0xaf000400 */
1474 /* Configure the erase command to be "page erase". */
1475 /* Configure the status command to be "read status register". */
1476 value32 = REG_RD( pDevice, Nvram.Config2 );
1477 value32 &= ~(NVRAM_STATUS_COMMAND( NVRAM_COMMAND_MASK ) |
1478 NVRAM_ERASE_COMMAND( NVRAM_COMMAND_MASK ));
1479 value32 |= NVRAM_STATUS_COMMAND( SAIFUN_SA25F0XX_READ_STATUS_CMD ) |
1480 NVRAM_ERASE_COMMAND( SAIFUN_SA25F0XX_PAGE_ERASE_CMD );
1481 REG_WR( pDevice, Nvram.Config2, value32 );
1483 /* Configure the write command to be "page write". */
1484 value32 = REG_RD( pDevice, Nvram.Config3 );
1485 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1486 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( SAIFUN_SA25F0XX_PAGE_WRITE_CMD );
1487 REG_WR( pDevice, Nvram.Config3, value32 );
1489 /* Make sure the "write enable" command is correct. */
1490 value32 = REG_RD( pDevice, Nvram.Write1 );
1491 value32 &= ~NVRAM_WRITE1_WRENA_CMD( NVRAM_COMMAND_MASK );
1492 value32 |= NVRAM_WRITE1_WRENA_CMD( SAIFUN_SA25F0XX_WRENA_CMD );
1493 REG_WR( pDevice, Nvram.Write1, value32 );
1495 pagemask = SAIFUN_SA25F0XX_PAGE_MASK;
1499 /* Unsupported flash type */
1500 return LM_STATUS_FAILURE;
1505 status = LM_STATUS_SUCCESS;
1511 /* Align the offset to a page boundary. */
1512 physaddr = offset & ~pagemask;
1514 status = LM_NVRAM_ReadBlock( pDevice, physaddr,
1515 pDevice->flashbuffer,
1517 if( status == LM_STATUS_FAILURE )
1522 /* Calculate the target index. */
1523 tgtoff = offset & pagemask;
1525 /* Copy the new data into the save buffer. */
1526 for( i = tgtoff; i < pagesize && size > 0; i++ )
1528 pDevice->flashbuffer[i] = *data++;
1532 /* Move the offset to the next page. */
1533 offset = offset + (pagesize - tgtoff);
1536 * The LM_NVRAM_ReadBlock() function releases
1537 * the access enable bit. Reacquire it.
1539 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1540 REG_WR(pDevice, Nvram.NvmAccess, NVRAM_ACCESS_ENABLE);
1544 * Before we can erase the flash page, we need
1545 * to issue a special "write enable" command.
1547 ctrlreg = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1549 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1550 if( status == LM_STATUS_FAILURE )
1555 /* Erase the target page */
1556 REG_WR(pDevice, Nvram.Addr, physaddr);
1558 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR |
1559 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
1561 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1562 if( status == LM_STATUS_FAILURE )
1567 /* Issue another write enable to start the write. */
1568 ctrlreg = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1570 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1571 if( status == LM_STATUS_FAILURE )
1576 /* Copy the data into our NIC's buffers. */
1577 for( i = 0; i < pagesize; i+= 4 )
1579 value32 = *((LM_UINT32 *)(&pDevice->flashbuffer[i]));
1580 value32 = MM_SWAP_BE32( value32 );
1582 /* Write the location we wish to write to. */
1583 REG_WR( pDevice, Nvram.Addr, physaddr );
1585 /* Write the data we wish to write. */
1586 REG_WR( pDevice, Nvram.WriteData, value32 );
1588 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR;
1592 ctrlreg |= NVRAM_CMD_FIRST;
1594 else if( i == (pagesize - 4) )
1596 ctrlreg |= NVRAM_CMD_LAST;
1599 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1600 if( status == LM_STATUS_FAILURE )
1606 physaddr += sizeof(LM_UINT32);
1610 /* Paranoia. Turn off the "write enable" flag. */
1611 ctrlreg = NVRAM_CMD_WRITE_DISABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1613 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1618 } /* LM_NVRAM_WriteBlockUnBuffered */
1622 /******************************************************************************/
1626 /******************************************************************************/
1628 LM_NVRAM_WriteBlockBuffered( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1629 LM_UINT8 * data, LM_UINT32 size )
1641 if(T3_ASIC_5752(pDevice->ChipRevId) &&
1642 (pDevice->flashinfo.jedecnum == JEDEC_ST ||
1643 pDevice->flashinfo.jedecnum == JEDEC_ATMEL ))
1645 /* Do nothing as the 5752 does will take care of it */
1647 else if( pDevice->flashinfo.jedecnum == JEDEC_ST )
1650 * Program our chip to look at bit0 of the NVRAM's status
1651 * register when polling the write or erase operation status.
1653 value32 = REG_RD(pDevice, Nvram.Config1);
1654 value32 &= ~FLASH_STATUS_BITS_MASK;
1655 REG_WR( pDevice, Nvram.Config1, value32 );
1657 /* Program the "read status" and "page erase" commands. */
1658 value32 = NVRAM_STATUS_COMMAND( ST_M45PEX0_READ_STATUS_CMD ) |
1659 NVRAM_ERASE_COMMAND( ST_M45PEX0_PAGE_ERASE_CMD );
1660 REG_WR( pDevice, Nvram.Config2, value32 );
1662 /* Set the write command to be "page program". */
1663 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1664 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1665 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ST_M45PEX0_PAGE_PRGM_CMD );
1666 REG_WR( pDevice, Nvram.Config3, value32 );
1668 /* Set the "write enable" and "write disable" commands. */
1669 value32 = NVRAM_WRITE1_WRENA_CMD( ST_M45PEX0_WRENA_CMD ) |
1670 NVRAM_WRITE1_WRDIS_CMD( ST_M45PEX0_WRDIS_CMD );
1671 REG_WR( pDevice, Nvram.Write1, value32 );
1673 else if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL )
1675 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1680 Config3 = 0xa184a053
1684 else if( pDevice->flashinfo.buffered == TRUE )
1687 * Program our chip to look at bit7 of the NVRAM's status
1688 * register when polling the write operation status.
1690 value32 = REG_RD(pDevice, Nvram.Config1);
1691 value32 |= FLASH_STATUS_BITS_MASK;
1692 REG_WR( pDevice, Nvram.Config1, value32 );
1694 /* Set the write command to be "page program". */
1695 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1696 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1697 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ATMEL_AT45DB0X1B_BUFFER_WRITE_CMD );
1698 REG_WR( pDevice, Nvram.Config3, value32 );
1699 /* Config1 = 0x2008273 */
1700 /* Config2 = 0x00570081 */
1701 /* Config3 = 0x68848353 */
1705 /* NVRAM type unsupported. */
1706 return LM_STATUS_FAILURE;
1711 /* NVRAM type unsupported. */
1712 return LM_STATUS_FAILURE;
1715 status = LM_STATUS_SUCCESS;
1720 * If our initial offset does not fall on a word boundary, we
1721 * have to do a read / modify / write to preserve the
1722 * preceding bits we are not interested in.
1724 status = LM_NVRAM_ReadBlock( pDevice, offset & ~0x3,
1725 (LM_UINT8 *)&subword1,
1727 if( status == LM_STATUS_FAILURE )
1733 if( (offset + size) & 0x3 )
1736 * Likewise, if our ending offset does not fall on a word
1737 * boundary, we have to do a read / modify / write to
1738 * preserve the trailing bits we are not interested in.
1740 status = LM_NVRAM_ReadBlock( pDevice, (offset + size) & ~0x3,
1741 (LM_UINT8 *)&subword2,
1743 if( status == LM_STATUS_FAILURE )
1749 ctrlreg = NVRAM_CMD_FIRST;
1753 value32 = offset & 0x3;
1757 * We have to read / modify / write the data to
1758 * preserve the flash contents preceding the offset.
1762 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1763 bytecnt = sizeof(LM_UINT32) - value32;
1766 else if( size < sizeof(LM_UINT32) )
1768 dstptr = (LM_UINT8 *)(&value32);
1774 dstptr = (LM_UINT8 *)(&value32);
1775 bytecnt = sizeof(LM_UINT32);
1778 if( size < bytecnt )
1783 memcpy( dstptr, (void *)data, bytecnt );
1789 * Swap the data so that the byte stream will be
1790 * written the same in little and big endian systems.
1792 value32 = MM_SWAP_BE32(value32);
1794 /* Set the desired write data value to the flash. */
1795 REG_WR(pDevice, Nvram.WriteData, value32);
1797 pageoff = offset % pDevice->flashinfo.pagesize;
1799 /* Set the target address. */
1800 if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
1801 pDevice->flashinfo.romtype == ROM_TYPE_FLASH )
1804 * If we're dealing with the special ATMEL part, we need to
1805 * convert the submitted offset before it can be considered
1806 * a physical address.
1810 pagenmbr = offset / pDevice->flashinfo.pagesize;
1811 pagenmbr = pagenmbr << ATMEL_AT45DB0X1B_PAGE_POS;
1813 physaddr = pagenmbr + pageoff;
1820 REG_WR(pDevice, Nvram.Addr, physaddr);
1822 ctrlreg |= (NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR);
1826 /* Set CMD_FIRST when we are at the beginning of a page. */
1827 ctrlreg |= NVRAM_CMD_FIRST;
1829 else if( pageoff == (pDevice->flashinfo.pagesize - 4) )
1832 * Enable the write to the current page
1833 * before moving on to the next one.
1835 ctrlreg |= NVRAM_CMD_LAST;
1840 ctrlreg |= NVRAM_CMD_LAST;
1843 if( pDevice->flashinfo.jedecnum == JEDEC_ST &&
1844 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) ||
1845 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5714)) &&
1846 (ctrlreg & NVRAM_CMD_FIRST) )
1850 REG_WR(pDevice, Nvram.Write1, ST_M45PEX0_WRENA_CMD);
1852 /* We need to issue a special "write enable" command first. */
1853 wrencmd = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1855 status = LM_NVRAM_ExecuteCommand( pDevice, wrencmd );
1856 if( status == LM_STATUS_FAILURE )
1862 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1864 /* We always do complete word writes to eeprom. */
1865 ctrlreg |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
1868 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1869 if( status == LM_STATUS_FAILURE )
1874 offset += sizeof(LM_UINT32);
1879 } /* LM_NVRAM_WriteBlockBuffered */
1883 /******************************************************************************/
1887 /******************************************************************************/
1888 LM_STATUS LM_NVRAM_WriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1889 LM_UINT8 * data, LM_UINT32 size )
1894 if( offset > pDevice->flashinfo.chipsize ||
1895 (offset + size) > pDevice->flashinfo.chipsize )
1897 return LM_STATUS_FAILURE;
1902 return LM_STATUS_SUCCESS;
1905 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1906 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 )
1908 status = LM_EEPROM_WriteBlock( pDevice, offset, data, size );
1912 status = LM_NVRAM_AcquireLock( pDevice );
1913 if( status == LM_STATUS_FAILURE )
1918 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1920 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1922 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1923 value32 |= (NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
1924 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1928 /* Enable EEPROM write. */
1929 if( pDevice->Flags & EEPROM_WP_FLAG )
1931 REG_WR(pDevice, Grc.LocalCtrl,
1932 pDevice->GrcLocalCtrl | GRC_MISC_LOCAL_CTRL_GPIO_OE1);
1933 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1936 value32 = REG_RD(pDevice, Grc.LocalCtrl);
1937 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1939 status = LM_STATUS_FAILURE;
1944 value32 = REG_RD(pDevice, Grc.Mode);
1945 value32 |= GRC_MODE_NVRAM_WRITE_ENABLE;
1946 REG_WR(pDevice, Grc.Mode, value32);
1948 if( pDevice->flashinfo.buffered == TRUE ||
1949 pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1951 status = LM_NVRAM_WriteBlockBuffered(pDevice, offset, data, size);
1955 status = LM_NVRAM_WriteBlockUnBuffered(pDevice, offset, data, size);
1958 value32 = REG_RD(pDevice, Grc.Mode);
1959 value32 &= ~GRC_MODE_NVRAM_WRITE_ENABLE;
1960 REG_WR(pDevice, Grc.Mode, value32);
1962 if( pDevice->Flags & EEPROM_WP_FLAG )
1964 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
1965 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
1966 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
1967 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1973 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1975 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1977 value32 = REG_RD(pDevice, Nvram.NvmAccess);
1978 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
1979 REG_WR(pDevice, Nvram.NvmAccess, value32);
1983 LM_NVRAM_ReleaseLock( pDevice );
1987 } /* LM_NVRAM_WriteBlock */
1990 LM_STATUS LM_NvramWriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1991 LM_UINT32 * data, LM_UINT32 size )
1993 return LM_NVRAM_WriteBlock( pDevice, offset, (LM_UINT8 *)data, size * 4 );
1996 #endif /* ETHTOOL_SEEPROM */
2000 LM_ReadVPD(PLM_DEVICE_BLOCK pDevice)
2003 LM_UINT32 Vpd_arr[256/4];
2004 LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0];
2005 LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
2009 /* Read PN from VPD */
2010 for (j = 0; j < 256; j += 4, Vpd_dptr++ )
2012 if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) {
2013 printf("VPD read failed\n");
2016 *Vpd_dptr = Value32;
2018 for (j = 0; j < 256; )
2020 unsigned int Vpd_r_len;
2021 unsigned int Vpd_r_end;
2023 if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91))
2025 j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
2027 else if (Vpd[j] == 0x90)
2029 Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
2031 Vpd_r_end = Vpd_r_len + j;
2032 while (j < Vpd_r_end)
2034 if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N'))
2036 unsigned int len = Vpd[j + 2];
2040 memcpy(pDevice->PartNo, &Vpd[j + 3], len);
2046 if (Vpd[j + 2] == 0)
2063 LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice)
2066 LM_UINT32 Value32, offset, ver_offset, start_addr;
2069 if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
2071 Value32 = MM_SWAP_BE32(Value32);
2072 if (Value32 != 0x669955aa)
2074 if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
2077 offset = MM_SWAP_BE32(offset);
2079 if( (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2080 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) &&
2081 pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
2082 pDevice->flashinfo.buffered == TRUE )
2086 highaddr = offset >> ATMEL_AT45DB0X1B_PAGE_POS;
2087 highaddr = highaddr * ATMEL_AT45DB0X1B_PAGE_SIZE;
2089 offset = highaddr + (offset & ATMEL_AT45DB0X1B_PAGE_MASK);
2091 if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
2094 Value32 = MM_SWAP_BE32(Value32);
2095 Value32 &= 0xfc000000;
2096 if ((Value32 == 0x0c000000) &&
2097 (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) &&
2100 if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
2102 if (LM_NvramRead(pDevice, 4, &start_addr) != LM_STATUS_SUCCESS)
2104 ver_offset = MM_SWAP_BE32(ver_offset);
2105 start_addr = MM_SWAP_BE32(start_addr);
2106 offset += ver_offset - start_addr;
2107 for (i = 0; i < 16; i += 4) {
2108 if (LM_NvramRead(pDevice, offset + i, &Value32) !=
2113 memcpy(&(pDevice->BootCodeVer[i]), &Value32, sizeof(Value32));
2119 if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
2122 Value32 = MM_SWAP_BE32(Value32);
2124 c = ((Value32 & 0xff00) >> 8);
2127 pDevice->BootCodeVer[i++] = c + '0';
2130 pDevice->BootCodeVer[i++] = (c / 10) + '0';
2131 pDevice->BootCodeVer[i++] = (c % 10) + '0';
2133 pDevice->BootCodeVer[i++] = '.';
2136 pDevice->BootCodeVer[i++] = '0';
2137 pDevice->BootCodeVer[i++] = c + '0';
2140 pDevice->BootCodeVer[i++] = (c / 10) + '0';
2141 pDevice->BootCodeVer[i++] = (c % 10) + '0';
2143 pDevice->BootCodeVer[i] = 0;
2149 LM_ReadIPMICodeVersion(PLM_DEVICE_BLOCK pDevice)
2152 static char * present = "BRCM ASF present";
2153 LM_UINT32 sig1, sig2;
2154 LM_UINT32 value32, offset, asf_offset, ver_offset, start_addr;
2157 if (LM_NvramRead(pDevice, 0x0, &value32) != LM_STATUS_SUCCESS)
2159 value32 = MM_SWAP_BE32(value32);
2160 if (value32 != 0x669955aa)
2164 for (i = 0; i < 8; i++) {
2165 if (LM_NvramRead(pDevice, offset, &value32) != LM_STATUS_SUCCESS)
2167 value32 = MM_SWAP_BE32(value32) & 0xff000000;
2168 if (value32 == 0x1000000)
2176 if (LM_NvramRead(pDevice, 0x14 + i * 12, &start_addr) != LM_STATUS_SUCCESS)
2179 start_addr = MM_SWAP_BE32(start_addr);
2181 if (start_addr == 0xc0034000)
2182 start_addr = 0x08000000;
2184 if (LM_NvramRead(pDevice, 0x14 + i * 12 + 8, &asf_offset) != LM_STATUS_SUCCESS)
2187 asf_offset = MM_SWAP_BE32(asf_offset);
2189 if (LM_NvramRead(pDevice, asf_offset, &sig1) != LM_STATUS_SUCCESS ||
2190 LM_NvramRead(pDevice, asf_offset + 4, &sig2) != LM_STATUS_SUCCESS )
2193 sig1 = MM_SWAP_BE32(sig1);
2195 if ((sig1 & 0xfc000000) != 0x0c000000 || sig2 != 0 ) {
2196 memcpy(pDevice->IPMICodeVer, present, 17);
2200 if (LM_NvramRead(pDevice, asf_offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
2203 ver_offset = MM_SWAP_BE32(ver_offset);
2205 ver_offset -= start_addr;
2206 ver_offset += asf_offset;
2208 for (i = 0; i < 16; i += 4) {
2209 if (LM_NvramRead(pDevice, ver_offset + i, &value32) != LM_STATUS_SUCCESS)
2211 memcpy(&(pDevice->IPMICodeVer[i]), &value32, sizeof(value32));
2217 LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
2220 LM_UINT32 PciState = pDevice->PciState;
2221 LM_UINT32 ClockCtrl;
2222 char *SpeedStr = "";
2224 if (pDevice->Flags & PCI_EXPRESS_FLAG)
2226 strcpy(pDevice->BusSpeedStr, "PCI Express");
2229 if (PciState & T3_PCI_STATE_32BIT_PCI_BUS)
2231 strcpy(pDevice->BusSpeedStr, "32-bit ");
2235 strcpy(pDevice->BusSpeedStr, "64-bit ");
2237 if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)
2239 strcat(pDevice->BusSpeedStr, "PCI ");
2240 if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED)
2251 strcat(pDevice->BusSpeedStr, "PCIX ");
2253 // Theses devices have internal PCI-X buses. The driver
2254 // is unable to use the ClockCtrl register to determine the
2255 // bus speed, so we just hardcode the bus speed to 133MHz.
2257 if ( ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) &&
2258 (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) ||
2259 (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)))
2261 SpeedStr = "133MHz";
2265 ClockCtrl = pDevice->ClockCtrl & 0x1f;
2281 SpeedStr = "100MHz";
2285 SpeedStr = "133MHz";
2290 strcat(pDevice->BusSpeedStr, SpeedStr);
2294 /******************************************************************************/
2296 /* This routine initializes default parameters and reads the PCI */
2297 /* configurations. */
2300 /* LM_STATUS_SUCCESS */
2301 /******************************************************************************/
2304 PLM_DEVICE_BLOCK pDevice)
2306 PLM_ADAPTER_INFO pAdapterInfo;
2307 LM_UINT32 Value32, LedCfg, Ver;
2309 LM_UINT32 EeSigFound;
2310 LM_UINT32 EePhyTypeSerdes = 0;
2311 LM_UINT32 EePhyId = 0;
2313 /* Get Device Id and Vendor Id */
2314 Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32);
2315 if(Status != LM_STATUS_SUCCESS)
2319 pDevice->PciVendorId = (LM_UINT16) Value32;
2320 pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
2322 Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32);
2323 if(Status != LM_STATUS_SUCCESS)
2327 pDevice->PciRevId = (LM_UINT8) Value32;
2329 /* Get chip revision id. */
2330 Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
2331 pDevice->ChipRevId = Value32 >> 16;
2333 /* determine if it is PCIE system */
2334 if( (Value32 = MM_FindCapability(pDevice, T3_PCIE_CAPABILITY_ID)) != 0)
2336 pDevice->Flags |= PCI_EXPRESS_FLAG;
2339 /* Get subsystem vendor. */
2340 Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
2341 if(Status != LM_STATUS_SUCCESS)
2345 pDevice->SubsystemVendorId = (LM_UINT16) Value32;
2347 /* Get PCI subsystem id. */
2348 pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
2350 /* Read bond id for baxter A0 since it has same rev id as hamilton A0*/
2352 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5714_A0) {
2353 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, Value32 | MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS);
2355 Value32 = LM_RegRdInd(pDevice, 0x6804);
2356 Value32 &= GRC_MISC_BD_ID_MASK;
2358 if((Value32 == 0)||(Value32 == 0x8000)) {
2359 pDevice->ChipRevId = T3_CHIP_ID_5752_A0;
2361 pDevice->ChipRevId = T3_CHIP_ID_5714_A0;
2364 Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
2365 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, Value32 & ~ MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS);
2369 /* Get the cache line size. */
2370 MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
2371 pDevice->CacheLineSize = (LM_UINT8) Value32;
2372 pDevice->SavedCacheLineReg = Value32;
2374 if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
2375 pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
2376 pDevice->ChipRevId != T3_CHIP_ID_5704_A0)
2378 pDevice->Flags &= ~UNDI_FIX_FLAG;
2380 #ifndef PCIX_TARGET_WORKAROUND
2381 pDevice->Flags &= ~UNDI_FIX_FLAG;
2383 /* Map the memory base to system address space. */
2384 if (!(pDevice->Flags & UNDI_FIX_FLAG))
2386 Status = MM_MapMemBase(pDevice);
2387 if(Status != LM_STATUS_SUCCESS)
2391 /* Initialize the memory view pointer. */
2392 pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
2395 if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) ||
2396 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX))
2398 pDevice->Flags |= TX_4G_WORKAROUND_FLAG;
2400 if ( (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
2401 (pDevice->Flags == PCI_EXPRESS_FLAG))
2403 pDevice->Flags |= REG_RD_BACK_FLAG;
2406 if(pDevice->ChipRevId==T3_CHIP_ID_5750_A0)
2407 return LM_STATUS_UNKNOWN_ADAPTER;
2409 #ifdef PCIX_TARGET_WORKAROUND
2410 MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
2411 if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)
2413 /* Enable PCI-X workaround only if we are running on 5700 BX. */
2414 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
2416 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2419 if (pDevice->Flags & UNDI_FIX_FLAG)
2421 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2424 /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
2425 /* management register may be clobbered which may cause the */
2426 /* BCM5700 to go into D3 state. While in this state, we will */
2427 /* not have memory mapped register access. As a workaround, we */
2428 /* need to restore the device to D0 state. */
2429 MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
2430 Value32 |= T3_PM_PME_ASSERTED;
2431 Value32 &= ~T3_PM_POWER_STATE_MASK;
2432 Value32 |= T3_PM_POWER_STATE_D0;
2433 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
2435 /* read the current PCI command word */
2436 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
2438 /* Make sure bus-mastering is enabled. */
2439 Value32 |= PCI_BUSMASTER_ENABLE;
2441 #ifdef PCIX_TARGET_WORKAROUND
2442 /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
2444 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG) {
2445 Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
2446 PCI_PARITY_ERROR_ENABLE);
2448 if (pDevice->Flags & UNDI_FIX_FLAG)
2450 Value32 &= ~PCI_MEM_SPACE_ENABLE;
2455 if (pDevice->Flags & ENABLE_MWI_FLAG)
2457 Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
2460 Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
2463 /* save the value we are going to write into the PCI command word */
2464 pDevice->PciCommandStatusWords = Value32;
2466 Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
2467 if(Status != LM_STATUS_SUCCESS)
2472 /* Setup the mode registers. */
2473 pDevice->MiscHostCtrl =
2474 MISC_HOST_CTRL_MASK_PCI_INT |
2475 MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
2476 #ifdef BIG_ENDIAN_HOST
2477 MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
2478 #endif /* BIG_ENDIAN_HOST */
2479 MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
2480 MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
2481 /* write to PCI misc host ctr first in order to enable indirect accesses */
2482 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
2484 /* Set power state to D0. */
2485 LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
2487 /* Preserve HOST_STACK_UP bit in case ASF firmware is running */
2488 Value32 = REG_RD(pDevice, Grc.Mode) & GRC_MODE_HOST_STACK_UP;
2489 #ifdef BIG_ENDIAN_HOST
2490 Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
2491 GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
2493 Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
2495 REG_WR(pDevice, Grc.Mode, Value32);
2497 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
2499 REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
2500 GRC_MISC_LOCAL_CTRL_GPIO_OE1);
2501 REG_RD_BACK(pDevice, Grc.LocalCtrl);
2505 /* Enable memory arbiter*/
2506 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
2508 Value32 = REG_RD(pDevice,MemArbiter.Mode);
2509 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE | Value32);
2513 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
2517 LM_SwitchClocks(pDevice);
2519 REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
2521 /* Check to see if PXE ran and did not shutdown properly */
2522 if ((REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE) ||
2523 !(REG_RD(pDevice, PciCfg.MiscHostCtrl) & MISC_HOST_CTRL_MASK_PCI_INT))
2525 LM_DisableInterrupt(pDevice);
2526 /* assume ASF is enabled */
2527 pDevice->AsfFlags = ASF_ENABLED;
2528 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2530 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
2532 LM_ShutdownChip(pDevice, LM_SHUTDOWN_RESET);
2533 pDevice->AsfFlags = 0;
2535 #ifdef PCIX_TARGET_WORKAROUND
2536 MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
2537 if (!(pDevice->Flags & ENABLE_PCIX_FIX_FLAG) &&
2538 ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
2540 if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
2541 pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
2542 pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
2543 pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
2545 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]), 0);
2546 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]), 0);
2547 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]),
2549 if (MM_MEMREADL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
2551 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2557 LM_NVRAM_Init(pDevice);
2559 Status = LM_STATUS_FAILURE;
2560 /* Get the node address. First try to get in from the shared memory. */
2561 /* If the signature is not present, then get it from the NVRAM. */
2562 Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
2563 if((Value32 >> 16) == 0x484b)
2567 pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
2568 pDevice->NodeAddress[1] = (LM_UINT8) Value32;
2570 Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX);
2572 pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
2573 pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
2574 pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
2575 pDevice->NodeAddress[5] = (LM_UINT8) Value32;
2577 /* Check for null MAC address which can happen with older boot code */
2578 for (i = 0; i < 6; i++)
2580 if (pDevice->NodeAddress[i] != 0)
2582 Status = LM_STATUS_SUCCESS;
2588 if (Status != LM_STATUS_SUCCESS)
2593 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
2594 (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)) )
2596 if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID)
2600 /* workaround - need to reset nvram if */
2601 /* the boot code is not running */
2602 if (LM_NVRAM_AcquireLock(pDevice) != LM_STATUS_SUCCESS)
2604 REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET);
2608 LM_NVRAM_ReleaseLock(pDevice);
2612 Status = LM_NvramRead(pDevice, MacOffset, &Value32);
2613 if(Status == LM_STATUS_SUCCESS)
2615 LM_UINT8 *c = (LM_UINT8 *) &Value32;
2617 pDevice->NodeAddress[0] = c[2];
2618 pDevice->NodeAddress[1] = c[3];
2620 Status = LM_NvramRead(pDevice, MacOffset + 4, &Value32);
2622 c = (LM_UINT8 *) &Value32;
2623 pDevice->NodeAddress[2] = c[0];
2624 pDevice->NodeAddress[3] = c[1];
2625 pDevice->NodeAddress[4] = c[2];
2626 pDevice->NodeAddress[5] = c[3];
2630 if(Status != LM_STATUS_SUCCESS)
2632 Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].High);
2633 pDevice->NodeAddress[0] = (Value32 >> 8) & 0xff;
2634 pDevice->NodeAddress[1] = Value32 & 0xff;
2635 Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].Low);
2636 pDevice->NodeAddress[2] = (Value32 >> 24) & 0xff;
2637 pDevice->NodeAddress[3] = (Value32 >> 16) & 0xff;
2638 pDevice->NodeAddress[4] = (Value32 >> 8) & 0xff;
2639 pDevice->NodeAddress[5] = Value32 & 0xff;
2640 printf("WARNING: Cannot get MAC addr from NVRAM, using %2.2x%2.2x%2.2x%2.2x%2.2x%2.2x\n",
2641 pDevice->NodeAddress[0], pDevice->NodeAddress[1],
2642 pDevice->NodeAddress[2], pDevice->NodeAddress[3],
2643 pDevice->NodeAddress[4], pDevice->NodeAddress[5]);
2646 memcpy(pDevice->PermanentNodeAddress, pDevice->NodeAddress, 6);
2648 /* Initialize the default values. */
2649 pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
2650 pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
2651 pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
2652 pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
2653 pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
2654 pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
2655 pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
2656 pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
2657 pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
2658 pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
2659 pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
2660 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
2661 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
2662 pDevice->DisableAutoNeg = FALSE;
2663 pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
2664 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
2666 pDevice->PhyFlags = 0;
2668 if (!(pDevice->Flags & PCI_EXPRESS_FLAG))
2669 pDevice->Flags |= DELAY_PCI_GRANT_FLAG;
2671 pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO;
2672 pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
2673 pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
2674 pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
2675 #ifdef INCLUDE_TBI_SUPPORT
2676 pDevice->TbiFlags = 0;
2677 pDevice->IgnoreTbiLinkChange = FALSE;
2679 #ifdef INCLUDE_TCP_SEG_SUPPORT
2680 pDevice->LargeSendMaxSize = T3_TCP_SEG_MAX_OFFLOAD_SIZE;
2681 pDevice->LargeSendMinNumSeg = T3_TCP_SEG_MIN_NUM_SEG;
2684 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
2685 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) ||
2686 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705))
2688 pDevice->PhyFlags |= PHY_RESET_ON_LINKDOWN;
2689 pDevice->PhyFlags |= PHY_CHECK_TAPS_AFTER_RESET;
2691 if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5703_AX) ||
2692 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX))
2694 pDevice->PhyFlags |= PHY_ADC_FIX;
2696 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
2698 pDevice->PhyFlags |= PHY_5704_A0_FIX;
2700 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
2702 pDevice->PhyFlags |= PHY_5705_5750_FIX;
2704 /* Ethernet@Wirespeed is supported on 5701,5702,5703,5704,5705a0,5705a1 */
2705 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2706 !((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
2707 (pDevice->ChipRevId != T3_CHIP_ID_5705_A0) &&
2708 (pDevice->ChipRevId != T3_CHIP_ID_5705_A1)))
2710 pDevice->PhyFlags |= PHY_ETHERNET_WIRESPEED;
2713 switch (T3_ASIC_REV(pDevice->ChipRevId))
2715 case T3_ASIC_REV_5704:
2716 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
2717 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
2720 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
2721 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
2725 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
2726 pDevice->QueueRxPackets = TRUE;
2728 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2730 if(T3_ASIC_IS_JUMBO_CAPABLE(pDevice->ChipRevId)){
2731 if( ! T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
2732 pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
2733 pDevice->Flags |= JUMBO_CAPABLE_FLAG;
2736 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2738 pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
2740 if(((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) &&
2741 ((pDevice->BondId == 0x10000) || (pDevice->BondId == 0x18000))) ||
2742 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) &&
2743 ((pDevice->BondId == 0x14000) || (pDevice->BondId == 0x1c000))))
2745 return LM_STATUS_UNKNOWN_ADAPTER;
2747 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
2749 if ((pDevice->BondId == 0x8000) || (pDevice->BondId == 0x4000))
2751 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2754 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
2756 if ((pDevice->BondId == GRC_MISC_BD_ID_5788) ||
2757 (pDevice->BondId == GRC_MISC_BD_ID_5788M))
2759 pDevice->Flags |= BCM5788_FLAG;
2762 if ((pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901)) ||
2763 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901A2)) ||
2764 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5705F)))
2766 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2770 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750)
2772 if ( (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5751F))||
2773 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5753F)))
2775 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2779 /* CIOBE multisplit has a bug */
2781 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) &&
2782 (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE))
2784 pDevice->Flags |= MULTI_SPLIT_ENABLE_FLAG;
2785 pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
2789 /* Get Eeprom info. */
2790 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
2791 if (Value32 == T3_NIC_DATA_SIG)
2794 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
2796 /* For now the 5753 cannot drive gpio2 or ASF will blow */
2797 if(Value32 & T3_NIC_GPIO2_NOT_AVAILABLE)
2799 pDevice->Flags |= GPIO2_DONOT_OUTPUT;
2802 if (Value32 & T3_NIC_MINI_PCI)
2804 pDevice->Flags |= MINI_PCI_FLAG;
2806 /* Determine PHY type. */
2807 switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK)
2809 case T3_NIC_CFG_PHY_TYPE_COPPER:
2810 EePhyTypeSerdes = FALSE;
2813 case T3_NIC_CFG_PHY_TYPE_FIBER:
2814 EePhyTypeSerdes = TRUE;
2818 EePhyTypeSerdes = FALSE;
2822 if ( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2824 LedCfg = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2);
2825 LedCfg = LedCfg & (T3_NIC_CFG_LED_MODE_MASK |
2826 T3_SHASTA_EXT_LED_MODE_MASK);
2830 /* Determine PHY led mode. for legacy devices */
2831 LedCfg = Value32 & T3_NIC_CFG_LED_MODE_MASK;
2837 case T3_NIC_CFG_LED_PHY_MODE_1:
2838 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
2841 case T3_NIC_CFG_LED_PHY_MODE_2:
2842 pDevice->LedCtrl = LED_CTRL_PHY_MODE_2;
2845 case T3_NIC_CFG_LED_MAC_MODE:
2846 pDevice->LedCtrl = LED_CTRL_MAC_MODE;
2849 case T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE:
2850 pDevice->LedCtrl = LED_CTRL_SHARED_TRAFFIC_LINK;
2851 if ((pDevice->ChipRevId != T3_CHIP_ID_5750_A0) &&
2852 (pDevice->ChipRevId != T3_CHIP_ID_5750_A1))
2854 pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 |
2855 LED_CTRL_PHY_MODE_2;
2859 case T3_SHASTA_EXT_LED_MAC_MODE:
2860 pDevice->LedCtrl = LED_CTRL_SHASTA_MAC_MODE;
2863 case T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE:
2864 pDevice->LedCtrl = LED_CTRL_WIRELESS_COMBO;
2865 if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)
2867 pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 |
2868 LED_CTRL_PHY_MODE_2;
2874 if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
2875 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)) &&
2876 (pDevice->SubsystemVendorId == T3_SVID_DELL))
2878 pDevice->LedCtrl = LED_CTRL_PHY_MODE_2;
2881 if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
2882 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) ||
2883 (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId)) )
2885 /* Enable EEPROM write protection. */
2886 if(Value32 & T3_NIC_EEPROM_WP)
2888 pDevice->Flags |= EEPROM_WP_FLAG;
2891 pDevice->AsfFlags = 0;
2893 if (Value32 & T3_NIC_CFG_ENABLE_ASF)
2895 pDevice->AsfFlags |= ASF_ENABLED;
2896 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2898 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
2902 if (Value32 & T3_NIC_FIBER_WOL_CAPABLE)
2904 pDevice->Flags |= FIBER_WOL_CAPABLE_FLAG;
2906 if (Value32 & T3_NIC_WOL_LIMIT_10)
2908 pDevice->Flags |= WOL_LIMIT_10MBPS_FLAG;
2911 /* Get the PHY Id. */
2912 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR);
2915 EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
2916 PHY_ID1_OUI_MASK) << 10;
2918 Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
2920 EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
2921 (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
2926 if (!EePhyTypeSerdes && !(pDevice->AsfFlags & ASF_ENABLED))
2928 /* reset PHY if boot code couldn't read the PHY ID */
2929 LM_ResetPhy(pDevice);
2933 Ver = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_VER);
2934 Ver >>= T3_NIC_DATA_VER_SHIFT;
2937 if((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2938 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) &&
2939 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703) &&
2940 (Ver > 0) && (Ver < 0x100)){
2942 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2);
2944 if (Value32 & T3_NIC_CFG_CAPACITIVE_COUPLING)
2946 pDevice->PhyFlags |= PHY_CAPACITIVE_COUPLING;
2949 if (Value32 & T3_NIC_CFG_PRESERVE_PREEMPHASIS)
2951 pDevice->TbiFlags |= TBI_DO_PREEMPHASIS;
2962 /* Set the PHY address. */
2963 pDevice->PhyAddr = PHY_DEVICE_ID;
2965 /* Disable auto polling. */
2966 pDevice->MiMode = 0xc0000;
2967 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
2968 REG_RD_BACK(pDevice, MacCtrl.MiMode);
2971 if (pDevice->AsfFlags & ASF_ENABLED)
2973 /* Reading PHY registers will contend with ASF */
2978 /* Get the PHY id. */
2979 LM_GetPhyId(pDevice);
2982 /* Set the EnableTbi flag to false if we have a copper PHY. */
2983 switch(pDevice->PhyId & PHY_ID_MASK)
2985 case PHY_BCM5400_PHY_ID:
2986 case PHY_BCM5401_PHY_ID:
2987 case PHY_BCM5411_PHY_ID:
2988 case PHY_BCM5701_PHY_ID:
2989 case PHY_BCM5703_PHY_ID:
2990 case PHY_BCM5704_PHY_ID:
2991 case PHY_BCM5705_PHY_ID:
2992 case PHY_BCM5750_PHY_ID:
2994 case PHY_BCM5714_PHY_ID:
2995 case PHY_BCM5780_PHY_ID:
2996 if(EePhyTypeSerdes == TRUE)
2998 pDevice->PhyFlags |= PHY_IS_FIBER;
3001 case PHY_BCM5752_PHY_ID:
3004 case PHY_BCM8002_PHY_ID:
3005 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3012 pDevice->PhyId = EePhyId;
3014 if (EePhyTypeSerdes && ((pDevice->PhyId == PHY_BCM5714_PHY_ID) || (pDevice->PhyId == PHY_BCM5780_PHY_ID)) )
3016 pDevice->PhyFlags |= PHY_IS_FIBER;
3018 else if (EePhyTypeSerdes)
3020 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3023 else if ((pAdapterInfo = LM_GetAdapterInfoBySsid(
3024 pDevice->SubsystemVendorId,
3025 pDevice->SubsystemId)))
3027 pDevice->PhyId = pAdapterInfo->PhyId;
3028 if (pAdapterInfo->Serdes)
3030 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3035 if (UNKNOWN_PHY_ID(pDevice->PhyId))
3037 LM_ResetPhy(pDevice);
3038 LM_GetPhyId(pDevice);
3044 if(UNKNOWN_PHY_ID(pDevice->PhyId) &&
3045 !(pDevice->TbiFlags & ENABLE_TBI_FLAG))
3047 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3048 printf("PHY ID unknown, assume it is SerDes\n");
3051 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
3053 if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000)
3055 pDevice->SavedCacheLineReg &= 0xffff00ff;
3056 pDevice->SavedCacheLineReg |= 0x4000;
3060 pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
3063 pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
3064 LM_TASK_OFFLOAD_TX_UDP_CHECKSUM | LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
3065 LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
3067 if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0)
3069 pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
3070 LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
3073 #ifdef INCLUDE_TCP_SEG_SUPPORT
3074 pDevice->TaskOffloadCap |= LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3076 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3077 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
3078 (pDevice->ChipRevId == T3_CHIP_ID_5705_A0))
3080 pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3085 if (pDevice->AsfFlags & ASF_ENABLED)
3087 if (!T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
3089 pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3094 /* Change driver parameters. */
3095 Status = MM_GetConfig(pDevice);
3096 if(Status != LM_STATUS_SUCCESS)
3101 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3103 pDevice->Flags &= ~NIC_SEND_BD_FLAG;
3106 /* Save the current phy link status. */
3107 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
3108 !(pDevice->AsfFlags & ASF_ENABLED))
3110 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
3111 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
3113 /* If we don't have link reset the PHY. */
3114 if(!(Value32 & PHY_STATUS_LINK_PASS) ||
3115 (pDevice->PhyFlags & PHY_RESET_ON_INIT))
3118 LM_ResetPhy(pDevice);
3120 if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS)
3122 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
3123 PHY_AN_AD_ALL_SPEEDS;
3124 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
3125 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
3127 if(!(pDevice->PhyFlags & PHY_NO_GIGABIT))
3128 Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS ;
3132 #ifdef INCLUDE_5701_AX_FIX
3133 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
3134 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
3136 Value32 |= BCM540X_CONFIG_AS_MASTER |
3137 BCM540X_ENABLE_CONFIG_AS_MASTER;
3140 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
3142 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
3143 PHY_CTRL_RESTART_AUTO_NEG);
3147 LM_SetEthWireSpeed(pDevice);
3149 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &pDevice->advertising);
3150 LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG,
3151 &pDevice->advertising1000);
3154 /* Currently 5401 phy only */
3155 LM_PhyTapPowerMgmt(pDevice);
3157 #ifdef INCLUDE_TBI_SUPPORT
3158 if(pDevice->TbiFlags & ENABLE_TBI_FLAG)
3160 if (!(pDevice->Flags & FIBER_WOL_CAPABLE_FLAG))
3162 pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
3164 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
3165 if (pDevice->TbiFlags & TBI_PURE_POLLING_FLAG)
3167 pDevice->IgnoreTbiLinkChange = TRUE;
3172 pDevice->TbiFlags = 0;
3175 #endif /* INCLUDE_TBI_SUPPORT */
3177 /* UseTaggedStatus is only valid for 5701 and later. */
3178 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3179 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
3180 ((pDevice->BondId == GRC_MISC_BD_ID_5788) ||
3181 (pDevice->BondId == GRC_MISC_BD_ID_5788M))))
3183 pDevice->Flags &= ~USE_TAGGED_STATUS_FLAG;
3184 pDevice->CoalesceMode = 0;
3188 pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
3189 HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
3192 /* Set the status block size. */
3193 if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
3194 T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX)
3196 pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
3199 /* Check the DURING_INT coalescing ticks parameters. */
3200 if (pDevice->Flags & USE_TAGGED_STATUS_FLAG)
3202 if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3204 pDevice->RxCoalescingTicksDuringInt =
3205 DEFAULT_RX_COALESCING_TICKS_DURING_INT;
3208 if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3210 pDevice->TxCoalescingTicksDuringInt =
3211 DEFAULT_TX_COALESCING_TICKS_DURING_INT;
3214 if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3216 pDevice->RxMaxCoalescedFramesDuringInt =
3217 DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
3220 if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3222 pDevice->TxMaxCoalescedFramesDuringInt =
3223 DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
3228 if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3230 pDevice->RxCoalescingTicksDuringInt = 0;
3233 if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3235 pDevice->TxCoalescingTicksDuringInt = 0;
3238 if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3240 pDevice->RxMaxCoalescedFramesDuringInt = 0;
3243 if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3245 pDevice->TxMaxCoalescedFramesDuringInt = 0;
3249 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3250 if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */))
3252 pDevice->RxJumboDescCnt = 0;
3253 if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC)
3255 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3258 else if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
3260 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3261 pDevice->RxJumboDescCnt = 0;
3265 pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ +
3266 COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK;
3268 if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE)
3270 pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE;
3271 pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */;
3273 pDevice->TxMtu = pDevice->RxMtu;
3276 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3277 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3279 pDevice->RxPacketDescCnt =
3280 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3281 pDevice->RxJumboDescCnt +
3282 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3283 pDevice->RxStdDescCnt;
3285 if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC)
3287 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3290 if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE)
3292 pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
3295 /* Configure the proper ways to get link change interrupt. */
3296 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO)
3298 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3300 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3304 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
3307 else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
3309 /* Auto-polling does not work on 5700_AX and 5700_BX. */
3310 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3312 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3316 /* Determine the method to get link change status. */
3317 if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO)
3319 /* The link status bit in the status block does not work on 5700_AX */
3320 /* and 5700_BX chips. */
3321 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3323 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3327 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
3331 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
3332 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3334 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3339 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
3342 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3343 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
3345 /* bug? 5701 in LINK10 mode does not seem to work when */
3346 /* PhyIntMode is LINK_READY. */
3347 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
3348 #ifdef INCLUDE_TBI_SUPPORT
3349 !(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
3351 pDevice->LedCtrl == LED_CTRL_PHY_MODE_2)
3353 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3354 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3356 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
3358 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
3363 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3364 pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
3365 pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
3366 pDevice->ChipRevId == T3_CHIP_ID_5701_B2)
3368 pDevice->WolSpeed = WOL_SPEED_10MB;
3372 if (pDevice->Flags & WOL_LIMIT_10MBPS_FLAG)
3374 pDevice->WolSpeed = WOL_SPEED_10MB;
3378 pDevice->WolSpeed = WOL_SPEED_100MB;
3383 pDevice->PciState = REG_RD(pDevice, PciCfg.PciState);
3385 pDevice->DmaReadFifoSize = 0;
3386 if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
3387 (pDevice->ChipRevId != T3_CHIP_ID_5705_A0)) ||
3388 T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId) )
3390 #ifdef INCLUDE_TCP_SEG_SUPPORT
3391 if ((pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION) &&
3392 ((pDevice->ChipRevId == T3_CHIP_ID_5705_A1) ||
3393 (pDevice->ChipRevId == T3_CHIP_ID_5705_A2)))
3395 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_SIZE_128;
3400 if (!(pDevice->PciState & T3_PCI_STATE_HIGH_BUS_SPEED) &&
3401 !(pDevice->Flags & BCM5788_FLAG) &&
3402 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3404 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST;
3405 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A1)
3407 pDevice->Flags |= RX_BD_LIMIT_64_FLAG;
3409 pDevice->Flags |= DMA_WR_MODE_RX_ACCELERATE_FLAG;
3411 else if (pDevice->Flags & PCI_EXPRESS_FLAG)
3413 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST;
3418 pDevice->Flags &= ~T3_HAS_TWO_CPUS;
3419 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3420 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
3421 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 ||
3422 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
3424 pDevice->Flags |= T3_HAS_TWO_CPUS;
3427 LM_ReadVPD(pDevice);
3428 LM_ReadBootCodeVersion(pDevice);
3429 LM_ReadIPMICodeVersion(pDevice);
3430 LM_GetBusSpeed(pDevice);
3432 return LM_STATUS_SUCCESS;
3433 } /* LM_GetAdapterInfo */
3435 STATIC PLM_ADAPTER_INFO
3436 LM_GetAdapterInfoBySsid(
3440 static LM_ADAPTER_INFO AdapterArr[] =
3442 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0},
3443 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0},
3444 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1},
3445 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 },
3446 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0},
3447 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0},
3448 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
3449 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0},
3450 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0},
3451 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5703_PHY_ID, 0},
3452 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5703_PHY_ID, 0},
3454 { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 },
3455 { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 },
3456 { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 },
3457 { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 },
3458 { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 },
3460 { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 },
3461 { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 },
3462 { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 },
3463 { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 },
3465 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 },
3466 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 },
3467 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 },
3468 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 },
3469 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 },
3471 { 0x1014, 0x0281, 0, 1 },
3475 for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++)
3477 if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid)
3479 return &AdapterArr[j];
3488 /******************************************************************************/
3490 /* This routine sets up receive/transmit buffer descriptions queues. */
3493 /* LM_STATUS_SUCCESS */
3494 /******************************************************************************/
3496 LM_InitializeAdapter(
3497 PLM_DEVICE_BLOCK pDevice)
3499 LM_PHYSICAL_ADDRESS MemPhy;
3504 LM_UINT32 Value32, j;
3505 LM_UINT32 DmaWrCmd, DmaRdCmd, DmaWrBdry, DmaRdBdry;
3507 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
3509 while (((Value32 & 0x3ff) != (pDevice->PciCommandStatusWords & 0x3ff)) &&
3512 /* On PCIE devices, there are some rare cases where the device */
3513 /* is in the process of link-training at this point */
3515 MM_WriteConfig32(pDevice, PCI_COMMAND_REG, pDevice->PciCommandStatusWords);
3516 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
3519 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
3520 /* Set power state to D0. */
3521 LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
3523 /* Intialize the queues. */
3524 QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container,
3525 MAX_RX_PACKET_DESC_COUNT);
3526 QQ_InitQueue(&pDevice->RxPacketFreeQ.Container,
3527 MAX_RX_PACKET_DESC_COUNT);
3529 QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT);
3530 QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT);
3532 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
3534 pDevice->RcvRetRcbEntryCount = 512;
3535 pDevice->RcvRetRcbEntryCountMask = 511;
3539 pDevice->RcvRetRcbEntryCount = T3_RCV_RETURN_RCB_ENTRY_COUNT;
3540 pDevice->RcvRetRcbEntryCountMask = T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
3543 /* Allocate shared memory for: status block, the buffers for receive */
3544 /* rings -- standard, mini, jumbo, and return rings. */
3545 Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) +
3546 T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
3547 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3548 T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
3549 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3550 (pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD));
3552 /* Memory for host based Send BD. */
3553 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3555 Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
3558 /* Allocate the memory block. */
3559 Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE);
3560 if(Status != LM_STATUS_SUCCESS)
3565 DmaWrCmd = DMA_CTRL_WRITE_CMD;
3566 DmaRdCmd = DMA_CTRL_READ_CMD;
3567 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_DISABLE;
3568 DmaRdBdry = DMA_CTRL_READ_BOUNDARY_DISABLE;
3569 #ifdef BCM_DISCONNECT_AT_CACHELINE
3570 /* This code is intended for PPC64 and other similar architectures */
3571 /* Only the following chips support this */
3572 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3573 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
3574 (pDevice->Flags & PCI_EXPRESS_FLAG))
3576 switch(pDevice->CacheLineSize * 4)
3582 if (!(pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) &&
3583 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3586 /* use 384 which is a multiple of 16,32,64,128 */
3587 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_384_PCIX;
3590 else if (pDevice->Flags & PCI_EXPRESS_FLAG)
3593 /* use 128 which is a multiple of 16,32,64,128 */
3594 DmaWrCmd = DMA_CTRL_WRITE_BOUNDARY_128_PCIE;
3599 /* use 256 which is a multiple of 16,32,64,128,256 */
3600 if ((pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) &&
3601 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3604 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256;
3606 else if (!(pDevice->Flags & PCI_EXPRESS_FLAG))
3609 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256_PCIX;
3615 pDevice->DmaReadWriteCtrl = DmaWrCmd | DmaRdCmd | DmaWrBdry | DmaRdBdry;
3616 /* Program DMA Read/Write */
3617 if (pDevice->Flags & PCI_EXPRESS_FLAG)
3620 /* !=0 is 256 max or greater payload size so set water mark accordingly*/
3621 Value32 = (REG_RD(pDevice, PciCfg.DeviceCtrl) & MAX_PAYLOAD_SIZE_MASK);
3624 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_PCIE_H20MARK_256;
3627 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_PCIE_H20MARK_128;
3631 else if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS)
3633 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3635 pDevice->DmaReadWriteCtrl |= 0x003f0000;
3639 pDevice->DmaReadWriteCtrl |= 0x003f000f;
3644 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
3646 pDevice->DmaReadWriteCtrl |= 0x009f0000;
3649 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
3651 pDevice->DmaReadWriteCtrl |= 0x009C0000;
3654 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
3655 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 )
3657 Value32 = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f;
3658 if ((Value32 == 0x6) || (Value32 == 0x7))
3660 pDevice->Flags |= ONE_DMA_AT_ONCE_FLAG;
3663 else if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
3665 pDevice->DmaReadWriteCtrl &= ~DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
3666 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5780)
3667 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | DMA_CTRL_WRITE_ONE_DMA_AT_ONCE);
3669 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | BIT_15);
3670 /* bit 15 is the current CQ 13140 Fix */
3674 pDevice->DmaReadWriteCtrl |= 0x001b000f;
3677 if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
3678 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
3680 pDevice->DmaReadWriteCtrl &= 0xfffffff0;
3683 if (pDevice->Flags & ONE_DMA_AT_ONCE_FLAG)
3685 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
3688 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
3690 LM_SwitchClocks(pDevice);
3692 if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS)
3694 return LM_STATUS_FAILURE;
3698 pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
3699 pDevice->StatusBlkPhy = MemPhy;
3700 pMemVirt += T3_STATUS_BLOCK_SIZE;
3701 LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE);
3703 /* Statistics block. */
3704 pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
3705 pDevice->StatsBlkPhy = MemPhy;
3706 pMemVirt += sizeof(T3_STATS_BLOCK);
3707 LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK));
3709 /* Receive standard BD buffer. */
3710 pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
3711 pDevice->RxStdBdPhy = MemPhy;
3713 pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
3714 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3715 T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
3717 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3718 /* Receive jumbo BD buffer. */
3719 pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
3720 pDevice->RxJumboBdPhy = MemPhy;
3722 pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
3723 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3724 T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
3725 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3727 /* Receive return BD buffer. */
3728 pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
3729 pDevice->RcvRetBdPhy = MemPhy;
3731 pMemVirt += pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD);
3732 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3733 pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD));
3735 /* Set up Send BD. */
3736 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3738 pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
3739 pDevice->SendBdPhy = MemPhy;
3741 pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
3742 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3743 sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT);
3745 #ifdef BCM_NIC_SEND_BD
3748 pDevice->pSendBdVirt = (PT3_SND_BD)
3749 pDevice->pMemView->uIntMem.First32k.BufferDesc;
3750 pDevice->SendBdPhy.High = 0;
3751 pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
3755 /* Allocate memory for packet descriptors. */
3756 Size = (pDevice->RxPacketDescCnt +
3757 pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
3758 Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket);
3759 if(Status != LM_STATUS_SUCCESS)
3763 pDevice->pPacketDescBase = (PLM_VOID) pPacket;
3765 /* Create transmit packet descriptors from the memory block and add them */
3766 /* to the TxPacketFreeQ for each send ring. */
3767 for(j = 0; j < pDevice->TxPacketDescCnt; j++)
3772 /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
3773 QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
3775 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3776 /* is the total size of the packet descriptor including the */
3777 /* os-specific extensions in the UM_PACKET structure. */
3778 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3781 /* Create receive packet descriptors from the memory block and add them */
3782 /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
3783 for(j = 0; j < pDevice->RxStdDescCnt; j++)
3785 /* Receive producer ring. */
3786 pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
3788 /* Receive buffer size. */
3789 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
3790 (pDevice->RxJumboBufferSize) )
3792 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
3794 pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
3797 /* Add the descriptor to RxPacketFreeQ. */
3798 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
3800 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3801 /* is the total size of the packet descriptor including the */
3802 /* os-specific extensions in the UM_PACKET structure. */
3803 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3807 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3808 /* Create the Jumbo packet descriptors. */
3809 for(j = 0; j < pDevice->RxJumboDescCnt; j++)
3811 /* Receive producer ring. */
3812 pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
3814 /* Receive buffer size. */
3815 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
3817 /* Add the descriptor to RxPacketFreeQ. */
3818 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
3820 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3821 /* is the total size of the packet descriptor including the */
3822 /* os-specific extensions in the UM_PACKET structure. */
3823 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3825 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3827 /* Initialize the rest of the packet descriptors. */
3828 Status = MM_InitializeUmPackets(pDevice);
3829 if(Status != LM_STATUS_SUCCESS)
3834 /* Default receive mask. */
3835 pDevice->ReceiveMask &= LM_KEEP_VLAN_TAG;
3836 pDevice->ReceiveMask |= LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
3839 /* Make sure we are in the first 32k memory window or NicSendBd. */
3840 REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
3842 /* Initialize the hardware. */
3843 Status = LM_ResetAdapter(pDevice);
3844 if(Status != LM_STATUS_SUCCESS)
3849 /* We are done with initialization. */
3850 pDevice->InitDone = TRUE;
3852 return LM_STATUS_SUCCESS;
3853 } /* LM_InitializeAdapter */
3857 LM_DisableChip(PLM_DEVICE_BLOCK pDevice)
3861 pDevice->RxMode &= ~RX_MODE_ENABLE;
3862 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
3863 if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE))
3867 data = REG_RD(pDevice, RcvBdIn.Mode);
3868 data &= ~RCV_BD_IN_MODE_ENABLE;
3869 REG_WR(pDevice, RcvBdIn.Mode,data);
3870 if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE))
3874 data = REG_RD(pDevice, RcvListPlmt.Mode);
3875 data &= ~RCV_LIST_PLMT_MODE_ENABLE;
3876 REG_WR(pDevice, RcvListPlmt.Mode,data);
3877 if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE))
3881 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3883 data = REG_RD(pDevice, RcvListSel.Mode);
3884 data &= ~RCV_LIST_SEL_MODE_ENABLE;
3885 REG_WR(pDevice, RcvListSel.Mode,data);
3886 if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE))
3891 data = REG_RD(pDevice, RcvDataBdIn.Mode);
3892 data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
3893 REG_WR(pDevice, RcvDataBdIn.Mode,data);
3894 if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE))
3898 data = REG_RD(pDevice, RcvDataComp.Mode);
3899 data &= ~RCV_DATA_COMP_MODE_ENABLE;
3900 REG_WR(pDevice, RcvDataComp.Mode,data);
3901 if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE))
3905 data = REG_RD(pDevice, RcvBdComp.Mode);
3906 data &= ~RCV_BD_COMP_MODE_ENABLE;
3907 REG_WR(pDevice, RcvBdComp.Mode,data);
3908 if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE))
3912 data = REG_RD(pDevice, SndBdSel.Mode);
3913 data &= ~SND_BD_SEL_MODE_ENABLE;
3914 REG_WR(pDevice, SndBdSel.Mode, data);
3915 if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE))
3919 data = REG_RD(pDevice, SndBdIn.Mode);
3920 data &= ~SND_BD_IN_MODE_ENABLE;
3921 REG_WR(pDevice, SndBdIn.Mode, data);
3922 if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE))
3926 data = REG_RD(pDevice, SndDataIn.Mode);
3927 data &= ~T3_SND_DATA_IN_MODE_ENABLE;
3928 REG_WR(pDevice, SndDataIn.Mode,data);
3929 if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE))
3933 data = REG_RD(pDevice, DmaRead.Mode);
3934 data &= ~DMA_READ_MODE_ENABLE;
3935 REG_WR(pDevice, DmaRead.Mode, data);
3936 if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE))
3940 data = REG_RD(pDevice, SndDataComp.Mode);
3941 data &= ~SND_DATA_COMP_MODE_ENABLE;
3942 REG_WR(pDevice, SndDataComp.Mode, data);
3943 if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE))
3948 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3950 data = REG_RD(pDevice,DmaComp.Mode);
3951 data &= ~DMA_COMP_MODE_ENABLE;
3952 REG_WR(pDevice, DmaComp.Mode, data);
3953 if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE))
3958 data = REG_RD(pDevice, SndBdComp.Mode);
3959 data &= ~SND_BD_COMP_MODE_ENABLE;
3960 REG_WR(pDevice, SndBdComp.Mode, data);
3961 if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE))
3966 pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
3967 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
3968 pDevice->TxMode &= ~TX_MODE_ENABLE;
3969 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
3970 if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE))
3974 data = REG_RD(pDevice, HostCoalesce.Mode);
3975 data &= ~HOST_COALESCE_ENABLE;
3976 REG_WR(pDevice, HostCoalesce.Mode, data);
3977 if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE))
3981 data = REG_RD(pDevice, DmaWrite.Mode);
3982 data &= ~DMA_WRITE_MODE_ENABLE;
3983 REG_WR(pDevice, DmaWrite.Mode,data);
3984 if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE))
3989 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3991 data = REG_RD(pDevice, MbufClusterFree.Mode);
3992 data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
3993 REG_WR(pDevice, MbufClusterFree.Mode,data);
3994 if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE))
3999 /* Reset all FTQs */
4000 REG_WR(pDevice, Ftq.Reset, 0xffffffff);
4001 REG_WR(pDevice, Ftq.Reset, 0x0);
4003 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4005 data = REG_RD(pDevice, BufMgr.Mode);
4006 data &= ~BUFMGR_MODE_ENABLE;
4007 REG_WR(pDevice, BufMgr.Mode,data);
4008 if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE))
4012 data = REG_RD(pDevice, MemArbiter.Mode);
4013 data &= ~T3_MEM_ARBITER_MODE_ENABLE;
4014 REG_WR(pDevice, MemArbiter.Mode, data);
4015 if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE))
4020 return LM_STATUS_SUCCESS;
4024 LM_DisableFW(PLM_DEVICE_BLOCK pDevice)
4030 if (pDevice->AsfFlags & ASF_ENABLED)
4032 MEM_WR_OFFSET(pDevice, T3_CMD_MAILBOX, T3_CMD_NICDRV_PAUSE_FW);
4033 Value32 = REG_RD(pDevice, Grc.RxCpuEvent);
4034 REG_WR(pDevice, Grc.RxCpuEvent, Value32 | BIT_14);
4035 for (j = 0; j < 100; j++)
4037 Value32 = REG_RD(pDevice, Grc.RxCpuEvent);
4038 if (!(Value32 & BIT_14))
4046 return LM_STATUS_SUCCESS;
4049 /******************************************************************************/
4051 /* This function reinitializes the adapter. */
4054 /* LM_STATUS_SUCCESS */
4055 /******************************************************************************/
4058 PLM_DEVICE_BLOCK pDevice)
4062 int reset_count = 0;
4064 /* Disable interrupt. */
4065 LM_DisableInterrupt(pDevice);
4068 LM_DisableFW(pDevice);
4070 /* May get a spurious interrupt */
4071 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
4073 LM_WritePreResetSignatures(pDevice, LM_INIT_RESET);
4074 /* Disable transmit and receive DMA engines. Abort all pending requests. */
4075 if(pDevice->InitDone)
4080 pDevice->ShuttingDown = FALSE;
4082 LM_ResetChip(pDevice);
4084 LM_WriteLegacySignatures(pDevice, LM_INIT_RESET);
4086 /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
4087 /* in other chip revisions except 5750 */
4088 if ((pDevice->Flags & DELAY_PCI_GRANT_FLAG) &&
4089 !(pDevice->Flags & PCI_EXPRESS_FLAG))
4091 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | BIT_31);
4094 if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
4096 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
4098 Value32 = REG_RD(pDevice, PciCfg.PciState);
4099 Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
4100 REG_WR(pDevice, PciCfg.PciState, Value32);
4103 if (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_BX)
4105 /* New bits defined in register 0x64 to enable some h/w fixes */
4106 /* These new bits are 'write-only' */
4107 Value32 = REG_RD(pDevice, PciCfg.MsiData);
4108 REG_WR(pDevice, PciCfg.MsiData, Value32 | BIT_26 | BIT_28 | BIT_29);
4111 /* Enable TaggedStatus mode. */
4112 if (pDevice->Flags & USE_TAGGED_STATUS_FLAG)
4114 pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
4117 /* Restore PCI configuration registers. */
4118 MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
4119 pDevice->SavedCacheLineReg);
4120 MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
4121 (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
4123 /* Initialize the statistis Block */
4124 pDevice->pStatusBlkVirt->Status = 0;
4125 pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
4126 pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
4127 pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
4129 for(j = 0; j < 16; j++)
4131 pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
4132 pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
4135 for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++)
4137 pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
4138 pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
4139 pDevice->pRxStdBdVirt[k].Flags = RCV_BD_FLAG_END;
4140 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
4141 (pDevice->RxJumboBufferSize) )
4142 pDevice->pRxStdBdVirt[k].Len = pDevice->RxJumboBufferSize;
4144 pDevice->pRxStdBdVirt[k].Len = MAX_STD_RCV_BUFFER_SIZE;
4147 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4148 /* Receive jumbo BD buffer. */
4149 for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++)
4151 pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
4152 pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
4153 pDevice->pRxJumboBdVirt[k].Flags = RCV_BD_FLAG_END |
4154 RCV_BD_FLAG_JUMBO_RING;
4155 pDevice->pRxJumboBdVirt[k].Len = (LM_UINT16) pDevice->RxJumboBufferSize;
4159 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
4161 /* GRC mode control register. */
4163 #ifdef BIG_ENDIAN_HOST
4164 GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
4165 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
4166 GRC_MODE_BYTE_SWAP_DATA |
4167 GRC_MODE_WORD_SWAP_DATA |
4169 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
4170 GRC_MODE_BYTE_SWAP_DATA |
4171 GRC_MODE_WORD_SWAP_DATA |
4173 GRC_MODE_INT_ON_MAC_ATTN |
4174 GRC_MODE_HOST_STACK_UP;
4176 /* Configure send BD mode. */
4177 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
4179 Value32 |= GRC_MODE_HOST_SEND_BDS;
4181 #ifdef BCM_NIC_SEND_BD
4184 Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
4188 /* Configure pseudo checksum mode. */
4189 if (pDevice->Flags & NO_TX_PSEUDO_HDR_CSUM_FLAG)
4191 Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
4194 if (pDevice->Flags & NO_RX_PSEUDO_HDR_CSUM_FLAG)
4196 Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
4199 pDevice->GrcMode = Value32;
4200 REG_WR(pDevice, Grc.Mode, Value32);
4202 /* Setup the timer prescalar register. */
4203 Value32 = REG_RD(pDevice, Grc.MiscCfg) & ~0xff;
4204 /* Clock is always 66Mhz. */
4205 REG_WR(pDevice, Grc.MiscCfg, Value32 | (65 << 1));
4207 /* Set up the MBUF pool base address and size. */
4208 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
4210 #ifdef INCLUDE_TCP_SEG_SUPPORT
4211 if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)
4213 Value32 = LM_GetStkOffLdFirmwareSize(pDevice);
4214 Value32 = (Value32 + 0x7f) & ~0x7f;
4215 pDevice->MbufBase = T3_NIC_BCM5705_MBUF_POOL_ADDR + Value32;
4216 pDevice->MbufSize = T3_NIC_BCM5705_MBUF_POOL_SIZE - Value32 - 0xa00;
4217 REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
4218 REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
4222 else if (!T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4224 REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
4225 REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
4227 /* Set up the DMA descriptor pool base address and size. */
4228 REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
4229 REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
4233 /* Configure MBUF and Threshold watermarks */
4234 /* Configure the DMA read MBUF low water mark. */
4235 if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
4237 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4239 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4240 T3_DEF_DMA_MBUF_LOW_WMARK_5705);
4241 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4242 T3_DEF_RX_MAC_MBUF_LOW_WMARK_5705);
4243 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4244 T3_DEF_MBUF_HIGH_WMARK_5705);
4248 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4249 T3_DEF_DMA_MBUF_LOW_WMARK);
4250 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4251 T3_DEF_RX_MAC_MBUF_LOW_WMARK);
4252 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4253 T3_DEF_MBUF_HIGH_WMARK);
4255 }else if( T3_ASIC_5714_FAMILY(pDevice->ChipRevId)){
4257 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,0);
4258 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,0x4b);
4259 REG_WR(pDevice, BufMgr.MbufHighWaterMark,0x96);
4263 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4264 T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
4265 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4266 T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
4267 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4268 T3_DEF_MBUF_HIGH_WMARK_JUMBO);
4271 REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
4272 REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
4274 /* Enable buffer manager. */
4275 REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
4277 for(j = 0 ;j < 2000; j++)
4279 if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
4286 return LM_STATUS_FAILURE;
4289 /* GRC reset will reset FTQ */
4291 /* Enable the FTQs. */
4292 REG_WR(pDevice, Ftq.Reset, 0xffffffff);
4293 REG_WR(pDevice, Ftq.Reset, 0);
4295 /* Wait until FTQ is ready */
4296 for(j = 0; j < 2000; j++)
4298 if(REG_RD(pDevice, Ftq.Reset) == 0)
4305 return LM_STATUS_FAILURE;
4309 /* Receive BD Ring replenish threshold. */
4310 REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8);
4312 /* Initialize the Standard Receive RCB. */
4313 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
4314 pDevice->RxStdBdPhy.High);
4315 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
4316 pDevice->RxStdBdPhy.Low);
4317 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
4318 (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
4320 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4322 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
4327 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
4328 MAX_STD_RCV_BUFFER_SIZE << 16);
4330 /* Initialize the Jumbo Receive RCB. */
4331 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
4332 T3_RCB_FLAG_RING_DISABLED);
4333 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4334 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
4335 pDevice->RxJumboBdPhy.High);
4336 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
4337 pDevice->RxJumboBdPhy.Low);
4338 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
4339 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
4340 (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
4342 REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8);
4344 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
4346 /* Initialize the Mini Receive RCB. */
4347 REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
4348 T3_RCB_FLAG_RING_DISABLED);
4350 /* Disable all the unused rings. */
4351 for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
4352 MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags,
4353 T3_RCB_FLAG_RING_DISABLED);
4358 /* Initialize the indices. */
4359 pDevice->SendProdIdx = 0;
4360 pDevice->SendConIdx = 0;
4362 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
4363 MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low);
4364 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
4365 MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low);
4367 /* Set up host or NIC based send RCB. */
4368 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
4370 MEM_WR(pDevice, SendRcb[0].HostRingAddr.High,
4371 pDevice->SendBdPhy.High);
4372 MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low,
4373 pDevice->SendBdPhy.Low);
4375 /* Setup the RCB. */
4376 MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags,
4377 T3_SEND_RCB_ENTRY_COUNT << 16);
4379 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4381 /* Set up the NIC ring address in the RCB. */
4382 MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR);
4384 for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
4386 pDevice->pSendBdVirt[k].HostAddr.High = 0;
4387 pDevice->pSendBdVirt[k].HostAddr.Low = 0;
4390 #ifdef BCM_NIC_SEND_BD
4393 MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0);
4394 MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0);
4395 MEM_WR(pDevice, SendRcb[0].NicRingAddr,
4396 pDevice->SendBdPhy.Low);
4398 for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
4400 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.High), 0);
4401 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.Low), 0);
4402 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].u1.Len_Flags), 0);
4403 pDevice->ShadowSendBd[k].HostAddr.High = 0;
4404 pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
4408 MM_ATOMIC_SET(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1);
4410 /* Configure the receive return rings. */
4411 for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++)
4413 MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
4416 pDevice->RcvRetConIdx = 0;
4418 MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High,
4419 pDevice->RcvRetBdPhy.High);
4420 MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low,
4421 pDevice->RcvRetBdPhy.Low);
4423 MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0);
4425 /* Setup the RCB. */
4426 MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags,
4427 pDevice->RcvRetRcbEntryCount << 16);
4429 /* Reinitialize RX ring producer index */
4430 MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0);
4431 MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low);
4432 MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
4433 MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low);
4434 MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
4435 MB_REG_RD(pDevice, Mailbox.RcvMiniProdIdx.Low);
4437 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4438 pDevice->RxJumboProdIdx = 0;
4439 pDevice->RxJumboQueuedCnt = 0;
4442 /* Reinitialize our copy of the indices. */
4443 pDevice->RxStdProdIdx = 0;
4444 pDevice->RxStdQueuedCnt = 0;
4446 #if T3_JUMBO_RCV_ENTRY_COUNT
4447 pDevice->RxJumboProdIdx = 0;
4448 #endif /* T3_JUMBO_RCV_ENTRY_COUNT */
4450 /* Configure the MAC address. */
4451 LM_SetMacAddress(pDevice, pDevice->NodeAddress);
4453 /* Initialize the transmit random backoff seed. */
4454 Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
4455 pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
4456 pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
4457 MAC_TX_BACKOFF_SEED_MASK;
4458 REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32);
4460 /* Receive MTU. Frames larger than the MTU is marked as oversized. */
4461 REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
4463 /* Configure Time slot/IPG per 802.3 */
4464 REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
4467 * Configure Receive Rules so that packets don't match
4468 * Programmble rule will be queued to Return Ring 1
4470 REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
4473 * Configure to have 16 Classes of Services (COS) and one
4474 * queue per class. Bad frames are queued to RRR#1.
4475 * And frames don't match rules are also queued to COS#1.
4477 REG_WR(pDevice, RcvListPlmt.Config, 0x181);
4479 /* Enable Receive Placement Statistics */
4480 if ((pDevice->DmaReadFifoSize == DMA_READ_MODE_FIFO_LONG_BURST) &&
4481 (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION))
4483 Value32 = REG_RD(pDevice, RcvListPlmt.StatsEnableMask);
4484 Value32 &= ~T3_DISABLE_LONG_BURST_READ_DYN_FIX;
4485 REG_WR(pDevice, RcvListPlmt.StatsEnableMask, Value32);
4489 REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff);
4491 REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
4493 /* Enable Send Data Initator Statistics */
4494 REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff);
4495 REG_WR(pDevice, SndDataIn.StatsCtrl,
4496 T3_SND_DATA_IN_STATS_CTRL_ENABLE | \
4497 T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
4499 /* Disable the host coalescing state machine before configuring it's */
4501 REG_WR(pDevice, HostCoalesce.Mode, 0);
4502 for(j = 0; j < 2000; j++)
4504 Value32 = REG_RD(pDevice, HostCoalesce.Mode);
4505 if(!(Value32 & HOST_COALESCE_ENABLE))
4512 /* Host coalescing configurations. */
4513 REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks);
4514 REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks);
4515 REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames,
4516 pDevice->RxMaxCoalescedFrames);
4517 REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames,
4518 pDevice->TxMaxCoalescedFrames);
4520 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4522 REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt,
4523 pDevice->RxCoalescingTicksDuringInt);
4524 REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt,
4525 pDevice->TxCoalescingTicksDuringInt);
4527 REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
4528 pDevice->RxMaxCoalescedFramesDuringInt);
4529 REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
4530 pDevice->TxMaxCoalescedFramesDuringInt);
4532 /* Initialize the address of the status block. The NIC will DMA */
4533 /* the status block to this memory which resides on the host. */
4534 REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High,
4535 pDevice->StatusBlkPhy.High);
4536 REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low,
4537 pDevice->StatusBlkPhy.Low);
4539 /* Initialize the address of the statistics block. The NIC will DMA */
4540 /* the statistics to this block of memory. */
4541 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4543 REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High,
4544 pDevice->StatsBlkPhy.High);
4545 REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low,
4546 pDevice->StatsBlkPhy.Low);
4548 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
4549 pDevice->StatsCoalescingTicks);
4551 REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
4552 REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00);
4555 /* Enable Host Coalesing state machine */
4556 REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
4557 pDevice->CoalesceMode);
4559 /* Enable the Receive BD Completion state machine. */
4560 REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
4561 RCV_BD_COMP_MODE_ATTN_ENABLE);
4563 /* Enable the Receive List Placement state machine. */
4564 REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
4566 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4568 /* Enable the Receive List Selector state machine. */
4569 REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
4570 RCV_LIST_SEL_MODE_ATTN_ENABLE);
4573 /* Reset the Rx MAC State Machine.
4575 * The Rx MAC State Machine must be reset when using fiber to prevent the
4576 * first packet being lost. This is needed primarily so that the loopback
4577 * test (which currently only sends one packet) doesn't fail.
4579 * Also note that the Rx MAC State Machine (0x468) should be reset _before_
4580 * writting to the MAC Mode register (0x400). Failures have been seen on
4581 * 5780/5714's using fiber where they stopped receiving packets in a simple
4582 * ping test when the Rx MAC State Machine was reset _after_ the MAC Mode
4586 if ((pDevice->TbiFlags & ENABLE_TBI_FLAG) ||
4587 (pDevice->PhyFlags & PHY_IS_FIBER))
4589 REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET);
4590 REG_RD_BACK(pDevice, MacCtrl.RxMode);
4592 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
4593 REG_RD_BACK(pDevice, MacCtrl.RxMode);
4596 /* Clear the statistics block. */
4597 for(j = 0x0300; j < 0x0b00; j = j + 4)
4599 MEM_WR_OFFSET(pDevice, j, 0);
4603 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
4605 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
4607 else if(pDevice->PhyFlags & PHY_IS_FIBER)
4609 pDevice->MacMode = MAC_MODE_PORT_MODE_GMII;
4613 pDevice->MacMode = 0;
4616 /* Enable transmit DMA, clear statistics. */
4617 pDevice->MacMode |= MAC_MODE_ENABLE_TX_STATISTICS |
4618 MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
4619 MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
4620 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
4621 MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
4623 /* GRC miscellaneous local control register. */
4624 pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
4625 GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
4627 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
4629 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
4630 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
4632 else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) &&
4633 !(pDevice->Flags & EEPROM_WP_FLAG))
4635 /* Make sure we're on Vmain */
4636 /* The other port may cause us to be on Vaux */
4637 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
4638 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2;
4641 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4644 /* Reset RX counters. */
4645 for(j = 0; j < sizeof(LM_RX_COUNTERS); j++)
4647 ((PLM_UINT8) &pDevice->RxCounters)[j] = 0;
4650 /* Reset TX counters. */
4651 for(j = 0; j < sizeof(LM_TX_COUNTERS); j++)
4653 ((PLM_UINT8) &pDevice->TxCounters)[j] = 0;
4656 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
4657 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4658 pDevice->LastTag = 0;
4660 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4662 /* Enable the DMA Completion state machine. */
4663 REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
4666 /* Enable the DMA Write state machine. */
4667 Value32 = DMA_WRITE_MODE_ENABLE |
4668 DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
4669 DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
4670 DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
4671 DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
4672 DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
4673 DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
4674 DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
4675 DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
4677 if (pDevice->Flags & DMA_WR_MODE_RX_ACCELERATE_FLAG)
4679 Value32 |= DMA_WRITE_MODE_RECEIVE_ACCELERATE;
4682 if (pDevice->Flags & HOST_COALESCING_BUG_FIX)
4684 Value32 |= (1 << 29);
4687 REG_WR(pDevice, DmaWrite.Mode, Value32);
4689 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
4691 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
4693 Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities);
4694 Value32 &= ~PCIX_CMD_MAX_BURST_MASK;
4695 Value32 |= PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL;
4696 REG_WR(pDevice, PciCfg.PciXCapabilities, Value32);
4698 else if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
4700 Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities);
4701 Value32 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK);
4702 Value32 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) &
4703 PCIX_CMD_MAX_BURST_MASK);
4704 if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG)
4706 Value32 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
4707 & PCIX_CMD_MAX_SPLIT_MASK;
4709 REG_WR(pDevice, PciCfg.PciXCapabilities, Value32);
4713 /* Enable the Read DMA state machine. */
4714 Value32 = DMA_READ_MODE_ENABLE |
4715 DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
4716 DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
4717 DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
4718 DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
4719 DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
4720 DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
4721 DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
4722 DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
4724 if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG)
4726 Value32 |= DMA_READ_MODE_MULTI_SPLIT_ENABLE;
4729 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4731 Value32 |= pDevice->DmaReadFifoSize;
4733 #ifdef INCLUDE_TCP_SEG_SUPPORT
4734 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4741 REG_WR(pDevice, DmaRead.Mode, Value32);
4743 /* Enable the Receive Data Completion state machine. */
4744 REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
4745 RCV_DATA_COMP_MODE_ATTN_ENABLE);
4747 if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4749 /* Enable the Mbuf Cluster Free state machine. */
4750 REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
4753 /* Enable the Send Data Completion state machine. */
4754 REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
4756 /* Enable the Send BD Completion state machine. */
4757 REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
4758 SND_BD_COMP_MODE_ATTN_ENABLE);
4760 /* Enable the Receive BD Initiator state machine. */
4761 REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
4762 RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
4764 /* Enable the Receive Data and Receive BD Initiator state machine. */
4765 REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
4766 RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
4768 /* Enable the Send Data Initiator state machine. */
4769 REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
4771 #ifdef INCLUDE_TCP_SEG_SUPPORT
4772 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4774 REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE | 0x8);
4778 /* Enable the Send BD Initiator state machine. */
4779 REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
4780 SND_BD_IN_MODE_ATTN_ENABLE);
4782 /* Enable the Send BD Selector state machine. */
4783 REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
4784 SND_BD_SEL_MODE_ATTN_ENABLE);
4786 #ifdef INCLUDE_5701_AX_FIX
4787 /* Load the firmware for the 5701_A0 workaround. */
4788 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0)
4790 LM_LoadRlsFirmware(pDevice);
4794 /* Queue Rx packet buffers. */
4795 if(pDevice->QueueRxPackets)
4797 LM_QueueRxPackets(pDevice);
4800 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)
4802 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8);
4804 while ((Value32 != MAX_STD_RCV_BUFFER_SIZE) && (j < 10))
4807 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8);
4814 if (reset_count > 5)
4815 return LM_STATUS_FAILURE;
4820 /* Enable the transmitter. */
4821 pDevice->TxMode = TX_MODE_ENABLE;
4822 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
4824 /* Enable the receiver. */
4825 pDevice->RxMode = (pDevice->RxMode & RX_MODE_KEEP_VLAN_TAG) |
4827 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
4830 if (pDevice->RestoreOnWakeUp)
4832 pDevice->RestoreOnWakeUp = FALSE;
4833 pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
4834 pDevice->RequestedLineSpeed = pDevice->WakeUpRequestedLineSpeed;
4835 pDevice->RequestedDuplexMode = pDevice->WakeUpRequestedDuplexMode;
4839 /* Disable auto polling. */
4840 pDevice->MiMode = 0xc0000;
4841 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
4843 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
4845 /* Activate Link to enable MAC state machine */
4846 REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
4848 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
4850 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1)
4852 REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000);
4854 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
4857 if(!(pDevice->TbiFlags & TBI_DO_PREEMPHASIS))
4859 /* Set SerDes drive transmission level to 1.2V */
4860 Value32 = REG_RD(pDevice, MacCtrl.SerdesCfg) & 0xfffff000;
4861 REG_WR(pDevice, MacCtrl.SerdesCfg, Value32 | 0x880);
4866 REG_WR(pDevice, MacCtrl.LowWaterMarkMaxRxFrame, 2);
4868 /* ecd 13216 workaround for serdes */
4869 if ((pDevice->PhyFlags & PHY_IS_FIBER) &&
4870 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5780))
4872 Value32 = REG_RD_OFFSET(pDevice, 0x5b0);
4873 REG_WR_OFFSET(pDevice, 0x5b0, Value32 | BIT_10 );
4875 pDevice->GrcLocalCtrl |= BIT_4 ;
4876 pDevice->GrcLocalCtrl &= ~BIT_5 ;
4878 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4879 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
4883 if (!pDevice->InitDone)
4885 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
4888 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
4889 ( ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5401_PHY_ID)&&
4890 ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) ))
4892 /* 5401/5411 PHY needs a delay of about 1 second after PHY reset */
4893 /* Without the delay, it has problem linking at forced 10 half */
4894 /* So skip the reset... */
4895 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5780)
4896 for(j =0; j<0x5000; j++)
4899 LM_ResetPhy(pDevice);
4902 /* Setup the phy chip. */
4903 LM_SetupPhy(pDevice);
4905 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG)){
4906 /* Clear CRC stats */
4907 LM_ReadPhy(pDevice, 0x1e, &Value32);
4908 LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000);
4909 LM_ReadPhy(pDevice, 0x14, &Value32);
4912 /* Set up the receive mask. */
4913 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask);
4915 #ifdef INCLUDE_TCP_SEG_SUPPORT
4916 if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)
4918 if (LM_LoadStkOffLdFirmware(pDevice) == LM_STATUS_FAILURE)
4920 return LM_STATUS_FAILURE;
4924 LM_WritePostResetSignatures(pDevice, LM_INIT_RESET);
4926 return LM_STATUS_SUCCESS;
4927 } /* LM_ResetAdapter */
4930 /******************************************************************************/
4932 /* This routine disables the adapter from generating interrupts. */
4935 /* LM_STATUS_SUCCESS */
4936 /******************************************************************************/
4938 LM_DisableInterrupt(
4939 PLM_DEVICE_BLOCK pDevice)
4941 REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
4942 MISC_HOST_CTRL_MASK_PCI_INT);
4943 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
4944 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4946 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4949 return LM_STATUS_SUCCESS;
4954 /******************************************************************************/
4956 /* This routine enables the adapter to generate interrupts. */
4959 /* LM_STATUS_SUCCESS */
4960 /******************************************************************************/
4963 PLM_DEVICE_BLOCK pDevice)
4965 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, pDevice->LastTag << 24);
4966 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4968 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4971 REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
4972 ~MISC_HOST_CTRL_MASK_PCI_INT);
4974 REG_WR(pDevice, HostCoalesce.Mode, pDevice->CoalesceMode |
4975 HOST_COALESCE_ENABLE | HOST_COALESCE_NOW);
4977 return LM_STATUS_SUCCESS;
4982 /******************************************************************************/
4984 /* This routine puts a packet on the wire if there is a transmit DMA */
4985 /* descriptor available; otherwise the packet is queued for later */
4986 /* transmission. If the second argue is NULL, this routine will put */
4987 /* the queued packet on the wire if possible. */
4990 /* LM_STATUS_SUCCESS */
4991 /******************************************************************************/
4993 LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
4995 LM_UINT32 FragCount;
4996 PT3_SND_BD pSendBd, pTmpSendBd;
4997 #ifdef BCM_NIC_SEND_BD
4998 PT3_SND_BD pShadowSendBd;
4999 T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
5001 LM_UINT32 StartIdx, Idx;
5005 /* Initalize the send buffer descriptors. */
5006 StartIdx = Idx = pDevice->SendProdIdx;
5008 #ifdef BCM_NIC_SEND_BD
5009 if (pDevice->Flags & NIC_SEND_BD_FLAG)
5011 pTmpSendBd = pSendBd = &NicSendBdArr[0];
5016 pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
5019 /* Next producer index. */
5020 for(FragCount = 0; ; )
5022 LM_UINT32 Value32, Len;
5024 /* Initialize the pointer to the send buffer fragment. */
5025 MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
5027 pSendBd->u2.VlanTag = pPacket->VlanTag;
5029 /* Setup the control flags and send buffer size. */
5030 Value32 = (Len << 16) | pPacket->Flags;
5032 #ifdef INCLUDE_TCP_SEG_SUPPORT
5033 if (Value32 & (SND_BD_FLAG_CPU_PRE_DMA | SND_BD_FLAG_CPU_POST_DMA))
5035 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
5037 pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize;
5039 else if (FragCount == 0)
5041 pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize;
5045 pSendBd->u2.s2.Reserved = 0;
5046 Value32 &= 0xffff0fff;
5050 Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5053 if (FragCount >= pPacket->u.Tx.FragCount)
5055 pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
5060 pSendBd->u1.Len_Flags = Value32;
5065 !(pDevice->Flags & NIC_SEND_BD_FLAG))
5067 pSendBd = &pDevice->pSendBdVirt[0];
5070 pDevice->SendRing[Idx] = 0;
5073 if (pDevice->Flags & TX_4G_WORKAROUND_FLAG)
5075 if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) ==
5078 if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS)
5080 QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
5081 return LM_STATUS_FAILURE;
5088 /* Put the packet descriptor in the ActiveQ. */
5089 pDevice->SendRing[StartIdx] = pPacket;
5091 #ifdef BCM_NIC_SEND_BD
5092 if (pDevice->Flags & NIC_SEND_BD_FLAG)
5094 pSendBd = &pDevice->pSendBdVirt[StartIdx];
5095 pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
5097 while (StartIdx != Idx)
5101 if ((Value32 = pTmpSendBd->HostAddr.High) !=
5102 pShadowSendBd->HostAddr.High)
5104 MM_MEMWRITEL(&(pSendBd->HostAddr.High), Value32);
5105 pShadowSendBd->HostAddr.High = Value32;
5108 MM_MEMWRITEL(&(pSendBd->HostAddr.Low), pTmpSendBd->HostAddr.Low);
5110 if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
5111 pShadowSendBd->u1.Len_Flags)
5113 MM_MEMWRITEL(&(pSendBd->u1.Len_Flags), Value32);
5114 pShadowSendBd->u1.Len_Flags = Value32;
5117 if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG)
5119 MM_MEMWRITEL(&(pSendBd->u2.VlanTag), pTmpSendBd->u2.VlanTag);
5122 StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5125 pSendBd = &pDevice->pSendBdVirt[0];
5126 pShadowSendBd = &pDevice->ShadowSendBd[0];
5136 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
5138 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
5140 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
5142 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
5144 MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low);
5155 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
5157 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
5159 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
5161 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
5163 MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low);
5171 /* Update the SendBdLeft count. */
5172 MM_ATOMIC_SUB(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5174 /* Update the producer index. */
5175 pDevice->SendProdIdx = Idx;
5177 return LM_STATUS_SUCCESS;
5181 LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
5185 LM_UINT32 Idx, Base, Len;
5187 Idx = pDevice->SendProdIdx;
5188 for(FragCount = 0; ; )
5190 Len = pSendBd->u1.Len_Flags >> 16;
5191 if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
5192 ((Base + 8 + Len) < Base))
5194 return LM_STATUS_SUCCESS;
5197 if (FragCount >= pPacket->u.Tx.FragCount)
5202 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
5204 Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5207 pSendBd = &pDevice->pSendBdVirt[0];
5211 return LM_STATUS_FAILURE;
5214 /******************************************************************************/
5218 /******************************************************************************/
5220 ComputeCrc32(LM_UINT8 *pBuffer, LM_UINT32 BufferSize)
5228 for(j = 0; j < BufferSize; j++)
5232 for(k = 0; k < 8; k++)
5246 } /* ComputeCrc32 */
5250 /******************************************************************************/
5252 /* This routine sets the receive control register according to ReceiveMask */
5255 /* LM_STATUS_SUCCESS */
5256 /******************************************************************************/
5258 LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
5260 LM_UINT32 ReceiveMask;
5266 RxMode = pDevice->RxMode;
5268 if(Mask & LM_ACCEPT_UNICAST)
5270 Mask &= ~LM_ACCEPT_UNICAST;
5273 if(Mask & LM_ACCEPT_MULTICAST)
5275 Mask &= ~LM_ACCEPT_MULTICAST;
5278 if(Mask & LM_ACCEPT_ALL_MULTICAST)
5280 Mask &= ~LM_ACCEPT_ALL_MULTICAST;
5283 if(Mask & LM_ACCEPT_BROADCAST)
5285 Mask &= ~LM_ACCEPT_BROADCAST;
5288 RxMode &= ~RX_MODE_KEEP_VLAN_TAG;
5289 if (Mask & LM_KEEP_VLAN_TAG)
5291 RxMode |= RX_MODE_KEEP_VLAN_TAG;
5292 Mask &= ~LM_KEEP_VLAN_TAG;
5295 RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
5296 if(Mask & LM_PROMISCUOUS_MODE)
5298 RxMode |= RX_MODE_PROMISCUOUS_MODE;
5299 Mask &= ~LM_PROMISCUOUS_MODE;
5302 RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
5303 if(Mask & LM_ACCEPT_ERROR_PACKET)
5305 RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
5306 Mask &= ~LM_ACCEPT_ERROR_PACKET;
5309 /* Make sure all the bits are valid before committing changes. */
5312 return LM_STATUS_FAILURE;
5315 /* Commit the new filter. */
5316 pDevice->ReceiveMask = ReceiveMask;
5318 pDevice->RxMode = RxMode;
5320 if (pDevice->PowerLevel != LM_POWER_STATE_D0)
5322 return LM_STATUS_SUCCESS;
5325 REG_WR(pDevice, MacCtrl.RxMode, RxMode);
5327 /* Set up the MC hash table. */
5328 if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST)
5330 for(k = 0; k < 4; k++)
5332 REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff);
5335 else if(ReceiveMask & LM_ACCEPT_MULTICAST)
5337 for(k = 0; k < 4; k++)
5339 REG_WR(pDevice, MacCtrl.HashReg[k], pDevice->MulticastHash[k]);
5344 /* Reject all multicast frames. */
5345 for(j = 0; j < 4; j++)
5347 REG_WR(pDevice, MacCtrl.HashReg[j], 0);
5351 /* By default, Tigon3 will accept broadcast frames. We need to setup */
5352 if(ReceiveMask & LM_ACCEPT_BROADCAST)
5354 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
5355 REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
5356 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
5357 REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
5358 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
5359 REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
5360 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
5361 REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
5365 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
5366 REJECT_BROADCAST_RULE1_RULE);
5367 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
5368 REJECT_BROADCAST_RULE1_VALUE);
5369 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
5370 REJECT_BROADCAST_RULE2_RULE);
5371 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
5372 REJECT_BROADCAST_RULE2_VALUE);
5375 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
5379 else if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
5388 if (pDevice->AsfFlags & ASF_ENABLED)
5394 /* disable the rest of the rules. */
5395 for(j = RCV_LAST_RULE_IDX; j < k; j++)
5397 REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0);
5398 REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0);
5401 return LM_STATUS_SUCCESS;
5402 } /* LM_SetReceiveMask */
5406 /******************************************************************************/
5408 /* Disable the interrupt and put the transmitter and receiver engines in */
5409 /* an idle state. Also aborts all pending send requests and receive */
5413 /* LM_STATUS_SUCCESS */
5414 /******************************************************************************/
5417 PLM_DEVICE_BLOCK pDevice)
5422 LM_DisableInterrupt(pDevice);
5424 LM_DisableChip(pDevice);
5427 * If we do not have a status block pointer, then
5428 * the device hasn't really been opened. Do not
5429 * attempt to clean up packets.
5431 if (pDevice->pStatusBlkVirt == NULL)
5432 return LM_STATUS_SUCCESS;
5434 /* Abort packets that have already queued to go out. */
5435 Idx = pDevice->SendConIdx;
5438 if ((pPacket = pDevice->SendRing[Idx]))
5440 pDevice->SendRing[Idx] = 0;
5441 pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
5442 pDevice->TxCounters.TxPacketAbortedCnt++;
5444 MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5445 Idx = (Idx + pPacket->u.Tx.FragCount) &
5446 T3_SEND_RCB_ENTRY_COUNT_MASK;
5448 QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
5456 /* Cleanup the receive return rings. */
5457 #ifdef BCM_NAPI_RXPOLL
5458 LM_ServiceRxPoll(pDevice, T3_RCV_RETURN_RCB_ENTRY_COUNT);
5460 LM_ServiceRxInterrupt(pDevice);
5463 /* Indicate packets to the protocol. */
5464 MM_IndicateTxPackets(pDevice);
5466 #ifdef BCM_NAPI_RXPOLL
5468 /* Move the receive packet descriptors in the ReceivedQ to the */
5472 pPacket = (PLM_PACKET) QQ_PopHead(
5473 &pDevice->RxPacketReceivedQ.Container);
5478 MM_UnmapRxDma(pDevice, pPacket);
5479 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5482 /* Indicate received packets to the protocols. */
5483 MM_IndicateRxPackets(pDevice);
5486 /* Clean up the Std Receive Producer ring. */
5487 /* Don't always trust the consumer idx in the status block in case of */
5491 while(Idx < T3_STD_RCV_RCB_ENTRY_COUNT)
5493 if ((pPacket = pDevice->RxStdRing[Idx]))
5495 MM_UnmapRxDma(pDevice, pPacket);
5496 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5497 pDevice->RxStdRing[Idx] = 0;
5503 /* Reinitialize our copy of the indices. */
5504 pDevice->RxStdProdIdx = 0;
5506 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5507 /* Clean up the Jumbo Receive Producer ring. */
5510 while(Idx < T3_JUMBO_RCV_RCB_ENTRY_COUNT)
5512 if ((pPacket = pDevice->RxJumboRing[Idx]))
5514 MM_UnmapRxDma(pDevice, pPacket);
5515 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5516 pDevice->RxJumboRing[Idx] = 0;
5521 /* Reinitialize our copy of the indices. */
5522 pDevice->RxJumboProdIdx = 0;
5523 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
5525 /* Initialize the statistis Block */
5526 pDevice->pStatusBlkVirt->Status = 0;
5527 pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
5528 pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
5529 pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
5531 return LM_STATUS_SUCCESS;
5536 /******************************************************************************/
5538 /* Disable the interrupt and put the transmitter and receiver engines in */
5539 /* an idle state. Aborts all pending send requests and receive buffers. */
5540 /* Also free all the receive buffers. */
5543 /* LM_STATUS_SUCCESS */
5544 /******************************************************************************/
5546 LM_DoHalt(LM_DEVICE_BLOCK *pDevice)
5551 LM_DisableFW(pDevice);
5553 LM_WritePreResetSignatures(pDevice, LM_SHUTDOWN_RESET);
5556 /* Get the number of entries in the queue. */
5557 EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container);
5559 /* Make sure all the packets have been accounted for. */
5560 for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++)
5562 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
5566 MM_FreeRxBuffer(pDevice, pPacket);
5568 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5571 LM_ResetChip(pDevice);
5572 LM_WriteLegacySignatures(pDevice, LM_SHUTDOWN_RESET);
5574 /* Restore PCI configuration registers. */
5575 MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
5576 pDevice->SavedCacheLineReg);
5577 LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
5578 (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
5580 /* Reprogram the MAC address. */
5581 LM_SetMacAddress(pDevice, pDevice->NodeAddress);
5583 return LM_STATUS_SUCCESS;
5588 LM_Halt(LM_DEVICE_BLOCK *pDevice)
5592 status = LM_DoHalt(pDevice);
5593 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
5599 LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5601 MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,T3_MAGIC_NUM_FIRMWARE_INIT_DONE);
5603 if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE)
5605 if (Mode == LM_INIT_RESET)
5607 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START);
5609 else if (Mode == LM_SHUTDOWN_RESET)
5611 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD);
5613 else if (Mode == LM_SUSPEND_RESET)
5615 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND);
5622 LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5625 if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE)
5627 if (Mode == LM_INIT_RESET)
5629 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX,
5630 T3_DRV_STATE_START_DONE);
5632 else if (Mode == LM_SHUTDOWN_RESET)
5634 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX,
5635 T3_DRV_STATE_UNLOAD_DONE);
5642 LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5645 if (pDevice->AsfFlags & ASF_ENABLED)
5647 if (Mode == LM_INIT_RESET)
5649 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START);
5651 else if (Mode == LM_SHUTDOWN_RESET)
5653 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD);
5655 else if (Mode == LM_SUSPEND_RESET)
5657 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND);
5664 LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
5667 LM_UINT32 j, tmp1 = 0, tmp2 = 0;
5669 /* Wait for access to the nvram interface before resetting. This is */
5670 /* a workaround to prevent EEPROM corruption. */
5671 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
5672 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
5674 /* Request access to the flash interface. */
5675 LM_NVRAM_AcquireLock(pDevice);
5678 Value32 = GRC_MISC_CFG_CORE_CLOCK_RESET;
5679 if (pDevice->Flags & PCI_EXPRESS_FLAG)
5681 if (REG_RD_OFFSET(pDevice, 0x7e2c) == 0x60) /* PCIE 1.0 system */
5683 REG_WR_OFFSET(pDevice, 0x7e2c, 0x20);
5685 if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)
5687 /* This bit prevents PCIE link training during GRC reset */
5688 REG_WR(pDevice, Grc.MiscCfg, BIT_29); /* Write bit 29 first */
5689 Value32 |= BIT_29; /* and keep bit 29 set during GRC reset */
5692 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
5694 Value32 |= GRC_MISC_GPHY_KEEP_POWER_DURING_RESET;
5697 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
5699 /* Save the MSI ENABLE bit (may need to save the message as well) */
5700 tmp1 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5704 RAW_REG_WR(pDevice, Grc.MiscCfg, Value32);
5707 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
5711 /* make sure we re-enable indirect accesses */
5712 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG,
5713 pDevice->MiscHostCtrl);
5715 /* Set MAX PCI retry to zero. */
5716 Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
5717 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
5719 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
5721 Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
5724 MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32);
5726 /* Restore PCI command register. */
5727 MM_WriteConfig32(pDevice, PCI_COMMAND_REG,
5728 pDevice->PciCommandStatusWords);
5730 /* Disable PCI-X relaxed ordering bit. */
5731 MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32);
5732 Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
5733 MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32);
5735 /* Enable memory arbiter */
5736 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
5738 Value32 = REG_RD(pDevice,MemArbiter.Mode);
5739 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE | Value32);
5743 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
5746 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
5748 /* restore the MSI ENABLE bit (may need to restore the message also) */
5749 tmp2 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5750 tmp2 |= (tmp1 & (1 << 16));
5751 LM_RegWr( pDevice, T3_PCI_MSI_ENABLE, tmp2, TRUE );
5752 tmp2 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5756 if (pDevice->ChipRevId == T3_CHIP_ID_5750_A3)
5758 /* Because of chip bug on A3, we need to kill the CPU */
5759 LM_DisableFW(pDevice);
5760 REG_WR_OFFSET(pDevice, 0x5000, 0x400);
5762 #ifdef BIG_ENDIAN_HOST
5763 /* Reconfigure the mode register. */
5764 Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
5765 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
5766 GRC_MODE_BYTE_SWAP_DATA |
5767 GRC_MODE_WORD_SWAP_DATA;
5769 /* Reconfigure the mode register. */
5770 Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
5772 REG_WR(pDevice, Grc.Mode, Value32);
5774 if ((pDevice->Flags & MINI_PCI_FLAG) &&
5775 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705))
5777 pDevice->ClockCtrl |= T3_PCI_CLKRUN_OUTPUT_EN;
5778 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)
5780 pDevice->ClockCtrl |= T3_PCI_FORCE_CLKRUN;
5782 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl);
5785 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
5787 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
5789 else if(pDevice->PhyFlags & PHY_IS_FIBER)
5791 pDevice->MacMode = MAC_MODE_PORT_MODE_GMII;
5795 pDevice->MacMode = 0;
5798 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
5799 REG_RD_BACK(pDevice, MacCtrl.Mode);
5802 /* Wait for the firmware to finish initialization. */
5803 for(j = 0; j < 100000; j++)
5810 Value32 = MEM_RD_OFFSET(pDevice, T3_FIRMWARE_MAILBOX);
5811 if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE)
5816 if ((j >= 0x100000) && (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
5818 /* workaround - need to reset nvram of both devices at the same time */
5819 /* if the boot code is not running */
5820 if (LM_NVRAM_AcquireLock(pDevice) != LM_STATUS_SUCCESS)
5822 LM_DEVICE_BLOCK *pDevice2;
5824 REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET);
5825 pDevice2 = MM_FindPeerDev(pDevice);
5826 if (pDevice2 && !pDevice2->InitDone)
5828 REG_WR(pDevice2, Nvram.Cmd, NVRAM_CMD_RESET);
5833 LM_NVRAM_ReleaseLock(pDevice);
5838 if ((pDevice->Flags & PCI_EXPRESS_FLAG) &&
5839 (pDevice->ChipRevId != T3_CHIP_ID_5750_A0))
5841 /* Enable PCIE bug fix */
5842 Value32 = REG_RD_OFFSET(pDevice, 0x7c00);
5843 REG_WR_OFFSET(pDevice, 0x7c00, Value32 | BIT_25 | BIT_29);
5847 pDevice->AsfFlags = 0;
5848 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
5850 if (Value32 == T3_NIC_DATA_SIG)
5852 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
5853 if (Value32 & T3_NIC_CFG_ENABLE_ASF)
5855 pDevice->AsfFlags = ASF_ENABLED;
5856 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
5858 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
5864 return LM_STATUS_SUCCESS;
5869 LM_ShutdownChip(PLM_DEVICE_BLOCK pDevice, LM_RESET_TYPE Mode)
5871 LM_DisableFW(pDevice);
5872 LM_WritePreResetSignatures(pDevice, Mode);
5873 if (pDevice->InitDone)
5879 LM_DisableChip(pDevice);
5881 LM_ResetChip(pDevice);
5882 LM_WriteLegacySignatures(pDevice, Mode);
5883 LM_WritePostResetSignatures(pDevice, Mode);
5884 return LM_STATUS_SUCCESS;
5887 /******************************************************************************/
5891 /******************************************************************************/
5893 LM_ServiceTxInterrupt(
5894 PLM_DEVICE_BLOCK pDevice) {
5899 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
5901 /* Get our copy of the consumer index. The buffer descriptors */
5902 /* that are in between the consumer indices are freed. */
5903 SwConIdx = pDevice->SendConIdx;
5905 /* Move the packets from the TxPacketActiveQ that are sent out to */
5906 /* the TxPacketXmittedQ. Packets that are sent use the */
5907 /* descriptors that are between SwConIdx and HwConIdx. */
5908 while(SwConIdx != HwConIdx)
5910 pPacket = pDevice->SendRing[SwConIdx];
5911 pDevice->SendRing[SwConIdx] = 0;
5913 /* Set the return status. */
5914 pPacket->PacketStatus = LM_STATUS_SUCCESS;
5916 /* Put the packet in the TxPacketXmittedQ for indication later. */
5917 QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
5919 /* Move to the next packet's BD. */
5920 SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
5921 T3_SEND_RCB_ENTRY_COUNT_MASK;
5923 /* Update the number of unused BDs. */
5924 MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5926 /* Get the new updated HwConIdx. */
5927 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
5930 /* Save the new SwConIdx. */
5931 pDevice->SendConIdx = SwConIdx;
5933 } /* LM_ServiceTxInterrupt */
5936 #ifdef BCM_NAPI_RXPOLL
5937 /******************************************************************************/
5941 /******************************************************************************/
5943 LM_ServiceRxPoll(PLM_DEVICE_BLOCK pDevice, int limit)
5945 PLM_PACKET pPacket=NULL;
5947 LM_UINT32 HwRcvRetProdIdx;
5948 LM_UINT32 SwRcvRetConIdx;
5951 /* Loop thru the receive return rings for received packets. */
5952 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
5954 SwRcvRetConIdx = pDevice->RcvRetConIdx;
5956 while (SwRcvRetConIdx != HwRcvRetProdIdx)
5958 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
5960 /* Get the received packet descriptor. */
5961 pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
5962 MM_UINT_PTR(pRcvBd->Opaque));
5964 switch(pPacket->u.Rx.RcvProdRing) {
5965 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5966 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
5967 pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5970 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
5971 pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5975 /* Check the error flag. */
5976 if(pRcvBd->ErrorFlag &&
5977 pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
5979 pPacket->PacketStatus = LM_STATUS_FAILURE;
5981 pDevice->RxCounters.RxPacketErrCnt++;
5983 if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
5985 pDevice->RxCounters.RxErrCrcCnt++;
5988 if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
5990 pDevice->RxCounters.RxErrCollCnt++;
5993 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
5995 pDevice->RxCounters.RxErrLinkLostCnt++;
5998 if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
6000 pDevice->RxCounters.RxErrPhyDecodeCnt++;
6003 if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6005 pDevice->RxCounters.RxErrOddNibbleCnt++;
6008 if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
6010 pDevice->RxCounters.RxErrMacAbortCnt++;
6013 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
6015 pDevice->RxCounters.RxErrShortPacketCnt++;
6018 if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
6020 pDevice->RxCounters.RxErrNoResourceCnt++;
6023 if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
6025 pDevice->RxCounters.RxErrLargePacketCnt++;
6030 pPacket->PacketStatus = LM_STATUS_SUCCESS;
6031 pPacket->PacketSize = pRcvBd->Len - 4;
6033 pPacket->Flags = pRcvBd->Flags;
6034 if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
6036 pPacket->VlanTag = pRcvBd->VlanTag;
6039 pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
6042 /* Put the packet descriptor containing the received packet */
6043 /* buffer in the RxPacketReceivedQ for indication later. */
6044 QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
6046 /* Go to the next buffer descriptor. */
6047 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
6048 pDevice->RcvRetRcbEntryCountMask;
6050 if (++received >= limit)
6056 pDevice->RcvRetConIdx = SwRcvRetConIdx;
6058 /* Update the receive return ring consumer index. */
6059 MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
6060 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
6062 MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low);
6069 } /* LM_ServiceRxPoll */
6070 #endif /* BCM_NAPI_RXPOLL */
6073 /******************************************************************************/
6077 /******************************************************************************/
6079 LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice)
6081 #ifndef BCM_NAPI_RXPOLL
6085 LM_UINT32 HwRcvRetProdIdx;
6086 LM_UINT32 SwRcvRetConIdx;
6088 /* Loop thru the receive return rings for received packets. */
6089 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
6091 SwRcvRetConIdx = pDevice->RcvRetConIdx;
6092 #ifdef BCM_NAPI_RXPOLL
6093 if (!pDevice->RxPoll)
6095 if (SwRcvRetConIdx != HwRcvRetProdIdx)
6097 if (MM_ScheduleRxPoll(pDevice) == LM_STATUS_SUCCESS)
6099 pDevice->RxPoll = TRUE;
6100 REG_WR(pDevice, Grc.Mode,
6101 pDevice->GrcMode | GRC_MODE_NO_INTERRUPT_ON_RECEIVE);
6107 while(SwRcvRetConIdx != HwRcvRetProdIdx)
6109 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
6111 /* Get the received packet descriptor. */
6112 pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
6113 MM_UINT_PTR(pRcvBd->Opaque));
6115 switch(pPacket->u.Rx.RcvProdRing) {
6116 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
6117 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
6118 pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
6121 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
6122 pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
6126 /* Check the error flag. */
6127 if(pRcvBd->ErrorFlag &&
6128 pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6130 pPacket->PacketStatus = LM_STATUS_FAILURE;
6132 pDevice->RxCounters.RxPacketErrCnt++;
6134 if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
6136 pDevice->RxCounters.RxErrCrcCnt++;
6139 if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
6141 pDevice->RxCounters.RxErrCollCnt++;
6144 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
6146 pDevice->RxCounters.RxErrLinkLostCnt++;
6149 if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
6151 pDevice->RxCounters.RxErrPhyDecodeCnt++;
6154 if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6156 pDevice->RxCounters.RxErrOddNibbleCnt++;
6159 if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
6161 pDevice->RxCounters.RxErrMacAbortCnt++;
6164 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
6166 pDevice->RxCounters.RxErrShortPacketCnt++;
6169 if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
6171 pDevice->RxCounters.RxErrNoResourceCnt++;
6174 if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
6176 pDevice->RxCounters.RxErrLargePacketCnt++;
6181 pPacket->PacketStatus = LM_STATUS_SUCCESS;
6182 pPacket->PacketSize = pRcvBd->Len - 4;
6184 pPacket->Flags = pRcvBd->Flags;
6185 if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
6187 pPacket->VlanTag = pRcvBd->VlanTag;
6190 pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
6193 /* Put the packet descriptor containing the received packet */
6194 /* buffer in the RxPacketReceivedQ for indication later. */
6195 QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
6197 /* Go to the next buffer descriptor. */
6198 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
6199 pDevice->RcvRetRcbEntryCountMask;
6203 pDevice->RcvRetConIdx = SwRcvRetConIdx;
6205 /* Update the receive return ring consumer index. */
6206 MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
6207 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
6209 MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low);
6217 } /* LM_ServiceRxInterrupt */
6221 /******************************************************************************/
6223 /* This is the interrupt event handler routine. It acknowledges all */
6224 /* pending interrupts and process all pending events. */
6227 /* LM_STATUS_SUCCESS */
6228 /******************************************************************************/
6230 LM_ServiceInterrupts(
6231 PLM_DEVICE_BLOCK pDevice)
6234 int ServicePhyInt = FALSE;
6236 /* Setup the phy chip whenever the link status changes. */
6237 if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG)
6239 Value32 = REG_RD(pDevice, MacCtrl.Status);
6240 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
6242 if (Value32 & MAC_STATUS_MI_INTERRUPT)
6244 ServicePhyInt = TRUE;
6247 else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED)
6249 ServicePhyInt = TRUE;
6254 if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS)
6256 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
6257 (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
6258 ServicePhyInt = TRUE;
6261 #ifdef INCLUDE_TBI_SUPPORT
6262 if (pDevice->IgnoreTbiLinkChange == TRUE)
6264 ServicePhyInt = FALSE;
6267 if (ServicePhyInt == TRUE)
6269 MM_ACQUIRE_PHY_LOCK_IN_IRQ(pDevice);
6270 LM_SetupPhy(pDevice);
6271 MM_RELEASE_PHY_LOCK_IN_IRQ(pDevice);
6274 /* Service receive and transmit interrupts. */
6275 LM_ServiceRxInterrupt(pDevice);
6276 LM_ServiceTxInterrupt(pDevice);
6278 #ifndef BCM_NAPI_RXPOLL
6279 /* No spinlock for this queue since this routine is serialized. */
6280 if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container))
6282 /* Indicate receive packets. */
6283 MM_IndicateRxPackets(pDevice);
6287 /* No spinlock for this queue since this routine is serialized. */
6288 if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container))
6290 MM_IndicateTxPackets(pDevice);
6293 return LM_STATUS_SUCCESS;
6294 } /* LM_ServiceInterrupts */
6297 /******************************************************************************/
6298 /* Description: Add a Multicast address. Note that MC addresses, once added, */
6299 /* cannot be individually deleted. All addresses must be */
6303 /******************************************************************************/
6305 LM_MulticastAdd(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress)
6312 Crc32 = ComputeCrc32(pMcAddress, ETHERNET_ADDRESS_SIZE);
6314 /* The most significant 7 bits of the CRC32 (no inversion), */
6315 /* are used to index into one of the possible 128 bit positions. */
6316 Bitpos = ~Crc32 & 0x7f;
6318 /* Hash register index. */
6319 RegIndex = (Bitpos & 0x60) >> 5;
6321 /* Bit to turn on within a hash register. */
6324 /* Enable the multicast bit. */
6325 pDevice->MulticastHash[RegIndex] |= (1 << Bitpos);
6327 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
6329 return LM_STATUS_SUCCESS;
6333 /******************************************************************************/
6337 /******************************************************************************/
6339 LM_MulticastDel(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress)
6341 return LM_STATUS_FAILURE;
6342 } /* LM_MulticastDel */
6346 /******************************************************************************/
6350 /******************************************************************************/
6352 LM_MulticastClear(LM_DEVICE_BLOCK *pDevice)
6356 for (i = 0; i < 4; i++)
6358 pDevice->MulticastHash[i] = 0;
6360 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
6362 return LM_STATUS_SUCCESS;
6363 } /* LM_MulticastClear */
6367 /******************************************************************************/
6371 /******************************************************************************/
6374 PLM_DEVICE_BLOCK pDevice,
6375 PLM_UINT8 pMacAddress)
6379 for(j = 0; j < 4; j++)
6381 REG_WR(pDevice, MacCtrl.MacAddr[j].High,
6382 (pMacAddress[0] << 8) | pMacAddress[1]);
6383 REG_WR(pDevice, MacCtrl.MacAddr[j].Low,
6384 (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
6385 (pMacAddress[4] << 8) | pMacAddress[5]);
6388 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
6389 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
6391 for (j = 0; j < 12; j++)
6393 REG_WR(pDevice, MacCtrl.MacAddrExt[j].High,
6394 (pMacAddress[0] << 8) | pMacAddress[1]);
6395 REG_WR(pDevice, MacCtrl.MacAddrExt[j].Low,
6396 (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
6397 (pMacAddress[4] << 8) | pMacAddress[5]);
6400 return LM_STATUS_SUCCESS;
6404 LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice)
6406 /* Turn off tap power management. */
6407 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
6409 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
6410 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
6411 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
6412 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
6413 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
6414 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
6415 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
6416 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
6417 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
6418 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
6419 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
6425 /******************************************************************************/
6429 /* LM_STATUS_LINK_ACTIVE */
6430 /* LM_STATUS_LINK_DOWN */
6431 /******************************************************************************/
6434 PLM_DEVICE_BLOCK pDevice)
6436 LM_LINE_SPEED CurrentLineSpeed;
6437 LM_DUPLEX_MODE CurrentDuplexMode;
6438 LM_STATUS CurrentLinkStatus;
6442 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02);
6444 if ((pDevice->PhyFlags & PHY_RESET_ON_LINKDOWN) &&
6445 (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE))
6447 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6448 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6449 if(!(Value32 & PHY_STATUS_LINK_PASS))
6451 LM_ResetPhy(pDevice);
6454 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
6456 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6457 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6459 if(!pDevice->InitDone)
6464 if(!(Value32 & PHY_STATUS_LINK_PASS))
6466 LM_PhyTapPowerMgmt(pDevice);
6468 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6469 for(j = 0; j < 1000; j++)
6473 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6474 if(Value32 & PHY_STATUS_LINK_PASS)
6481 if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV)
6483 if(!(Value32 & PHY_STATUS_LINK_PASS) &&
6484 (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS))
6486 LM_ResetPhy(pDevice);
6491 else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
6492 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
6494 /* Bug: 5701 A0, B0 TX CRC workaround. */
6495 LM_WritePhy(pDevice, 0x15, 0x0a75);
6496 LM_WritePhy(pDevice, 0x1c, 0x8c68);
6497 LM_WritePhy(pDevice, 0x1c, 0x8d68);
6498 LM_WritePhy(pDevice, 0x1c, 0x8c68);
6501 /* Acknowledge interrupts. */
6502 LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
6503 LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
6505 /* Configure the interrupt mask. */
6506 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
6508 LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE);
6511 /* Configure PHY led mode. */
6512 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
6513 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
6515 if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_1)
6517 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
6518 BCM540X_EXT_CTRL_LINK3_LED_MODE);
6522 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0);
6526 if (pDevice->PhyFlags & PHY_CAPACITIVE_COUPLING)
6528 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4007);
6529 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &Value32);
6530 if (!(Value32 & BIT_10))
6532 /* set the bit and re-link */
6533 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, Value32 | BIT_10);
6534 return LM_STATUS_LINK_SETTING_MISMATCH;
6538 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
6540 /* Get current link and duplex mode. */
6541 for(j = 0; j < 100; j++)
6543 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6544 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6546 if(Value32 & PHY_STATUS_LINK_PASS)
6553 if(Value32 & PHY_STATUS_LINK_PASS)
6556 /* Determine the current line and duplex settings. */
6557 LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
6558 for(j = 0; j < 2000; j++)
6562 LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
6569 switch(Value32 & BCM540X_AUX_SPEED_MASK)
6571 case BCM540X_AUX_10BASET_HD:
6572 CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
6573 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6576 case BCM540X_AUX_10BASET_FD:
6577 CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
6578 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6581 case BCM540X_AUX_100BASETX_HD:
6582 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6583 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6586 case BCM540X_AUX_100BASETX_FD:
6587 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6588 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6591 case BCM540X_AUX_100BASET_HD:
6592 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6593 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6596 case BCM540X_AUX_100BASET_FD:
6597 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6598 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6603 CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
6604 CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
6608 /* Make sure we are in auto-neg mode. */
6609 for (j = 0; j < 200; j++)
6611 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
6612 if(Value32 && Value32 != 0x7fff)
6618 pDevice->RequestedLineSpeed == LM_LINE_SPEED_10MBPS &&
6619 pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_HALF)
6627 /* Use the current line settings for "auto" mode. */
6628 if(pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
6630 if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)
6632 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6634 /* We may be exiting low power mode and the link is in */
6635 /* 10mb. In this case, we need to restart autoneg. */
6637 if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS)
6639 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6644 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6649 /* Force line settings. */
6650 /* Use the current setting if it matches the user's requested */
6652 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
6653 if((pDevice->LineSpeed == CurrentLineSpeed) &&
6654 (pDevice->DuplexMode == CurrentDuplexMode))
6656 if ((pDevice->DisableAutoNeg &&
6657 !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
6658 (!pDevice->DisableAutoNeg &&
6659 (Value32 & PHY_CTRL_AUTO_NEG_ENABLE)))
6661 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6665 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6670 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6674 /* Save line settings. */
6675 pDevice->LineSpeed = CurrentLineSpeed;
6676 pDevice->DuplexMode = CurrentDuplexMode;
6679 return CurrentLinkStatus;
6680 } /* LM_InitBcm540xPhy */
6682 /******************************************************************************/
6686 /******************************************************************************/
6689 PLM_DEVICE_BLOCK pDevice,
6690 LM_UINT32 LocalPhyAd,
6691 LM_UINT32 RemotePhyAd)
6693 LM_FLOW_CONTROL FlowCap;
6695 /* Resolve flow control. */
6696 FlowCap = LM_FLOW_CONTROL_NONE;
6698 /* See Table 28B-3 of 802.3ab-1999 spec. */
6699 if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE)
6701 if(pDevice->PhyFlags & PHY_IS_FIBER){
6702 LocalPhyAd &= ~(PHY_AN_AD_ASYM_PAUSE |
6703 PHY_AN_AD_PAUSE_CAPABLE);
6704 RemotePhyAd &= ~(PHY_AN_AD_ASYM_PAUSE |
6705 PHY_AN_AD_PAUSE_CAPABLE);
6707 if (LocalPhyAd & PHY_AN_AD_1000XPAUSE)
6708 LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
6709 if (LocalPhyAd & PHY_AN_AD_1000XPSE_ASYM)
6710 LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
6711 if (RemotePhyAd & PHY_AN_AD_1000XPAUSE)
6712 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
6713 if (RemotePhyAd & PHY_AN_AD_1000XPSE_ASYM)
6714 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
6717 if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
6719 if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6721 if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
6723 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
6724 LM_FLOW_CONTROL_RECEIVE_PAUSE;
6726 else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)
6728 FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
6733 if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
6735 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
6736 LM_FLOW_CONTROL_RECEIVE_PAUSE;
6740 else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6742 if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
6743 (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE))
6745 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
6751 FlowCap = pDevice->FlowControlCap;
6754 pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
6756 /* Enable/disable rx PAUSE. */
6757 pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
6758 if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
6759 (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
6760 pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE))
6762 pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
6763 pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
6766 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
6768 /* Enable/disable tx PAUSE. */
6769 pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
6770 if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
6771 (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
6772 pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))
6774 pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
6775 pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
6778 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
6780 return LM_STATUS_SUCCESS;
6784 #ifdef INCLUDE_TBI_SUPPORT
6785 /******************************************************************************/
6789 /******************************************************************************/
6792 PLM_DEVICE_BLOCK pDevice)
6798 Value32 = REG_RD(pDevice, MacCtrl.Status);
6800 /* Reset the SERDES during init and when we have link. */
6801 if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED)
6803 /* Set PLL lock range. */
6804 LM_WritePhy(pDevice, 0x16, 0x8007);
6806 /* Software reset. */
6807 LM_WritePhy(pDevice, 0x00, 0x8000);
6809 /* Wait for reset to complete. */
6810 for(j = 0; j < 500; j++)
6815 /* Config mode; seletct PMA/Ch 1 regs. */
6816 LM_WritePhy(pDevice, 0x10, 0x8411);
6818 /* Enable auto-lock and comdet, select txclk for tx. */
6819 LM_WritePhy(pDevice, 0x11, 0x0a10);
6821 LM_WritePhy(pDevice, 0x18, 0x00a0);
6822 LM_WritePhy(pDevice, 0x16, 0x41ff);
6824 /* Assert and deassert POR. */
6825 LM_WritePhy(pDevice, 0x13, 0x0400);
6827 LM_WritePhy(pDevice, 0x13, 0x0000);
6829 LM_WritePhy(pDevice, 0x11, 0x0a50);
6831 LM_WritePhy(pDevice, 0x11, 0x0a10);
6833 /* Delay for signal to stabilize. */
6834 for(j = 0; j < 15000; j++)
6839 /* Deselect the channel register so we can read the PHY id later. */
6840 LM_WritePhy(pDevice, 0x10, 0x8011);
6843 return LM_STATUS_SUCCESS;
6848 /******************************************************************************/
6852 /******************************************************************************/
6855 PLM_DEVICE_BLOCK pDevice)
6857 LM_STATUS CurrentLinkStatus;
6858 AUTONEG_STATUS AnStatus = 0;
6862 LM_UINT32 MacStatus, RemotePhyAd, LocalPhyAd;
6863 LM_FLOW_CONTROL PreviousFlowControl = pDevice->FlowControl;
6866 if (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE)
6868 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
6869 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
6870 return LM_STATUS_SUCCESS;
6874 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) &&
6875 (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) && pDevice->InitDone)
6877 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6878 if ((MacStatus & (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED |
6879 MAC_STATUS_CFG_CHANGED | MAC_STATUS_RECEIVING_CFG))
6880 == (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED))
6883 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
6884 MAC_STATUS_CFG_CHANGED);
6885 return LM_STATUS_SUCCESS;
6888 pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
6890 /* Initialize the send_config register. */
6891 REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
6893 pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
6894 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
6897 /* Initialize the BCM8002 SERDES PHY. */
6898 switch(pDevice->PhyId & PHY_ID_MASK)
6900 case PHY_BCM8002_PHY_ID:
6901 LM_InitBcm800xPhy(pDevice);
6908 /* Enable link change interrupt. */
6909 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
6911 /* Default to link down. */
6912 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
6914 /* Get the link status. */
6915 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6917 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
6919 LM_UINT32 SgDigCtrl, SgDigStatus;
6920 LM_UINT32 SerdesCfg = 0;
6921 LM_UINT32 ExpectedSgDigCtrl = 0;
6922 LM_UINT32 WorkAround = 0;
6923 LM_UINT32 PortA = 1;
6925 if ((pDevice->ChipRevId != T3_CHIP_ID_5704_A0) &&
6926 (pDevice->ChipRevId != T3_CHIP_ID_5704_A1))
6929 if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID)
6934 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6936 /* Save voltage reg bits & bits 14:0 */
6937 SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) &
6938 (BIT_23 | BIT_22 | BIT_21 | BIT_20 | 0x7fff );
6943 /* preserve the voltage regulator bits */
6944 SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) &
6945 (BIT_23 | BIT_22 | BIT_21 | BIT_20);
6948 SgDigCtrl = REG_RD(pDevice, MacCtrl.SgDigControl);
6949 if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ||
6950 (pDevice->DisableAutoNeg == FALSE))
6953 ExpectedSgDigCtrl = 0x81388400;
6954 LocalPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
6955 if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
6957 ExpectedSgDigCtrl |= BIT_11;
6959 if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6961 ExpectedSgDigCtrl |= BIT_12;
6963 if (SgDigCtrl != ExpectedSgDigCtrl)
6967 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6969 REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011000 | SerdesCfg);
6973 REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011880 | SerdesCfg);
6976 REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl |
6978 REG_RD_BACK(pDevice, MacCtrl.SgDigControl);
6980 REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl);
6981 pDevice->AutoNegJustInited = TRUE;
6983 /* If autoneg is off, you only get SD when link is up */
6984 else if(MacStatus & (MAC_STATUS_PCS_SYNCED |
6985 MAC_STATUS_SIGNAL_DETECTED))
6987 SgDigStatus = REG_RD(pDevice, MacCtrl.SgDigStatus);
6988 if ((SgDigStatus & BIT_1) &&
6989 (MacStatus & MAC_STATUS_PCS_SYNCED))
6991 /* autoneg. completed */
6993 if(SgDigStatus & BIT_19)
6995 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
6998 if(SgDigStatus & BIT_20)
7000 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
7003 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7004 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7005 pDevice->AutoNegJustInited = FALSE;
7007 else if (!(SgDigStatus & BIT_1))
7009 if (pDevice->AutoNegJustInited == TRUE)
7011 /* we may be checking too soon, so check again */
7012 /* at the next poll interval */
7013 pDevice->AutoNegJustInited = FALSE;
7017 /* autoneg. failed */
7022 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7024 REG_WR(pDevice, MacCtrl.SerdesCfg,
7025 0xc010000 | (SerdesCfg & ~0x00001000));
7029 REG_WR(pDevice, MacCtrl.SerdesCfg,
7030 0xc010880 | SerdesCfg);
7035 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7037 REG_WR(pDevice, MacCtrl.SerdesCfg,
7038 0x4010000 | (SerdesCfg & ~0x00001000));
7042 REG_WR(pDevice, MacCtrl.SerdesCfg,
7043 0x4010880 | SerdesCfg);
7047 /* turn off autoneg. to allow traffic to pass */
7048 REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400);
7049 REG_RD_BACK(pDevice, MacCtrl.SgDigControl);
7051 MacStatus = REG_RD(pDevice, MacCtrl.Status);
7052 if ((MacStatus & MAC_STATUS_PCS_SYNCED) && !(MacStatus & MAC_STATUS_RECEIVING_CFG))
7054 LM_SetFlowControl(pDevice, 0, 0);
7055 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7063 if (SgDigCtrl & BIT_31) {
7069 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7071 REG_WR(pDevice, MacCtrl.SerdesCfg,
7072 0xc010000 | (SerdesCfg & ~0x00001000));
7076 REG_WR(pDevice, MacCtrl.SerdesCfg,
7077 0xc010880 | SerdesCfg);
7082 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7084 REG_WR(pDevice, MacCtrl.SerdesCfg,
7085 0x4010000 | (SerdesCfg & ~0x00001000));
7089 REG_WR(pDevice, MacCtrl.SerdesCfg,
7090 0x4010880 | SerdesCfg);
7094 REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400);
7096 if(MacStatus & MAC_STATUS_PCS_SYNCED)
7098 LM_SetFlowControl(pDevice, 0, 0);
7099 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7103 else if(MacStatus & MAC_STATUS_PCS_SYNCED)
7105 if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ||
7106 (pDevice->DisableAutoNeg == FALSE))
7108 /* auto-negotiation mode. */
7109 /* Initialize the autoneg default capaiblities. */
7110 AutonegInit(&pDevice->AnInfo);
7112 /* Set the context pointer to point to the main device structure. */
7113 pDevice->AnInfo.pContext = pDevice;
7115 /* Setup flow control advertisement register. */
7116 Value32 = GetPhyAdFlowCntrlSettings(pDevice);
7117 if(Value32 & PHY_AN_AD_PAUSE_CAPABLE)
7119 pDevice->AnInfo.mr_adv_sym_pause = 1;
7123 pDevice->AnInfo.mr_adv_sym_pause = 0;
7126 if(Value32 & PHY_AN_AD_ASYM_PAUSE)
7128 pDevice->AnInfo.mr_adv_asym_pause = 1;
7132 pDevice->AnInfo.mr_adv_asym_pause = 0;
7135 /* Try to autoneg up to six times. */
7136 if (pDevice->IgnoreTbiLinkChange)
7144 for (j = 0; j < Cnt; j++)
7146 REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
7148 Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
7149 REG_WR(pDevice, MacCtrl.Mode, Value32);
7150 REG_RD_BACK(pDevice, MacCtrl.Mode);
7153 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7154 MAC_MODE_SEND_CONFIGS);
7155 REG_RD_BACK(pDevice, MacCtrl.Mode);
7159 pDevice->AnInfo.State = AN_STATE_UNKNOWN;
7160 pDevice->AnInfo.CurrentTime_us = 0;
7162 REG_WR(pDevice, Grc.Timer, 0);
7163 for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) &&
7166 AnStatus = Autoneg8023z(&pDevice->AnInfo);
7168 if((AnStatus == AUTONEG_STATUS_DONE) ||
7169 (AnStatus == AUTONEG_STATUS_FAILED))
7174 pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer);
7177 if((AnStatus == AUTONEG_STATUS_DONE) ||
7178 (AnStatus == AUTONEG_STATUS_FAILED))
7184 if (!(REG_RD(pDevice, MacCtrl.Status) &
7185 MAC_STATUS_PCS_SYNCED)) {
7191 /* Stop sending configs. */
7192 MM_AnTxIdle(&pDevice->AnInfo);
7194 /* Resolve flow control settings. */
7195 if((AnStatus == AUTONEG_STATUS_DONE) &&
7196 pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok &&
7197 pDevice->AnInfo.mr_lp_adv_full_duplex)
7199 LM_UINT32 RemotePhyAd;
7200 LM_UINT32 LocalPhyAd;
7203 if(pDevice->AnInfo.mr_adv_sym_pause)
7205 LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
7208 if(pDevice->AnInfo.mr_adv_asym_pause)
7210 LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
7214 if(pDevice->AnInfo.mr_lp_adv_sym_pause)
7216 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
7219 if(pDevice->AnInfo.mr_lp_adv_asym_pause)
7221 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
7224 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7226 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7230 LM_SetFlowControl(pDevice, 0, 0);
7232 for (j = 0; j < 30; j++)
7235 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7236 MAC_STATUS_CFG_CHANGED);
7237 REG_RD_BACK(pDevice, MacCtrl.Status);
7239 if ((REG_RD(pDevice, MacCtrl.Status) &
7240 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
7243 if (pDevice->TbiFlags & TBI_POLLING_FLAGS)
7245 Value32 = REG_RD(pDevice, MacCtrl.Status);
7246 if (Value32 & MAC_STATUS_RECEIVING_CFG)
7248 pDevice->IgnoreTbiLinkChange = TRUE;
7250 else if (pDevice->TbiFlags & TBI_POLLING_INTR_FLAG)
7252 pDevice->IgnoreTbiLinkChange = FALSE;
7255 Value32 = REG_RD(pDevice, MacCtrl.Status);
7256 if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
7257 (Value32 & MAC_STATUS_PCS_SYNCED) &&
7258 ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0))
7260 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7265 /* We are forcing line speed. */
7266 pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
7267 LM_SetFlowControl(pDevice, 0, 0);
7269 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7270 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7271 MAC_MODE_SEND_CONFIGS);
7274 /* Set the link polarity bit. */
7275 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7276 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7278 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7279 (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7281 for (j = 0; j < 100; j++)
7283 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7284 MAC_STATUS_CFG_CHANGED);
7285 REG_RD_BACK(pDevice, MacCtrl.Status);
7287 if ((REG_RD(pDevice, MacCtrl.Status) &
7288 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
7292 Value32 = REG_RD(pDevice, MacCtrl.Status);
7293 if((Value32 & MAC_STATUS_PCS_SYNCED) == 0)
7295 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7296 if (pDevice->DisableAutoNeg == FALSE)
7298 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7299 MAC_MODE_SEND_CONFIGS);
7300 REG_RD_BACK(pDevice, MacCtrl.Mode);
7302 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7306 /* Initialize the current link status. */
7307 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7309 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
7310 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
7311 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl |
7312 LED_CTRL_OVERRIDE_LINK_LED |
7313 LED_CTRL_1000MBPS_LED_ON);
7317 pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
7318 pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
7319 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl |
7320 LED_CTRL_OVERRIDE_LINK_LED |
7321 LED_CTRL_OVERRIDE_TRAFFIC_LED);
7324 /* Indicate link status. */
7325 if ((pDevice->LinkStatus != CurrentLinkStatus) ||
7326 ((CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
7327 (PreviousFlowControl != pDevice->FlowControl)))
7329 pDevice->LinkStatus = CurrentLinkStatus;
7330 MM_IndicateStatus(pDevice, CurrentLinkStatus);
7333 return LM_STATUS_SUCCESS;
7335 #endif /* INCLUDE_TBI_SUPPORT */
7338 /******************************************************************************/
7342 /******************************************************************************/
7345 PLM_DEVICE_BLOCK pDevice)
7347 LM_STATUS CurrentLinkStatus;
7350 /* Assume there is not link first. */
7351 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7353 /* Disable phy link change attention. */
7354 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7356 /* Clear link change attention. */
7357 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7358 MAC_STATUS_CFG_CHANGED | MAC_STATUS_MI_COMPLETION |
7359 MAC_STATUS_LINK_STATE_CHANGED);
7361 /* Disable auto-polling for the moment. */
7362 pDevice->MiMode = 0xc0000;
7363 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
7364 REG_RD_BACK(pDevice, MacCtrl.MiMode);
7367 /* Determine the requested line speed and duplex. */
7368 pDevice->OldLineSpeed = pDevice->LineSpeed;
7369 pDevice->LineSpeed = pDevice->RequestedLineSpeed;
7370 pDevice->DuplexMode = pDevice->RequestedDuplexMode;
7372 /* Set the phy to loopback mode. */
7373 if ((pDevice->LoopBackMode == LM_PHY_LOOP_BACK_MODE) ||
7374 (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE))
7376 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7377 if(!(Value32 & PHY_CTRL_LOOPBACK_MODE) &&
7378 (pDevice->LoopBackMode == LM_PHY_LOOP_BACK_MODE))
7380 /* Disable link change and PHY interrupts. */
7381 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7383 /* Clear link change attention. */
7384 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7385 MAC_STATUS_CFG_CHANGED);
7387 LM_WritePhy(pDevice, PHY_CTRL_REG, 0x4140);
7390 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7391 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
7392 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 ||
7393 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
7394 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705 ||
7395 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 &&
7396 (pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID))
7398 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7401 /* Prevent the interrupt handling from being called. */
7402 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7403 (pDevice->pStatusBlkVirt->Status &
7404 ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7406 /* GMII interface. */
7407 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
7408 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7409 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7410 REG_RD_BACK(pDevice, MacCtrl.Mode);
7413 /* Configure PHY led mode. */
7414 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
7415 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
7417 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
7418 BCM540X_EXT_CTRL_LINK3_LED_MODE);
7422 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
7426 while (REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)
7434 Value32 = DMA_WRITE_MODE_ENABLE |
7435 DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
7436 DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
7437 DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
7438 DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
7439 DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
7440 DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
7441 DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
7442 DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
7443 REG_WR(pDevice, DmaWrite.Mode, Value32);
7447 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7448 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
7450 return LM_STATUS_SUCCESS;
7453 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7454 if(Value32 & PHY_CTRL_LOOPBACK_MODE)
7456 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7458 /* Re-enable link change interrupt. This was disabled when we */
7459 /* enter loopback mode. */
7460 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
7462 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
7466 REG_WR(pDevice, MacCtrl.MacEvent,
7467 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7472 /* Initialize the phy chip. */
7473 CurrentLinkStatus = LM_InitBcm540xPhy(pDevice);
7476 if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH)
7478 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7481 /* Setup flow control. */
7482 pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
7483 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7485 LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
7487 FlowCap = LM_FLOW_CONTROL_NONE;
7489 if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL)
7491 if(pDevice->DisableAutoNeg == FALSE ||
7492 pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
7494 LM_UINT32 ExpectedPhyAd;
7495 LM_UINT32 LocalPhyAd;
7496 LM_UINT32 RemotePhyAd;
7498 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd);
7499 pDevice->advertising = LocalPhyAd;
7500 LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE);
7502 ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
7504 if(LocalPhyAd != ExpectedPhyAd)
7506 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7510 LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG,
7513 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7518 pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
7519 LM_SetFlowControl(pDevice, 0, 0);
7524 if(CurrentLinkStatus == LM_STATUS_LINK_DOWN)
7526 LM_ForceAutoNeg(pDevice);
7528 /* If we force line speed, we make get link right away. */
7529 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
7530 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
7531 if(Value32 & PHY_STATUS_LINK_PASS)
7533 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7537 /* GMII interface. */
7538 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
7539 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7541 if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
7542 pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7544 pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
7548 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7552 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7555 /* Set the MAC to operate in the appropriate duplex mode. */
7556 pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
7557 if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)
7559 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
7562 /* Set the link polarity bit. */
7563 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7564 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
7566 if((pDevice->LedCtrl == LED_CTRL_PHY_MODE_2) ||
7567 (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
7568 pDevice->LineSpeed == LM_LINE_SPEED_10MBPS))
7570 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7575 if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7577 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7581 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7583 /* Enable auto polling. */
7584 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
7586 pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
7587 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
7589 /* if using MAC led mode and not using auto polling, need to configure */
7590 /* mi status register */
7591 else if ((pDevice->LedCtrl &
7592 (LED_CTRL_PHY_MODE_1 | LED_CTRL_PHY_MODE_2)) == 0)
7594 if (CurrentLinkStatus != LM_STATUS_LINK_ACTIVE)
7596 REG_WR(pDevice, MacCtrl.MiStatus, 0);
7598 else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7600 REG_WR(pDevice, MacCtrl.MiStatus,
7601 MI_STATUS_ENABLE_LINK_STATUS_ATTN | MI_STATUS_10MBPS);
7605 REG_WR(pDevice, MacCtrl.MiStatus,
7606 MI_STATUS_ENABLE_LINK_STATUS_ATTN);
7610 /* Enable phy link change attention. */
7611 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
7613 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
7617 REG_WR(pDevice, MacCtrl.MacEvent,
7618 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7620 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
7621 (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
7622 (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
7623 (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
7624 (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
7625 !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)))
7628 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7629 MAC_STATUS_CFG_CHANGED);
7630 MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,
7631 T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
7634 /* Indicate link status. */
7635 if (pDevice->LinkStatus != CurrentLinkStatus) {
7636 pDevice->LinkStatus = CurrentLinkStatus;
7637 MM_IndicateStatus(pDevice, CurrentLinkStatus);
7640 return LM_STATUS_SUCCESS;
7641 } /* LM_SetupCopperPhy */
7645 LM_5714_FamForceFiber(
7646 PLM_DEVICE_BLOCK pDevice)
7649 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7651 new_bmcr = Creg & ~PHY_CTRL_AUTO_NEG_ENABLE;
7653 if ( pDevice->RequestedDuplexMode == 0 ||
7654 pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_FULL){
7656 new_bmcr |= PHY_CTRL_FULL_DUPLEX_MODE;
7659 if(Creg == new_bmcr)
7662 new_bmcr |= PHY_CTRL_SPEED_SELECT_1000MBPS; /* Reserve bit */
7664 /* Force a linkdown */
7665 LM_WritePhy(pDevice, PHY_AN_AD_REG, 0);
7666 LM_WritePhy(pDevice, PHY_CTRL_REG, new_bmcr |
7667 PHY_CTRL_RESTART_AUTO_NEG |
7668 PHY_CTRL_AUTO_NEG_ENABLE |
7669 PHY_CTRL_SPEED_SELECT_1000MBPS);
7673 LM_WritePhy(pDevice, PHY_CTRL_REG, new_bmcr);
7678 }/* LM_5714_FamForceFiber */
7682 LM_5714_FamGoFiberAutoNeg(
7683 PLM_DEVICE_BLOCK pDevice)
7687 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7688 LM_ReadPhy(pDevice,PHY_AN_AD_REG, &adv);
7690 new = adv & ~( PHY_AN_AD_1000XFULL |
7691 PHY_AN_AD_1000XHALF |
7692 PHY_AN_AD_1000XPAUSE |
7693 PHY_AN_AD_1000XPSE_ASYM |
7696 new |= PHY_AN_AD_1000XPAUSE;
7698 new |= PHY_AN_AD_1000XFULL;
7699 new |= PHY_AN_AD_1000XHALF;
7701 if ((new != adv) || !(Creg & PHY_CTRL_AUTO_NEG_ENABLE)){
7702 LM_WritePhy(pDevice, PHY_AN_AD_REG, new);
7704 pDevice->AutoNegJustInited=1;
7705 LM_WritePhy(pDevice, PHY_CTRL_REG, (Creg |
7706 PHY_CTRL_RESTART_AUTO_NEG |
7707 PHY_CTRL_SPEED_SELECT_1000MBPS |
7708 PHY_CTRL_AUTO_NEG_ENABLE) );
7712 } /* 5714_FamGoFiberAutoNeg */
7716 LM_5714_FamDoFiberLoopback(PLM_DEVICE_BLOCK pDevice)
7720 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7722 if( !(Value32 & PHY_CTRL_LOOPBACK_MODE) )
7724 LM_WritePhy(pDevice, PHY_CTRL_REG, 0x4140);
7726 /* Prevent the interrupt handling from being called. */
7727 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7728 (pDevice->pStatusBlkVirt->Status &
7729 ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7732 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7733 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
7737 }/* 5714_FamDoFiberLoopBack */
7740 /******************************************************************************/
7744 /******************************************************************************/
7747 LM_SetupNewFiberPhy(
7748 PLM_DEVICE_BLOCK pDevice)
7750 LM_STATUS LmStatus = LM_STATUS_SUCCESS;
7753 rsav = pDevice->LinkStatus;
7755 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7756 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7759 /* Disable phy link change attention. */
7760 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7762 /* Clear link change attention. */
7763 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7764 MAC_STATUS_CFG_CHANGED | MAC_STATUS_MI_COMPLETION |
7765 MAC_STATUS_LINK_STATE_CHANGED);
7768 if( (pDevice->PhyFlags & PHY_FIBER_FALLBACK) &&
7769 ( pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ){
7772 }else if ( pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE){
7774 LM_5714_FamDoFiberLoopback(pDevice);
7775 goto fiberloopbackreturn;
7777 } else if( pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) {
7779 LM_5714_FamGoFiberAutoNeg(pDevice);
7784 LM_5714_FamForceFiber(pDevice);
7787 /* 5714/15 Serdes link status is valid only in reg 0x460 */
7788 /* ecd 13216 workaround for serdes */
7789 Sreg = REG_RD(pDevice, MacCtrl.TxStatus);
7791 if(Sreg & TX_STATUS_LINK_UP){
7793 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7794 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
7796 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7798 if(Creg & PHY_CTRL_FULL_DUPLEX_MODE) {
7799 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
7801 pDevice->DuplexMode = LM_DUPLEX_MODE_HALF;
7802 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
7803 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7806 if(Creg & PHY_CTRL_AUTO_NEG_ENABLE){
7809 LM_ReadPhy(pDevice,PHY_AN_AD_REG, &ours);
7810 LM_ReadPhy(pDevice,PHY_LINK_PARTNER_ABILITY_REG, &partner);
7811 LM_SetFlowControl(pDevice, ours, partner);
7815 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
7816 pDevice->LineSpeed = 0;
7819 if(rsav != pDevice->LinkStatus)
7820 MM_IndicateStatus(pDevice, pDevice->LinkStatus);
7822 fiberloopbackreturn:
7823 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7824 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7826 /* Enable link change interrupt. */
7827 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7830 } /* Setup New phy */
7833 LM_5714_FamFiberCheckLink(
7834 PLM_DEVICE_BLOCK pDevice)
7837 if(pDevice->AutoNegJustInited){
7838 pDevice->AutoNegJustInited=0;
7842 if ((pDevice->LinkStatus != LM_STATUS_LINK_ACTIVE) &&
7843 (pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) &&
7844 !(pDevice->PhyFlags & PHY_FIBER_FALLBACK)){
7847 LM_ReadPhy(pDevice, PHY_CTRL_REG, &bmcr);
7848 if (bmcr & PHY_CTRL_AUTO_NEG_ENABLE) {
7851 LM_WritePhy(pDevice, 0x1c, 0x7c00);
7852 LM_ReadPhy(pDevice, 0x1c, &phy1);
7854 LM_WritePhy(pDevice, 0x17, 0x0f01);
7855 LM_ReadPhy(pDevice, 0x15, &phy2);
7856 LM_ReadPhy(pDevice, 0x15, &phy2);
7858 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
7860 /* We have signal detect and not receiving
7864 pDevice->PhyFlags |= PHY_FIBER_FALLBACK;
7865 LM_5714_FamForceFiber(pDevice);
7869 else if ( (pDevice->PhyFlags & PHY_FIBER_FALLBACK) &&
7870 (pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)) {
7873 LM_WritePhy(pDevice, 0x17, 0x0f01);
7874 LM_ReadPhy(pDevice, 0x15, &phy2);
7876 /* Receiving configs. */
7878 pDevice->PhyFlags &= ~PHY_FIBER_FALLBACK;
7879 LM_5714_FamGoFiberAutoNeg(pDevice);
7883 } /* LM_5714_FamFiberCheckLink */
7886 /******************************************************************************/
7890 /******************************************************************************/
7893 PLM_DEVICE_BLOCK pDevice)
7898 if(pDevice->PhyFlags & PHY_IS_FIBER)
7900 LmStatus = LM_SetupNewFiberPhy(pDevice);
7902 #ifdef INCLUDE_TBI_SUPPORT
7903 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
7905 LmStatus = LM_SetupFiberPhy(pDevice);
7908 #endif /* INCLUDE_TBI_SUPPORT */
7910 LmStatus = LM_SetupCopperPhy(pDevice);
7912 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
7914 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
7916 Value32 = REG_RD(pDevice, PciCfg.PciState);
7917 REG_WR(pDevice, PciCfg.PciState,
7918 Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
7921 if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
7922 (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF))
7924 REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff);
7928 REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
7930 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
7932 if (pDevice->LinkStatus == LM_STATUS_LINK_DOWN)
7934 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, 0);
7938 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
7939 pDevice->StatsCoalescingTicks);
7947 /* test data pattern */
7948 static LM_UINT32 pattern[4][6] = {
7949 /* For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6)
7950 For 5705 , each DFE TAP has 19-bits (low word 15, hi word 4)
7951 For simplicity, we check only 19-bits, so we don't have to
7952 distinguish which chip it is.
7953 the LO word contains 15 bits, make sure pattern data is < 0x7fff
7954 the HI word contains 6 bits, make sure pattern data is < 0x003f */
7955 {0x00005555, 0x00000005, /* ch0, TAP 0, LO/HI pattern */
7956 0x00002aaa, 0x0000000a, /* ch0, TAP 1, LO/HI pattern */
7957 0x00003456, 0x00000003}, /* ch0, TAP 2, LO/HI pattern */
7959 {0x00002aaa, 0x0000000a, /* ch1, TAP 0, LO/HI pattern */
7960 0x00003333, 0x00000003, /* ch1, TAP 1, LO/HI pattern */
7961 0x0000789a, 0x00000005}, /* ch1, TAP 2, LO/HI pattern */
7963 {0x00005a5a, 0x00000005, /* ch2, TAP 0, LO/HI pattern */
7964 0x00002a6a, 0x0000000a, /* ch2, TAP 1, LO/HI pattern */
7965 0x00001bcd, 0x00000003}, /* ch2, TAP 2, LO/HI pattern */
7967 {0x00002a5a, 0x0000000a, /* ch3, TAP 0, LO/HI pattern */
7968 0x000033c3, 0x00000003, /* ch3, TAP 1, LO/HI pattern */
7969 0x00002ef1, 0x00000005}, /* ch3, TAP 2, LO/HI pattern */
7972 /********************************************************/
7973 /* Routine to wait for PHY Macro Command to complete */
7975 /* If PHY's Macro operation keeps stay busy, nothing we */
7976 /* can do anyway. The timeout is there so we won't */
7977 /* stay in this routine indefinitly. */
7978 /********************************************************/
7979 static LM_UINT32 LM_wait_macro_done(LM_DEVICE_BLOCK *pDevice);
7982 LM_wait_macro_done(LM_DEVICE_BLOCK *pDevice)
7990 /* make sure the MACRO operation is complete */
7991 LM_ReadPhy(pDevice, 0x16, &val32);
7992 if ((val32 & 0x1000) == 0) break;
7995 return( timeout > 0 );
7998 /********************************************************/
7999 /* This routine resets the PHY on following chips: */
8000 /* 5703, 04, CIOB-E and 5705 */
8002 /* This routine will issue PHY_RESET and check if */
8003 /* the reset is sucessful. If not, another PHY RESET */
8004 /* will be issued, until max "retry" reaches */
8007 /* pDevice - device's context */
8008 /* retry - number of retries */
8009 /* reset - TRUE=will cause a PHY reset initially */
8010 /* FALSE = will not issue a PHY reset */
8011 /* unless TAP lockup detected */
8014 /* TRUE - PHY Reset is done sucessfully */
8015 /* FALSE - PHY Reset had failed, after "retry" */
8019 /* void LM_wait_macro_done() */
8023 /* a. Before calling this routine, caller must */
8024 /* determine if the chip is a 5702/03/04 or */
8025 /* CIOB-E, and only call this routine if the */
8026 /* is one of these. */
8027 /* or its derivatives. */
8028 /* b. Instead of using MII register write to reset */
8029 /* the PHY, call this routine instead */
8030 /* c. Upon return from this routine, check return */
8031 /* value (TRUE/FALSE) to determine if PHY reset */
8032 /* is successful of not and "optionally" take */
8033 /* appropriate action (such as: event log) */
8034 /* d. Regardless of the return TRUE or FALSE, */
8035 /* proceed with PHY setup as you normally would */
8036 /* after a PHY_RESET. */
8037 /* e. It is recommended that the caller will give */
8038 /* 10 "retry", however, caller can change to a */
8039 /* different number, depending on you code. */
8041 /********************************************************/
8042 LM_STATUS LM_ResetPhy_5703_4_5(LM_DEVICE_BLOCK *pDevice, int retry, int reset);
8045 LM_ResetPhy_5703_4_5(LM_DEVICE_BLOCK *pDevice, int retry, int reset)
8047 LM_UINT32 val32, save9;
8048 LM_UINT32 dataLo, dataHi;
8050 int reset_success = LM_STATUS_FAILURE;
8053 /* to actually do a PHY_RESET or not is dictated by the caller */
8054 force_reset = reset;
8056 while (retry-- && (reset_success != LM_STATUS_SUCCESS))
8060 /* issue a phy reset, and wait for reset to complete */
8061 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
8062 for(i = 0; i < 100; i++)
8066 LM_ReadPhy(pDevice, PHY_CTRL_REG, &val32);
8067 if(val32 && !(val32 & PHY_CTRL_PHY_RESET))
8074 /* no more phy reset unless lockup detected */
8075 force_reset = FALSE;
8078 /* assuming reset is successful first */
8079 reset_success = LM_STATUS_SUCCESS;
8081 /* now go check the DFE TAPs to see if locked up, but
8082 first, we need to set up PHY so we can read DFE TAPs */
8084 /* Disable Transmitter and Interrupt, while we play with
8085 the PHY registers, so the link partner won't see any
8086 strange data and the Driver won't see any interrupts. */
8087 LM_ReadPhy(pDevice, 0x10, &val32);
8088 LM_WritePhy(pDevice, 0x10, val32 | 0x3000);
8090 /* Setup Full-Duplex, 1000 mbps */
8091 LM_WritePhy(pDevice, 0x0, 0x0140);
8093 /* Set to Master mode */
8094 LM_ReadPhy(pDevice, 0x9, &save9);
8095 LM_WritePhy(pDevice, 0x9, 0x1800);
8097 /* Enable SM_DSP_CLOCK & 6dB */
8098 LM_WritePhy(pDevice, 0x18, 0x0c00);
8100 /* blocks the PHY control access */
8101 LM_WritePhy(pDevice, 0x17, 0x8005);
8102 LM_WritePhy(pDevice, 0x15, 0x0800);
8104 /* check TAPs for all 4 channels, as soon
8105 as we see a lockup we'll stop checking */
8106 for (channel=0; (channel<4) && (reset_success == LM_STATUS_SUCCESS);
8109 /* select channel and set TAP index to 0 */
8110 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8111 /* freeze filter again just to be safe */
8112 LM_WritePhy(pDevice, 0x16, 0x0002);
8114 /* write fixed pattern to the RAM, 3 TAPs for
8115 each channel, each TAP have 2 WORDs (LO/HI) */
8117 LM_WritePhy(pDevice, 0x15, pattern[channel][i]);
8119 /* Activate PHY's Macro operation to write DFE TAP from RAM,
8120 and wait for Macro to complete */
8121 LM_WritePhy(pDevice, 0x16, 0x0202);
8122 if (!LM_wait_macro_done(pDevice))
8124 reset_success = LM_STATUS_FAILURE;
8129 /* --- done with write phase, now begin read phase --- */
8131 /* select channel and set TAP index to 0 */
8132 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8134 /* Active PHY's Macro operation to load DFE TAP to RAM,
8135 and wait for Macro to complete */
8136 LM_WritePhy(pDevice, 0x16, 0x0082);
8137 if (!LM_wait_macro_done(pDevice))
8139 reset_success = LM_STATUS_FAILURE;
8144 /* enable "pre-fetch" */
8145 LM_WritePhy(pDevice, 0x16, 0x0802);
8146 if (!LM_wait_macro_done(pDevice))
8148 reset_success = LM_STATUS_FAILURE;
8153 /* read back the TAP values.
8154 3 TAPs for each channel, each TAP have 2 WORDs (LO/HI) */
8155 for (i=0; i<6; i+=2)
8157 /* read Lo/Hi then wait for 'done' is faster */
8158 LM_ReadPhy(pDevice, 0x15, &dataLo);
8159 LM_ReadPhy(pDevice, 0x15, &dataHi);
8160 if (!LM_wait_macro_done(pDevice))
8162 reset_success = LM_STATUS_FAILURE;
8167 /* For 5703/04, each DFE TAP has 21-bits (low word 15,
8168 * hi word 6) For 5705, each DFE TAP pas 19-bits (low word 15,
8169 * hi word 4) For simplicity, we check only 19-bits, so we
8170 * don't have to distinguish which chip it is. */
8174 /* check if what we wrote is what we read back */
8175 if ( (dataLo != pattern[channel][i]) || (dataHi != pattern[channel][i+1]) )
8177 /* if failed, then the PHY is locked up,
8178 we need to do PHY reset again */
8179 reset_success = LM_STATUS_FAILURE;
8181 /* 04/25/2003. sb. do these writes before issueing a reset. */
8182 /* these steps will reduce the chance of back-to-back
8183 * phy lockup after reset */
8184 LM_WritePhy(pDevice, 0x17, 0x000B);
8185 LM_WritePhy(pDevice, 0x15, 0x4001);
8186 LM_WritePhy(pDevice, 0x15, 0x4005);
8193 /* restore dfe coeff back to zeros */
8194 for (channel=0; channel<4 ; channel++)
8196 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8197 LM_WritePhy(pDevice, 0x16, 0x0002);
8199 LM_WritePhy(pDevice, 0x15, 0x0000);
8200 LM_WritePhy(pDevice, 0x16, 0x0202);
8201 if (!LM_wait_macro_done(pDevice))
8203 reset_success = LM_STATUS_FAILURE;
8208 /* remove block phy control */
8209 LM_WritePhy(pDevice, 0x17, 0x8005);
8210 LM_WritePhy(pDevice, 0x15, 0x0000);
8212 /* unfreeze DFE TAP filter for all channels */
8213 LM_WritePhy(pDevice, 0x17, 0x8200);
8214 LM_WritePhy(pDevice, 0x16, 0x0000);
8216 /* Restore PHY back to operating state */
8217 LM_WritePhy(pDevice, 0x18, 0x0400);
8219 /* Restore register 9 */
8220 LM_WritePhy(pDevice, 0x9, save9);
8222 /* enable transmitter and interrupt */
8223 LM_ReadPhy(pDevice, 0x10, &val32);
8224 LM_WritePhy(pDevice, 0x10, (val32 & ~0x3000));
8226 return reset_success;
8230 LM_ResetPhy(LM_DEVICE_BLOCK *pDevice)
8235 if (pDevice->PhyFlags & PHY_CHECK_TAPS_AFTER_RESET)
8237 LM_ResetPhy_5703_4_5(pDevice, 5, 1);
8242 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
8244 if( pDevice->PhyFlags & PHY_IS_FIBER )
8247 for(j = 0; j < wait_val; j++)
8251 LM_ReadPhy(pDevice, PHY_CTRL_REG, &miireg);
8252 if(miireg && !(miireg & PHY_CTRL_PHY_RESET))
8259 LM_PhyTapPowerMgmt(pDevice);
8261 if ( (pDevice->PhyFlags & PHY_ADC_FIX) &&
8262 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8264 LM_WritePhy(pDevice, 0x18, 0x0c00);
8265 LM_WritePhy(pDevice, 0x17, 0x201f);
8266 LM_WritePhy(pDevice, 0x15, 0x2aaa);
8267 LM_WritePhy(pDevice, 0x17, 0x000a);
8268 LM_WritePhy(pDevice, 0x15, 0x0323);
8269 LM_WritePhy(pDevice, 0x18, 0x0400);
8271 if ( (pDevice->PhyFlags & PHY_5705_5750_FIX) &&
8272 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8274 LM_WritePhy(pDevice, 0x18, 0x0c00);
8275 LM_WritePhy(pDevice, 0x17, 0x000a);
8276 LM_WritePhy(pDevice, 0x15, 0x310b);
8277 LM_WritePhy(pDevice, 0x17, 0x201f);
8278 LM_WritePhy(pDevice, 0x15, 0x9506);
8279 LM_WritePhy(pDevice, 0x17, 0x401f);
8280 LM_WritePhy(pDevice, 0x15, 0x14e2);
8281 LM_WritePhy(pDevice, 0x18, 0x0400);
8283 if ( (pDevice->PhyFlags & PHY_5704_A0_FIX) &&
8284 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8286 LM_WritePhy(pDevice, 0x1c, 0x8d68);
8287 LM_WritePhy(pDevice, 0x1c, 0x8d68);
8289 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
8291 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &miireg);
8292 miireg |= 1; /* set tx elastic fifo */
8293 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, miireg);
8295 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
8297 else if (pDevice->Flags & JUMBO_CAPABLE_FLAG)
8299 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
8300 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &miireg);
8301 miireg |= 0x4000; /* set rx extended packet length */
8302 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, miireg);
8304 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &miireg);
8305 miireg |= 1; /* set tx elastic fifo */
8306 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, miireg);
8310 LM_SetEthWireSpeed(pDevice);
8311 pDevice->PhyFlags &= ~PHY_FIBER_FALLBACK;
8315 LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice)
8319 if( pDevice->PhyFlags & PHY_IS_FIBER)
8322 /* Enable Ethernet@WireSpeed. */
8323 if (pDevice->PhyFlags & PHY_ETHERNET_WIRESPEED)
8325 LM_WritePhy(pDevice, 0x18, 0x7007);
8326 LM_ReadPhy(pDevice, 0x18, &Value32);
8327 LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4);
8332 LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice)
8336 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &miireg);
8337 pDevice->advertising = miireg;
8338 if ((miireg & PHY_AN_AD_ALL_SPEEDS) != PHY_AN_AD_ALL_SPEEDS)
8340 return LM_STATUS_FAILURE;
8343 LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &miireg);
8344 pDevice->advertising1000 = miireg;
8346 if (!(pDevice->PhyFlags & PHY_NO_GIGABIT))
8348 if ((miireg & BCM540X_AN_AD_ALL_1G_SPEEDS) !=
8349 BCM540X_AN_AD_ALL_1G_SPEEDS)
8351 return LM_STATUS_FAILURE;
8357 return LM_STATUS_FAILURE;
8360 return LM_STATUS_SUCCESS;
8363 /******************************************************************************/
8367 /******************************************************************************/
8370 PLM_DEVICE_BLOCK pDevice,
8372 PLM_UINT32 pData32) {
8376 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8378 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
8379 ~MI_MODE_AUTO_POLLING_ENABLE);
8380 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8384 Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
8385 ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
8386 MI_COM_CMD_READ | MI_COM_START;
8388 REG_WR(pDevice, MacCtrl.MiCom, Value32);
8390 for(j = 0; j < 200; j++)
8394 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8396 if(!(Value32 & MI_COM_BUSY))
8399 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8400 Value32 &= MI_COM_PHY_DATA_MASK;
8405 if(Value32 & MI_COM_BUSY)
8412 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8414 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
8415 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8422 /******************************************************************************/
8426 /******************************************************************************/
8429 PLM_DEVICE_BLOCK pDevice,
8435 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8437 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
8438 ~MI_MODE_AUTO_POLLING_ENABLE);
8439 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8443 Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
8444 ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
8445 (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START;
8447 REG_WR(pDevice, MacCtrl.MiCom, Value32);
8449 for(j = 0; j < 200; j++)
8453 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8455 if(!(Value32 & MI_COM_BUSY))
8462 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8464 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
8465 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8471 LM_GetPhyId(LM_DEVICE_BLOCK *pDevice)
8475 LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32);
8476 pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
8478 LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32);
8479 pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
8480 (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
8485 LM_EnableMacLoopBack(PLM_DEVICE_BLOCK pDevice)
8487 pDevice->LoopBackMode = LM_MAC_LOOP_BACK_MODE;
8488 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
8489 pDevice->MacMode |= (MAC_MODE_PORT_INTERNAL_LOOPBACK |
8490 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII);
8491 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
8493 LM_SetupPhy(pDevice);
8494 return LM_STATUS_SUCCESS;
8498 LM_DisableMacLoopBack(PLM_DEVICE_BLOCK pDevice)
8500 pDevice->LoopBackMode = 0;
8502 pDevice->MacMode &= ~(MAC_MODE_PORT_INTERNAL_LOOPBACK |
8503 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_MASK);
8504 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
8506 if(pDevice->PhyFlags & PHY_IS_FIBER)
8507 LM_ResetPhy(pDevice);
8509 LM_SetupPhy(pDevice);
8510 return LM_STATUS_SUCCESS;
8514 LM_EnablePhyLoopBack(PLM_DEVICE_BLOCK pDevice)
8516 pDevice->LoopBackMode = LM_PHY_LOOP_BACK_MODE;
8517 LM_SetupPhy(pDevice);
8518 return LM_STATUS_SUCCESS;
8522 LM_DisablePhyLoopBack(PLM_DEVICE_BLOCK pDevice)
8524 pDevice->LoopBackMode = 0;
8525 LM_SetupPhy(pDevice);
8526 return LM_STATUS_SUCCESS;
8530 LM_EnableExtLoopBack(PLM_DEVICE_BLOCK pDevice, LM_LINE_SPEED LineSpeed)
8532 pDevice->LoopBackMode = LM_EXT_LOOP_BACK_MODE;
8534 pDevice->SavedDisableAutoNeg = pDevice->DisableAutoNeg;
8535 pDevice->SavedRequestedLineSpeed = pDevice->RequestedLineSpeed;
8536 pDevice->SavedRequestedDuplexMode = pDevice->RequestedDuplexMode;
8538 pDevice->DisableAutoNeg = TRUE;
8539 pDevice->RequestedLineSpeed = LineSpeed;
8540 pDevice->RequestedDuplexMode = LM_DUPLEX_MODE_FULL;
8541 LM_SetupPhy(pDevice);
8542 return LM_STATUS_SUCCESS;
8546 LM_DisableExtLoopBack(PLM_DEVICE_BLOCK pDevice)
8548 pDevice->LoopBackMode = 0;
8550 pDevice->DisableAutoNeg = pDevice->SavedDisableAutoNeg;
8551 pDevice->RequestedLineSpeed = pDevice->SavedRequestedLineSpeed;
8552 pDevice->RequestedDuplexMode = pDevice->SavedRequestedDuplexMode;
8554 LM_SetupPhy(pDevice);
8555 return LM_STATUS_SUCCESS;
8558 /******************************************************************************/
8562 /******************************************************************************/
8565 PLM_DEVICE_BLOCK pDevice,
8566 LM_POWER_STATE PowerLevel)
8569 LM_UINT32 PmeSupport;
8570 PLM_DEVICE_BLOCK pDevice2 = 0;
8576 /* make sureindirect accesses are enabled*/
8577 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
8579 /* Clear the PME_ASSERT bit and the power state bits. Also enable */
8581 MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
8583 PmCtrl |= T3_PM_PME_ASSERTED;
8584 PmCtrl &= ~T3_PM_POWER_STATE_MASK;
8586 /* Set the appropriate power state. */
8587 if(PowerLevel == LM_POWER_STATE_D0)
8589 /* Bring the card out of low power mode. */
8590 PmCtrl |= T3_PM_POWER_STATE_D0;
8591 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
8593 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
8595 if(T3_ASIC_5752(pDevice->ChipRevId)){
8596 Value32 |= (GRC_MISC_LOCAL_CTRL_GPIO_OE3 |
8597 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT3 |
8598 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8599 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8600 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8601 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8602 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8603 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8607 Value32 &= ~(GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8608 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8609 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8610 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8611 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8612 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8615 RAW_REG_WR(pDevice, Grc.LocalCtrl, Value32);
8617 MM_Wait(40); /* Required delay is about 20us. */
8619 pDevice->PowerLevel = PowerLevel;
8620 return LM_STATUS_SUCCESS;
8623 else if(PowerLevel == LM_POWER_STATE_D1)
8625 PmCtrl |= T3_PM_POWER_STATE_D1;
8627 else if(PowerLevel == LM_POWER_STATE_D2)
8629 PmCtrl |= T3_PM_POWER_STATE_D2;
8631 else if(PowerLevel == LM_POWER_STATE_D3)
8633 PmCtrl |= T3_PM_POWER_STATE_D3;
8637 return LM_STATUS_FAILURE;
8639 PmCtrl |= T3_PM_PME_ENABLE;
8641 /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
8642 /* setting new line speed. */
8643 Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl);
8644 REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
8646 if(!pDevice->RestoreOnWakeUp)
8648 pDevice->RestoreOnWakeUp = TRUE;
8649 pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
8650 pDevice->WakeUpRequestedLineSpeed = pDevice->RequestedLineSpeed;
8651 pDevice->WakeUpRequestedDuplexMode = pDevice->RequestedDuplexMode;
8654 /* Force auto-negotiation to 10 line speed. */
8655 pDevice->DisableAutoNeg = FALSE;
8657 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG))
8659 pDevice->RequestedLineSpeed = LM_LINE_SPEED_10MBPS;
8660 LM_SetupPhy(pDevice);
8663 /* Put the driver in the initial state, and go through the power down */
8667 if (!(pDevice->AsfFlags & ASF_ENABLED))
8669 for(j = 0; j < 20000; j++)
8673 Value32 = MEM_RD_OFFSET(pDevice, T3_ASF_FW_STATUS_MAILBOX);
8674 if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE)
8681 MEM_WR_OFFSET(pDevice, DRV_WOL_MAILBOX, DRV_WOL_SIGNATURE |
8682 DRV_DOWN_STATE_SHUTDOWN | 0x2 | DRV_WOL_SET_MAGIC_PKT);
8684 MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
8686 if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)
8690 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG))
8692 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a);
8696 if (! T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
8698 /* Let boot code deal with LED mode on shasta */
8699 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
8702 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
8704 Value32 = MAC_MODE_PORT_MODE_TBI;
8708 Value32 = MAC_MODE_PORT_MODE_MII;
8709 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
8711 if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_2 ||
8712 pDevice->WolSpeed == WOL_SPEED_10MB)
8714 Value32 |= MAC_MODE_LINK_POLARITY;
8719 Value32 |= MAC_MODE_LINK_POLARITY;
8722 REG_WR(pDevice, MacCtrl.Mode, Value32);
8723 REG_RD_BACK(pDevice, MacCtrl.Mode);
8724 MM_Wait(40); MM_Wait(40); MM_Wait(40);
8726 /* Always enable magic packet wake-up if we have vaux. */
8727 if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
8728 (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET))
8730 Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
8734 if (pDevice->AsfFlags & ASF_ENABLED)
8736 Value32 &= ~MAC_MODE_ACPI_POWER_ON_ENABLE;
8739 REG_WR(pDevice, MacCtrl.Mode, Value32);
8741 /* Enable the receiver. */
8742 REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
8744 else if (!(pDevice->AsfFlags & ASF_ENABLED))
8746 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
8748 REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
8749 LED_CTRL_OVERRIDE_TRAFFIC_LED);
8753 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
8754 BCM540X_EXT_CTRL_FORCE_LED_OFF);
8755 LM_WritePhy(pDevice, 0x18, 0x01b2);
8756 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
8757 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) &&
8758 !T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8760 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOWER_POWER_MODE);
8765 /* Disable tx/rx clocks, and select an alternate clock. */
8766 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)){
8769 else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
8770 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) &&
8771 (pDevice->WolSpeed == WOL_SPEED_10MB)))
8773 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8774 T3_PCI_SELECT_ALTERNATE_CLOCK |
8775 T3_PCI_POWER_DOWN_PCI_PLL133;
8777 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8779 /* ASF on 5750 will not run properly on slow core clock */
8780 else if( !(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId) &&
8781 (pDevice->AsfFlags & ASF_ENABLED) ))
8783 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8785 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8786 T3_PCI_SELECT_ALTERNATE_CLOCK;
8788 else if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8790 Value32 = T3_PCI_625_CORE_CLOCK;
8794 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
8796 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8800 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8801 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8803 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8804 T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
8806 else if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8808 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_625_CORE_CLOCK;
8810 else if(!T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
8812 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
8815 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8817 if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
8821 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8822 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8824 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8825 T3_PCI_44MHZ_CORE_CLOCK;
8829 Value32 = T3_PCI_44MHZ_CORE_CLOCK;
8832 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8838 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
8840 pDevice2 = MM_FindPeerDev(pDevice);
8842 if (!(pDevice->Flags & EEPROM_WP_FLAG))
8844 LM_SwitchVaux(pDevice, pDevice2);
8847 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
8849 /* Workaround for pll instability */
8850 if((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5750_AX) ||
8851 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5750_BX)) {
8853 Value32= REG_RD_OFFSET(pDevice, 0x7d00);
8854 REG_WR_OFFSET(pDevice, 0x7d00,Value32 & ~(BIT_16 | BIT_4 | BIT_2 | BIT_1 | BIT_0));
8856 if(!(pDevice->AsfFlags & ASF_ENABLED))
8857 LM_HaltCpu(pDevice, T3_RX_CPU_ID);
8861 /* Put the the hardware in low power mode. */
8862 if (!(pDevice->Flags & DISABLE_D3HOT_FLAG))
8864 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
8865 MM_Wait(200); /* Wait 200us for state transition */
8868 pDevice->PowerLevel = PowerLevel;
8871 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
8872 #endif /* BCM_WOL */
8874 return LM_STATUS_SUCCESS;
8875 } /* LM_SetPowerState */
8879 LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2)
8881 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
8884 pDevice->GrcLocalCtrl &= ~(GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8885 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8886 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8887 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8888 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8889 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8891 /* Switch adapter to auxilliary power if WOL enabled */
8892 if ((pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) ||
8893 (pDevice->AsfFlags & ASF_ENABLED) ||
8894 (pDevice2 && ((pDevice2->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) ||
8895 (pDevice2->AsfFlags & ASF_ENABLED))))
8897 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8898 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8900 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
8901 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8902 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8903 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8904 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8905 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8906 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8911 if (pDevice2 && pDevice2->InitDone)
8916 /* On NICs GPIOs are used for vaux.
8917 The transition of GPIO0 from 0-1 causes vaux
8918 to power up. Transition of GPIO1 from 1-0 turns vaux off.
8919 GPIO2 transition from 1-0 enables a non-glitch vaux
8920 transition from one state to another.
8921 On certain designs we should not output GPIO2.
8923 if(pDevice->Flags & GPIO2_DONOT_OUTPUT)
8925 /* GPIO0 = 0, GPIO1 = 1. */
8926 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8927 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8928 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8929 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8933 /* GPIO0 = 1, GPIO1 = 1. */
8934 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8935 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8936 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8937 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8938 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8945 /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
8946 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8947 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8948 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8949 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8950 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8951 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8955 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
8956 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8957 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8958 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8959 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8960 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8961 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8962 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8965 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
8966 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8967 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8968 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8969 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8970 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8971 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8974 } /* Not 5700||5701 */
8975 } /* WOL disabled */
8978 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
8979 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
8981 if (pDevice2 && pDevice2->InitDone)
8987 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8988 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8989 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
8993 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8994 GRC_MISC_LOCAL_CTRL_GPIO_OE1);
8998 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
8999 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9000 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9007 /******************************************************************************/
9011 /******************************************************************************/
9013 GetPhyAdFlowCntrlSettings(
9014 PLM_DEVICE_BLOCK pDevice)
9020 /* Auto negotiation flow control only when autonegotiation is enabled. */
9021 if(pDevice->DisableAutoNeg == FALSE ||
9022 pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
9024 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
9025 (pDevice->PhyFlags & PHY_IS_FIBER)) {
9027 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
9028 if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
9029 ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
9030 (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
9032 Value32 |=PHY_AN_AD_1000XPAUSE;
9034 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
9036 Value32 |= PHY_AN_AD_1000XPSE_ASYM;
9038 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
9040 Value32 |= (PHY_AN_AD_1000XPSE_ASYM | PHY_AN_AD_1000XPAUSE);
9045 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
9046 if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
9047 ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
9048 (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
9050 Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
9052 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
9054 Value32 |= PHY_AN_AD_ASYM_PAUSE;
9056 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
9058 Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
9068 /******************************************************************************/
9072 /* LM_STATUS_FAILURE */
9073 /* LM_STATUS_SUCCESS */
9075 /******************************************************************************/
9077 LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice)
9079 LM_LINE_SPEED LineSpeed;
9080 LM_DUPLEX_MODE DuplexMode;
9081 LM_UINT32 NewPhyCtrl;
9082 LM_UINT32 Value32, PhyReg18;
9085 /* Get the interface type, line speed, and duplex mode. */
9086 LineSpeed = pDevice->RequestedLineSpeed;
9087 DuplexMode = pDevice->RequestedDuplexMode;
9089 /* Exit ext. loop back, in case it was in ext. loopback mode */
9090 /* Set Extended packet length bit on chips that support jumbo frames */
9091 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
9093 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
9095 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &Value32);
9096 Value32 |= 1; /* set tx elastic fifo */
9097 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, Value32);
9102 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
9103 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &PhyReg18);
9104 PhyReg18 &= ~0x8000; /* clear external loop back */
9106 if (pDevice->Flags & JUMBO_CAPABLE_FLAG)
9108 PhyReg18 |= 0x4000; /* set extended packet length */
9109 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &Value32);
9110 Value32 |= 1; /* set tx elastic fifo */
9111 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, Value32);
9113 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, PhyReg18);
9117 if (pDevice->RestoreOnWakeUp)
9119 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9120 pDevice->advertising1000 = 0;
9121 Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
9122 if (pDevice->WolSpeed == WOL_SPEED_100MB)
9124 Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
9126 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9127 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9128 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9129 pDevice->advertising = Value32;
9131 /* Setup the auto-negotiation advertisement register. */
9132 else if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
9134 /* Setup the auto-negotiation advertisement register. */
9135 if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
9138 /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
9139 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | PHY_AN_AD_ALL_SPEEDS;
9140 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9142 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9143 pDevice->advertising = Value32;
9145 /* Advertise 1000Mbps */
9146 if (!(pDevice->PhyFlags & PHY_NO_GIGABIT))
9148 Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS;
9150 #ifdef INCLUDE_5701_AX_FIX
9151 /* Bug: workaround for CRC error in gigabit mode when we are in */
9152 /* slave mode. This will force the PHY to operate in */
9154 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
9155 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
9157 Value32 |= BCM540X_CONFIG_AS_MASTER |
9158 BCM540X_ENABLE_CONFIG_AS_MASTER;
9162 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
9163 pDevice->advertising1000 = Value32;
9167 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9168 pDevice->advertising1000 = 0;
9173 if ((pDevice->PhyFlags & PHY_NO_GIGABIT) &&
9174 (LineSpeed == LM_LINE_SPEED_1000MBPS))
9176 LineSpeed = LM_LINE_SPEED_100MBPS;
9178 if(LineSpeed == LM_LINE_SPEED_1000MBPS)
9180 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9181 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9183 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9184 pDevice->advertising = Value32;
9186 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9188 Value32 = BCM540X_AN_AD_1000BASET_HALF;
9192 Value32 = BCM540X_AN_AD_1000BASET_FULL;
9195 #ifdef INCLUDE_5701_AX_FIX
9196 if ((pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE) ||
9197 (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
9198 pDevice->ChipRevId == T3_CHIP_ID_5701_B0))
9200 if (pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE)
9203 Value32 |= BCM540X_CONFIG_AS_MASTER |
9204 BCM540X_ENABLE_CONFIG_AS_MASTER;
9206 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
9207 pDevice->advertising1000 = Value32;
9208 if (pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE)
9210 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
9212 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x8c20);
9216 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
9217 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &PhyReg18);
9218 PhyReg18 |= 0x8000; /* set loop back */
9219 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, PhyReg18);
9223 else if(LineSpeed == LM_LINE_SPEED_100MBPS)
9225 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9226 pDevice->advertising1000 = 0;
9228 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9230 Value32 = PHY_AN_AD_100BASETX_HALF;
9234 Value32 = PHY_AN_AD_100BASETX_FULL;
9237 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9238 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9240 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9241 pDevice->advertising = Value32;
9243 else if(LineSpeed == LM_LINE_SPEED_10MBPS)
9245 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9246 pDevice->advertising1000 = 0;
9248 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9250 Value32 = PHY_AN_AD_10BASET_HALF;
9254 Value32 = PHY_AN_AD_10BASET_FULL;
9257 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9258 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9260 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9261 pDevice->advertising = Value32;
9265 /* Force line speed if auto-negotiation is disabled. */
9266 if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN)
9268 /* This code path is executed only when there is link. */
9269 pDevice->LineSpeed = LineSpeed;
9270 pDevice->DuplexMode = DuplexMode;
9272 /* Force line seepd. */
9276 case LM_LINE_SPEED_10MBPS:
9277 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
9279 case LM_LINE_SPEED_100MBPS:
9280 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
9282 case LM_LINE_SPEED_1000MBPS:
9283 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
9286 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
9290 if(DuplexMode == LM_DUPLEX_MODE_FULL)
9292 NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
9295 /* Don't do anything if the PHY_CTRL is already what we wanted. */
9296 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
9297 if(Value32 != NewPhyCtrl)
9299 /* Temporary bring the link down before forcing line speed. */
9300 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE);
9302 /* Wait for link to go down. */
9303 for(Cnt = 0; Cnt < 1500; Cnt++)
9307 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
9308 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
9310 if(!(Value32 & PHY_STATUS_LINK_PASS))
9317 LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl);
9323 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
9324 PHY_CTRL_RESTART_AUTO_NEG);
9327 return LM_STATUS_SUCCESS;
9328 } /* LM_ForceAutoNegBcm540xPhy */
9330 /******************************************************************************/
9334 /******************************************************************************/
9335 LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
9336 PT3_FWIMG_INFO pFwImg,
9342 LM_VOID (*Wr_fn)(PLM_DEVICE_BLOCK pDevice,LM_UINT32 Register,LM_UINT32 Value32);
9343 LM_UINT32 (*Rd_fn)(PLM_DEVICE_BLOCK pDevice,LM_UINT32 Register);
9345 LM_UINT32 base_addr;
9347 #ifdef INCLUDE_TCP_SEG_SUPPORT
9348 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
9350 Wr_fn = LM_MemWrInd;
9351 Rd_fn = LM_MemRdInd;
9352 len = LM_GetStkOffLdFirmwareSize(pDevice);
9353 base_addr = T3_NIC_BCM5705_MBUF_POOL_ADDR;
9358 Wr_fn = LM_RegWrInd;
9359 Rd_fn = LM_RegRdInd;
9360 len = T3_RX_CPU_SPAD_SIZE;
9361 base_addr = T3_RX_CPU_SPAD_ADDR;
9364 if (LoadCpu & T3_RX_CPU_ID)
9366 if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS)
9368 return LM_STATUS_FAILURE;
9371 /* First of all clear scrach pad memory */
9372 for (i = 0; i < len; i+=4)
9374 Wr_fn(pDevice,base_addr+i,0);
9377 /* Copy code first */
9378 address = base_addr + (pFwImg->Text.Offset & 0xffff);
9379 for (i = 0; i <= pFwImg->Text.Length; i+=4)
9381 Wr_fn(pDevice,address+i,
9382 ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
9385 address = base_addr + (pFwImg->ROnlyData.Offset & 0xffff);
9386 for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4)
9388 Wr_fn(pDevice,address+i,
9389 ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
9392 address = base_addr + (pFwImg->Data.Offset & 0xffff);
9393 for (i= 0; i <= pFwImg->Data.Length; i+=4)
9395 Wr_fn(pDevice,address+i,
9396 ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
9400 if ((LoadCpu & T3_TX_CPU_ID) &&
9401 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705))
9403 if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS)
9405 return LM_STATUS_FAILURE;
9408 /* First of all clear scrach pad memory */
9409 for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4)
9411 Wr_fn(pDevice,T3_TX_CPU_SPAD_ADDR+i,0);
9414 /* Copy code first */
9415 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
9416 for (i= 0; i <= pFwImg->Text.Length; i+=4)
9418 Wr_fn(pDevice,address+i,
9419 ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
9422 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
9423 for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4)
9425 Wr_fn(pDevice,address+i,
9426 ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
9429 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
9430 for (i= 0; i <= pFwImg->Data.Length; i+=4)
9432 Wr_fn(pDevice,address+i,
9433 ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
9437 if (StartCpu & T3_RX_CPU_ID)
9440 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9441 REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
9442 for (i = 0 ; i < 5; i++)
9444 if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC))
9447 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9448 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9449 REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
9450 REG_RD_BACK(pDevice,rxCpu.reg.PC);
9454 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9455 REG_WR(pDevice,rxCpu.reg.mode, 0);
9458 if ((StartCpu & T3_TX_CPU_ID) &&
9459 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705))
9462 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9463 REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
9464 for (i = 0 ; i < 5; i++)
9466 if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC))
9469 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9470 REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
9471 REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
9472 REG_RD_BACK(pDevice,txCpu.reg.PC);
9476 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9477 REG_WR(pDevice,txCpu.reg.mode, 0);
9480 return LM_STATUS_SUCCESS;
9483 LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number)
9488 status = LM_STATUS_SUCCESS;
9490 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) &&
9491 !(cpu_number & T3_RX_CPU_ID))
9496 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9497 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9499 status = LM_NVRAM_AcquireLock(pDevice);
9502 if (cpu_number & T3_RX_CPU_ID)
9504 for (i = 0 ; i < 10000; i++)
9506 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9507 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9509 if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT)
9513 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9514 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9515 REG_RD_BACK(pDevice,rxCpu.reg.mode);
9519 status = LM_STATUS_FAILURE;
9522 if ((pDevice->Flags & T3_HAS_TWO_CPUS) &&
9523 (cpu_number & T3_TX_CPU_ID))
9525 for (i = 0 ; i < 10000; i++)
9527 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9528 REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
9530 if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT)
9535 status = LM_STATUS_FAILURE;
9538 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9539 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9541 if (status != LM_STATUS_SUCCESS)
9544 * Some part of this operation failed.
9545 * Just undo our own actions.
9547 LM_NVRAM_ReleaseLock(pDevice);
9549 else if (!(pDevice->Flags & T3_HAS_TWO_CPUS) ||
9550 cpu_number == (T3_TX_CPU_ID | T3_RX_CPU_ID))
9553 * Release our NVRAM arbitration grant along
9554 * with the firmware's arbitration request bit.
9556 REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 | SW_ARB_REQ_CLR0);
9557 REG_RD_BACK(pDevice, Nvram.SwArb);
9561 LM_NVRAM_ReleaseLock(pDevice);
9563 if (LM_NVRAM_AcquireLock(pDevice) == LM_STATUS_SUCCESS)
9565 /* All is well. Release the arbitration and continue. */
9566 LM_NVRAM_ReleaseLock(pDevice);
9571 * We've timed out while attempting to get the
9572 * NVRAM arbitration. Assume the cause is that
9573 * the NVRAM has requested arbitration after we
9574 * acquired arbitration the first time, but before
9575 * the CPU was actually halted.
9579 * Release our NVRAM arbitration grant along
9580 * with the firmware's arbitration request bit.
9582 REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 | SW_ARB_REQ_CLR0);
9583 REG_RD_BACK(pDevice, Nvram.SwArb);
9593 LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
9596 int ret = LM_STATUS_SUCCESS;
9598 if(BlinkDurationSec == 0)
9600 BlinkDurationSec = 1;
9602 if(BlinkDurationSec > 120)
9604 BlinkDurationSec = 120;
9607 for(j = 0; j < BlinkDurationSec * 2; j++)
9611 // Turn on the LEDs.
9612 REG_WR(pDevice, MacCtrl.LedCtrl,
9613 LED_CTRL_OVERRIDE_LINK_LED |
9614 LED_CTRL_1000MBPS_LED_ON |
9615 LED_CTRL_100MBPS_LED_ON |
9616 LED_CTRL_10MBPS_LED_ON |
9617 LED_CTRL_OVERRIDE_TRAFFIC_LED |
9618 LED_CTRL_BLINK_TRAFFIC_LED |
9619 LED_CTRL_TRAFFIC_LED);
9623 // Turn off the LEDs.
9624 REG_WR(pDevice, MacCtrl.LedCtrl,
9625 LED_CTRL_OVERRIDE_LINK_LED |
9626 LED_CTRL_OVERRIDE_TRAFFIC_LED);
9628 if (MM_Sleep(pDevice, 500) != LM_STATUS_SUCCESS)/* 0.5 second */
9630 ret = LM_STATUS_FAILURE;
9634 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
9639 LM_SwitchClocks(PLM_DEVICE_BLOCK pDevice)
9641 LM_UINT32 ClockCtrl;
9643 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
9644 return LM_STATUS_SUCCESS;
9646 ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl);
9647 pDevice->ClockCtrl = ClockCtrl & (T3_PCI_FORCE_CLKRUN |
9648 T3_PCI_CLKRUN_OUTPUT_EN | 0x1f);
9649 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
9651 if (ClockCtrl & T3_PCI_625_CORE_CLOCK)
9653 /* clear ALT clock first */
9654 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9655 T3_PCI_625_CORE_CLOCK);
9656 MM_Wait(40); /* required delay is 27usec */
9661 if (ClockCtrl & T3_PCI_44MHZ_CORE_CLOCK)
9663 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9664 T3_PCI_44MHZ_CORE_CLOCK | T3_PCI_SELECT_ALTERNATE_CLOCK);
9665 MM_Wait(40); /* required delay is 27usec */
9666 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9667 T3_PCI_SELECT_ALTERNATE_CLOCK);
9668 MM_Wait(40); /* required delay is 27usec */
9672 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl);
9673 MM_Wait(40); /* required delay is 27usec */
9674 return LM_STATUS_SUCCESS;
9677 int t3_do_dma(PLM_DEVICE_BLOCK pDevice,
9678 LM_PHYSICAL_ADDRESS host_addr_phy, int length,
9681 T3_DMA_DESC dma_desc;
9683 LM_UINT32 dma_desc_addr;
9686 REG_WR(pDevice, BufMgr.Mode, 0);
9687 REG_WR(pDevice, Ftq.Reset, 0);
9689 dma_desc.host_addr.High = host_addr_phy.High;
9690 dma_desc.host_addr.Low = host_addr_phy.Low;
9691 dma_desc.nic_mbuf = 0x2100;
9692 dma_desc.len = length;
9693 dma_desc.flags = 0x00000005; /* Generate Rx-CPU event */
9697 dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
9698 T3_QID_DMA_HIGH_PRI_READ;
9699 REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
9703 dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
9704 T3_QID_DMA_HIGH_PRI_WRITE;
9705 REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
9708 dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
9710 /* Writing this DMA descriptor to DMA memory */
9711 for (i = 0; i < sizeof(T3_DMA_DESC); i += 4)
9713 value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i));
9714 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i);
9715 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG,
9716 MM_SWAP_LE32(value32));
9718 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
9721 REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr);
9723 REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr);
9725 for (i = 0; i < 40; i++)
9728 value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue);
9730 value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue);
9732 if ((value32 & 0xffff) == dma_desc_addr)
9738 return LM_STATUS_SUCCESS;
9742 LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
9743 LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
9747 int dma_success = 0;
9748 LM_STATUS ret = LM_STATUS_FAILURE;
9750 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
9751 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
9753 return LM_STATUS_SUCCESS;
9755 while (!dma_success)
9757 /* Fill data with incremental patterns */
9758 ptr = (LM_UINT32 *)pBufferVirt;
9759 for (j = 0; j < BufferSize/4; j++)
9762 if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE)
9764 goto LM_DmaTestDone;
9768 ptr = (LM_UINT32 *)pBufferVirt;
9769 /* Fill data with zero */
9770 for (j = 0; j < BufferSize/4; j++)
9773 if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE)
9775 goto LM_DmaTestDone;
9779 /* Check for data */
9780 ptr = (LM_UINT32 *)pBufferVirt;
9781 for (j = 0; j < BufferSize/4; j++)
9785 if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK)
9786 != DMA_CTRL_WRITE_BOUNDARY_16)
9788 pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl &
9789 ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
9790 DMA_CTRL_WRITE_BOUNDARY_16;
9791 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl,
9792 pDevice->DmaReadWriteCtrl);
9797 goto LM_DmaTestDone;
9801 if (j == (BufferSize/4))
9804 ret = LM_STATUS_SUCCESS;
9806 memset(pBufferVirt, 0, BufferSize);
9811 LM_Add32To64Counter(LM_UINT32 Counter32, T3_64BIT_REGISTER *Counter64)
9813 Counter64->Low += Counter32;
9814 if (Counter64->Low < Counter32)
9821 LM_GetStats(PLM_DEVICE_BLOCK pDevice)
9823 PT3_STATS_BLOCK pStats = (PT3_STATS_BLOCK) pDevice->pStatsBlkVirt;
9825 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
9827 return LM_STATUS_FAILURE;
9832 return LM_STATUS_FAILURE;
9834 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutOctets),
9835 &pStats->ifHCOutOctets);
9836 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsCollisions),
9837 &pStats->etherStatsCollisions);
9838 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.outXonSent),
9839 &pStats->outXonSent);
9840 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.outXoffSent),
9841 &pStats->outXoffSent);
9842 LM_Add32To64Counter(REG_RD(pDevice,
9843 MacCtrl.dot3StatsInternalMacTransmitErrors),
9844 &pStats->dot3StatsInternalMacTransmitErrors);
9845 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsSingleCollisionFrames),
9846 &pStats->dot3StatsSingleCollisionFrames);
9847 LM_Add32To64Counter(REG_RD(pDevice,
9848 MacCtrl.dot3StatsMultipleCollisionFrames),
9849 &pStats->dot3StatsMultipleCollisionFrames);
9850 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsDeferredTransmissions),
9851 &pStats->dot3StatsDeferredTransmissions);
9852 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsExcessiveCollisions),
9853 &pStats->dot3StatsExcessiveCollisions);
9854 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsLateCollisions),
9855 &pStats->dot3StatsLateCollisions);
9856 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutUcastPkts),
9857 &pStats->ifHCOutUcastPkts);
9858 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutMulticastPkts),
9859 &pStats->ifHCOutMulticastPkts);
9860 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutBroadcastPkts),
9861 &pStats->ifHCOutBroadcastPkts);
9862 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInOctets),
9863 &pStats->ifHCInOctets);
9864 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsFragments),
9865 &pStats->etherStatsFragments);
9866 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInUcastPkts),
9867 &pStats->ifHCInUcastPkts);
9868 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInMulticastPkts),
9869 &pStats->ifHCInMulticastPkts);
9870 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInBroadcastPkts),
9871 &pStats->ifHCInBroadcastPkts);
9872 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsFCSErrors),
9873 &pStats->dot3StatsFCSErrors);
9874 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsAlignmentErrors),
9875 &pStats->dot3StatsAlignmentErrors);
9876 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xonPauseFramesReceived),
9877 &pStats->xonPauseFramesReceived);
9878 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xoffPauseFramesReceived),
9879 &pStats->xoffPauseFramesReceived);
9880 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.macControlFramesReceived),
9881 &pStats->macControlFramesReceived);
9882 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xoffStateEntered),
9883 &pStats->xoffStateEntered);
9884 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsFramesTooLong),
9885 &pStats->dot3StatsFramesTooLong);
9886 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsJabbers),
9887 &pStats->etherStatsJabbers);
9888 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsUndersizePkts),
9889 &pStats->etherStatsUndersizePkts);
9891 return LM_STATUS_SUCCESS;