1 /******************************************************************************/
3 /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2005 Broadcom */
5 /* All rights reserved. */
7 /* This program is free software; you can redistribute it and/or modify */
8 /* it under the terms of the GNU General Public License as published by */
9 /* the Free Software Foundation, located in the file LICENSE. */
13 /******************************************************************************/
19 #if INCLUDE_TBI_SUPPORT
25 /******************************************************************************/
27 /******************************************************************************/
30 #define TIGON3_DEBUG 0
31 #endif /* TIGON3_DEBUG */
33 /* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */
34 /* Currently, Jumbo Receive RCB is disabled. */
35 #ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT
36 #define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0
37 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
39 #ifndef T3_JUMBO_RCV_ENTRY_COUNT
40 #define T3_JUMBO_RCV_ENTRY_COUNT 0
41 #endif /* T3_JUMBO_RCV_ENTRY_COUNT */
43 #ifndef T3_JUMBO_RCB_ENTRY_COUNT
44 #define T3_JUMBO_RCB_ENTRY_COUNT 0
45 #endif /* T3_JUMBO_RCB_ENTRY_COUNT */
47 /* Maxim number of packet descriptors used for sending packets. */
48 #define MAX_TX_PACKET_DESC_COUNT T3_SEND_RCB_ENTRY_COUNT
49 #define DEFAULT_TX_PACKET_DESC_COUNT 120
51 /* Maximum number of packet descriptors used for receiving packets. */
52 #if T3_JUMBO_RCB_ENTRY_COUNT
53 #define MAX_RX_PACKET_DESC_COUNT \
54 (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT)
56 #define MAX_RX_PACKET_DESC_COUNT T3_STD_RCV_RCB_ENTRY_COUNT
58 #define DEFAULT_RX_PACKET_DESC_COUNT 200
60 /* Threshhold for double copying small tx packets. 0 will disable double */
61 /* copying of small Tx packets. */
62 #define DEFAULT_TX_COPY_BUFFER_SIZE 0
63 #define MIN_TX_COPY_BUFFER_SIZE 64
64 #define MAX_TX_COPY_BUFFER_SIZE 512
67 #define COMMON_CACHE_LINE_SIZE 0x20
68 #define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1)
70 /* Maximum number of fragment we can handle. */
71 #ifndef MAX_FRAGMENT_COUNT
72 #define MAX_FRAGMENT_COUNT 32
76 #define BCM5700_BX_MIN_FRAG_SIZE 10
77 #define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */
78 #define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
79 #define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
83 //#define T3_MAGIC_NUM 'KevT'
84 #define T3_FIRMWARE_MAILBOX 0x0b50
85 #define T3_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4B657654
86 #define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b
88 #define T3_NIC_DATA_SIG_ADDR 0x0b54
89 #define T3_NIC_DATA_SIG 0x4b657654
91 #define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58
92 #define T3_NIC_CFG_LED_MAC_MODE BIT_NONE
93 #define T3_NIC_CFG_LED_PHY_MODE_1 BIT_2
94 #define T3_NIC_CFG_LED_PHY_MODE_2 BIT_3
95 #define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3)
96 #define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE
97 #define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4
98 #define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5
99 #define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5)
100 #define T3_NIC_CFG_ENABLE_WOL BIT_6
101 #define T3_NIC_CFG_ENABLE_ASF BIT_7
102 #define T3_NIC_EEPROM_WP BIT_8
103 #define T3_NIC_WOL_LIMIT_10 BIT_10
104 #define T3_NIC_MINI_PCI BIT_12
105 #define T3_NIC_FIBER_WOL_CAPABLE BIT_14
106 #define T3_NIC_BOTH_PORT_100MB_WOL_CAPABLE BIT_15
107 #define T3_NIC_GPIO2_NOT_AVAILABLE BIT_20
109 #define T3_NIC_DATA_VER 0x0b5c
110 #define T3_NIC_DATA_VER_SHIFT 16
112 #define T3_NIC_DATA_PHY_ID_ADDR 0x0b74
113 #define T3_NIC_PHY_ID1_MASK 0xffff0000
114 #define T3_NIC_PHY_ID2_MASK 0x0000ffff
116 #define T3_CMD_MAILBOX 0x0b78
117 #define T3_CMD_NICDRV_ALIVE 0x01
118 #define T3_CMD_NICDRV_PAUSE_FW 0x02
119 #define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03
120 #define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04
121 #define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05
122 #define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06
124 #define T3_CMD_NICDRV_ALIVE2 0x0d
126 #define T3_CMD_LENGTH_MAILBOX 0x0b7c
127 #define T3_CMD_DATA_MAILBOX 0x0b80
129 #define T3_ASF_FW_STATUS_MAILBOX 0x0c00
131 #define T3_DRV_STATE_MAILBOX 0x0c04
132 #define T3_DRV_STATE_START 0x01
133 #define T3_DRV_STATE_START_DONE 0x80000001
134 #define T3_DRV_STATE_UNLOAD 0x02
135 #define T3_DRV_STATE_UNLOAD_DONE 0x80000002
136 #define T3_DRV_STATE_WOL 0x03
137 #define T3_DRV_STATE_SUSPEND 0x04
139 #define T3_FW_RESET_TYPE_MAILBOX 0x0c08
141 #define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14
142 #define T3_MAC_ADDR_LOW_MAILBOX 0x0c18
144 #define DRV_WOL_MAILBOX 0xd30
145 #define DRV_WOL_SIGNATURE 0x474c0000
147 #define DRV_DOWN_STATE_SHUTDOWN 0x1
149 #define DRV_WOL_SET_MAGIC_PKT BIT_2
151 #define T3_NIC_DATA_NIC_CFG_ADDR2 0x0d38 /* bit 2-3 are same as in */
153 #define T3_SHASTA_EXT_LED_MODE_MASK (BIT_15 | BIT_16)
154 #define T3_SHASTA_EXT_LED_LEGACY_MODE BIT_NONE
155 #define T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE BIT_15
156 #define T3_SHASTA_EXT_LED_MAC_MODE BIT_16
157 #define T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE (BIT_15 | BIT_16)
158 #define T3_NIC_CFG_CAPACITIVE_COUPLING BIT_17
159 #define T3_NIC_CFG_PRESERVE_PREEMPHASIS BIT_18
161 /******************************************************************************/
162 /* Hardware constants. */
163 /******************************************************************************/
165 /* Number of entries in the send ring: must be 512. */
166 #define T3_SEND_RCB_ENTRY_COUNT 512
167 #define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1)
169 /* Number of send RCBs. May be 1-16 but for now, only support one. */
170 #define T3_MAX_SEND_RCB_COUNT 16
172 /* Number of entries in the Standard Receive RCB. Must be 512 entries. */
173 #define T3_STD_RCV_RCB_ENTRY_COUNT 512
174 #define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1)
175 #define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */
176 #define MAX_STD_RCV_BUFFER_SIZE 0x600
178 /* Number of entries in the Mini Receive RCB. This value can either be */
179 /* 0, 1024. Currently Mini Receive RCB is disabled. */
180 #ifndef T3_MINI_RCV_RCB_ENTRY_COUNT
181 #define T3_MINI_RCV_RCB_ENTRY_COUNT 0
182 #endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
183 #define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1)
184 #define MAX_MINI_RCV_BUFFER_SIZE 512
185 #define DEFAULT_MINI_RCV_BUFFER_SIZE 64
186 #define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */
188 #define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1)
190 #define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */
191 #define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */
192 #define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */
194 #define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */
195 #define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */
197 /* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */
198 #define T3_MAX_RCV_RETURN_RCB_COUNT 16
200 /* Number of entries in a Receive Return ring. This value is either 1024 */
202 #ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT
203 #define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024
204 #endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
205 #define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)
208 /* Default coalescing parameters. */
209 #ifdef BCM_NAPI_RXPOLL
210 #define DEFAULT_RX_COALESCING_TICKS 18
211 #define DEFAULT_RX_MAX_COALESCED_FRAMES 6
213 #define DEFAULT_RX_COALESCING_TICKS 60
214 #define DEFAULT_RX_MAX_COALESCED_FRAMES 15
217 #define DEFAULT_TX_COALESCING_TICKS 200
218 #define DEFAULT_TX_MAX_COALESCED_FRAMES 35
220 #define MAX_RX_COALESCING_TICKS 500
221 #define MAX_TX_COALESCING_TICKS 500
222 #define MAX_RX_MAX_COALESCED_FRAMES 100
223 #define MAX_TX_MAX_COALESCED_FRAMES 100
225 #define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5
226 #define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 48
227 #define ADAPTIVE_LO_RX_COALESCING_TICKS 25
228 #define ADAPTIVE_HI_RX_COALESCING_TICKS 120
229 #define ADAPTIVE_LO_PKT_THRESH 52000
230 #define ADAPTIVE_HI_PKT_THRESH 112000
231 #define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 20
232 #define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75
234 #ifdef BCM_NAPI_RXPOLL
235 #define DEFAULT_RX_COALESCING_TICKS_DURING_INT 18
236 #define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 6
238 #define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25
239 #define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 2
241 #define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25
242 #define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES_DURING_INT 1
243 #define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES_DURING_INT 5
244 #define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5
246 #define BAD_DEFAULT_VALUE 0xffffffff
248 #define DEFAULT_STATS_COALESCING_TICKS 1000000
249 #define MIN_STATS_COALESCING_TICKS 100
250 #define MAX_STATS_COALESCING_TICKS 3600000000U
253 /* Receive BD Replenish thresholds. */
254 #define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4
255 #define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4
257 /* Maximum physical fragment size. */
258 #define MAX_FRAGMENT_SIZE (64 * 1024)
262 #define T3_STD_VIEW_SIZE (64 * 1024)
263 #define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024)
266 /* Buffer descriptor base address on the NIC's memory. */
268 #define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000
269 #define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000
270 #define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000
272 #define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000
273 #define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000
274 #define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000
276 #define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \
277 sizeof(T3_SND_BD) / 4)
279 #define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \
280 sizeof(T3_RCV_BD) / 4)
282 #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
283 sizeof(T3_EXT_RCV_BD) / 4)
287 #define T3_NIC_MBUF_POOL_ADDR 0x8000
288 #define T3_NIC_MBUF_POOL_SIZE32 0x8000
289 #define T3_NIC_MBUF_POOL_SIZE96 0x18000
290 #define T3_NIC_MBUF_POOL_SIZE64 0x10000
292 #define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000
294 #define T3_NIC_BCM5705_MBUF_POOL_ADDR 0x10000
295 #define T3_NIC_BCM5705_MBUF_POOL_SIZE 0xe000
297 /* DMA descriptor pool */
298 #define T3_NIC_DMA_DESC_POOL_ADDR 0x2000
299 #define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */
301 #define T3_DEF_DMA_MBUF_LOW_WMARK 0x50
302 #define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20
303 #define T3_DEF_MBUF_HIGH_WMARK 0x60
305 #define T3_DEF_DMA_MBUF_LOW_WMARK_5705 0x0
306 #define T3_DEF_RX_MAC_MBUF_LOW_WMARK_5705 0x10
307 #define T3_DEF_MBUF_HIGH_WMARK_5705 0x60
309 #define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304
310 #define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152
311 #define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380
313 #define T3_DEF_DMA_DESC_LOW_WMARK 5
314 #define T3_DEF_DMA_DESC_HIGH_WMARK 10
316 /* Maximum size of giant TCP packet can be sent */
317 #define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000
318 #define T3_TCP_SEG_MIN_NUM_SEG 20
320 #define T3_RX_CPU_ID 0x1
321 #define T3_TX_CPU_ID 0x2
322 #define T3_RX_CPU_SPAD_ADDR 0x30000
323 #define T3_RX_CPU_SPAD_SIZE 0x4000
324 #define T3_TX_CPU_SPAD_ADDR 0x34000
325 #define T3_TX_CPU_SPAD_SIZE 0x4000
327 typedef struct T3_DIR_ENTRY
332 } T3_DIR_ENTRY,*PT3_DIR_ENTRY;
334 typedef struct T3_FWIMG_INFO
336 LM_UINT32 StartAddress;
338 T3_DIR_ENTRY ROnlyData;
342 } T3_FWIMG_INFO, *PT3_FWIMG_INFO;
346 /******************************************************************************/
347 /* Tigon3 PCI Registers. */
348 /******************************************************************************/
349 /* MSI ENABLE bit is located at this offset */
350 #define T3_PCI_MSI_ENABLE 0x58
352 #define T3_PCI_ID_BCM5700 0x164414e4
353 #define T3_PCI_ID_BCM5701 0x164514e4
354 #define T3_PCI_ID_BCM5702 0x164614e4
355 #define T3_PCI_ID_BCM5702x 0x16A614e4
356 #define T3_PCI_ID_BCM5703 0x164714e4
357 #define T3_PCI_ID_BCM5703x 0x16A714e4
358 #define T3_PCI_ID_BCM5702FE 0x164D14e4
359 #define T3_PCI_ID_BCM5704 0x164814e4
360 #define T3_PCI_ID_BCM5705 0x165314e4
361 #define T3_PCI_ID_BCM5705M 0x165D14e4
362 #define T3_PCI_ID_BCM5705F 0x166E14e4
363 #define T3_PCI_ID_BCM5901 0x170D14e4
364 #define T3_PCI_ID_BCM5901A2 0x170E14e4
365 #define T3_PCI_ID_BCM5751F 0x167E14e4
367 #define T3_PCI_ID_BCM5753 0x16f714e4
368 #define T3_PCI_ID_BCM5753M 0x16fd14e4
369 #define T3_PCI_ID_BCM5753F 0x16fe14e4
370 #define T3_PCI_ID_BCM5781 0x16dd14e4
372 #define T3_PCI_ID_BCM5903M 0x16ff14e4
374 #define T3_PCI_VENDOR_ID(x) ((x) & 0xffff)
375 #define T3_PCI_DEVICE_ID(x) ((x) >> 16)
377 #define T3_PCI_MISC_HOST_CTRL_REG 0x68
379 /* The most significant 16bit of register 0x68. */
380 /* ChipId:4, ChipRev:4, MetalRev:8 */
381 #define T3_CHIP_ID_5700_A0 0x7000
382 #define T3_CHIP_ID_5700_A1 0x7001
383 #define T3_CHIP_ID_5700_B0 0x7100
384 #define T3_CHIP_ID_5700_B1 0x7101
385 #define T3_CHIP_ID_5700_C0 0x7200
387 #define T3_CHIP_ID_5701_A0 0x0000
388 #define T3_CHIP_ID_5701_B0 0x0100
389 #define T3_CHIP_ID_5701_B2 0x0102
390 #define T3_CHIP_ID_5701_B5 0x0105
392 #define T3_CHIP_ID_5703_A0 0x1000
393 #define T3_CHIP_ID_5703_A1 0x1001
394 #define T3_CHIP_ID_5703_A2 0x1002
395 #define T3_CHIP_ID_5703_A3 0x1003
397 #define T3_CHIP_ID_5704_A0 0x2000
398 #define T3_CHIP_ID_5704_A1 0x2001
399 #define T3_CHIP_ID_5704_A2 0x2002
401 #define T3_CHIP_ID_5705_A0 0x3000
402 #define T3_CHIP_ID_5705_A1 0x3001
403 #define T3_CHIP_ID_5705_A2 0x3002
404 #define T3_CHIP_ID_5705_A3 0x3003
406 #define T3_CHIP_ID_5750_A0 0x4000
407 #define T3_CHIP_ID_5750_A1 0x4001
408 #define T3_CHIP_ID_5750_A3 0x4003
409 #define T3_CHIP_ID_5750_B0 0x4010
410 #define T3_CHIP_ID_5750_C0 0x4200
412 #define T3_CHIP_ID_5714_A0 0x5000
413 #define T3_CHIP_ID_5752_A0 0x6000
414 #define T3_CHIP_ID_5714 0x8000
418 #define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12)
419 #define T3_ASIC_REV_5700 0x07
420 #define T3_ASIC_REV_5701 0x00
421 #define T3_ASIC_REV_5703 0x01
422 #define T3_ASIC_REV_5704 0x02
423 #define T3_ASIC_REV_5705 0x03
424 #define T3_ASIC_REV_5750 0x04
425 #define T3_ASIC_REV_5714_A0 0x05 /*5714,5715*/
426 #define T3_ASIC_REV_5752 0x06
427 #define T3_ASIC_REV_5780 0x08 /* 5780 previously htle */
428 #define T3_ASIC_REV_5714 0x09 /*5714,5715*/
430 #define T3_ASIC_IS_5705_BEYOND(_ChipRevId) \
431 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5705) || \
432 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5750) || \
433 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714_A0) || \
434 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5780) || \
435 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714) || \
436 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5752))
438 #define T3_ASIC_IS_575X_PLUS(_ChipRevId) \
439 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5750) || \
440 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714_A0) || \
441 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5780) || \
442 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714) || \
443 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5752))
445 #define T3_ASIC_5714_FAMILY(_ChipRevId) \
446 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714_A0) || \
447 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5780) || \
448 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714))
450 #define T3_ASIC_IS_JUMBO_CAPABLE(_ChipRevId) \
451 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5700) || \
452 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5701) || \
453 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5703) || \
454 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714_A0) || \
455 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5780) || \
456 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714) || \
457 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5704))
459 #define T3_ASIC_5752(_ChipRevId) \
460 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5752)
462 #define T3_ASIC_5705_OR_5750(_ChipRevId) \
463 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5705) || \
464 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5750))
466 /* Chip id and revision. */
467 #define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8)
468 #define T3_CHIP_REV_5700_AX 0x70
469 #define T3_CHIP_REV_5700_BX 0x71
470 #define T3_CHIP_REV_5700_CX 0x72
471 #define T3_CHIP_REV_5701_AX 0x00
472 #define T3_CHIP_REV_5703_AX 0x10
473 #define T3_CHIP_REV_5704_AX 0x20
474 #define T3_CHIP_REV_5704_BX 0x21
476 #define T3_CHIP_REV_5750_AX 0x40
477 #define T3_CHIP_REV_5750_BX 0x41
479 /* Metal revision. */
480 #define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff)
481 #define T3_METAL_REV_A0 0x00
482 #define T3_METAL_REV_A1 0x01
483 #define T3_METAL_REV_B0 0x00
484 #define T3_METAL_REV_B1 0x01
485 #define T3_METAL_REV_B2 0x02
487 #define T3_PCI_REG_CLOCK_CTRL 0x74
489 #define T3_PCI_DISABLE_RX_CLOCK BIT_10
490 #define T3_PCI_DISABLE_TX_CLOCK BIT_11
491 #define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12
492 #define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15
493 #define T3_PCI_44MHZ_CORE_CLOCK BIT_18
494 #define T3_PCI_625_CORE_CLOCK BIT_20
495 #define T3_PCI_FORCE_CLKRUN BIT_21
496 #define T3_PCI_CLKRUN_OUTPUT_EN BIT_22
499 #define T3_PCI_REG_ADDR_REG 0x78
500 #define T3_PCI_REG_DATA_REG 0x80
502 #define T3_PCI_MEM_WIN_ADDR_REG 0x7c
503 #define T3_PCI_MEM_WIN_DATA_REG 0x84
505 #define T3_PCI_PM_CAP_REG 0x48
507 #define T3_PCI_PM_CAP_PME_D3COLD BIT_31
508 #define T3_PCI_PM_CAP_PME_D3HOT BIT_30
510 #define T3_PCI_PM_STATUS_CTRL_REG 0x4c
512 #define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1)
513 #define T3_PM_POWER_STATE_D0 BIT_NONE
514 #define T3_PM_POWER_STATE_D1 BIT_0
515 #define T3_PM_POWER_STATE_D2 BIT_1
516 #define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1)
518 #define T3_PM_PME_ENABLE BIT_8
519 #define T3_PM_PME_ASSERTED BIT_15
521 #define T3_MSI_CAPABILITY_ID_REG 0x58
522 #define T3_MSI_NEXT_CAPABILITY_PTR 0x59
524 /* PCI state register. */
525 #define T3_PCI_STATE_REG 0x70
527 #define T3_PCI_STATE_FORCE_RESET BIT_0
528 #define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1
529 #define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2
530 #define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3
531 #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
534 /* Broadcom subsystem/subvendor IDs. */
535 #define T3_SVID_BROADCOM 0x14e4
537 #define T3_SSID_BROADCOM_BCM95700A6 0x1644
538 #define T3_SSID_BROADCOM_BCM95701A5 0x0001
539 #define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */
540 #define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */
541 #define T3_SSID_BROADCOM_BCM95701T1 0x0005
542 #define T3_SSID_BROADCOM_BCM95701T8 0x0006
543 #define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */
544 #define T3_SSID_BROADCOM_BCM95701A10 0x0008
545 #define T3_SSID_BROADCOM_BCM95701A12 0x8008
546 #define T3_SSID_BROADCOM_BCM95703Ax1 0x0009
547 #define T3_SSID_BROADCOM_BCM95703Ax2 0x8009
549 /* 3COM subsystem/subvendor IDs. */
550 #define T3_SVID_3COM 0x10b7
552 #define T3_SSID_3COM_3C996T 0x1000
553 #define T3_SSID_3COM_3C996BT 0x1006
554 #define T3_SSID_3COM_3C996CT 0x1002
555 #define T3_SSID_3COM_3C997T 0x1003
556 #define T3_SSID_3COM_3C1000T 0x1007
557 #define T3_SSID_3COM_3C940BR01 0x1008
560 #define T3_SSID_3COM_3C996SX 0x1004
561 #define T3_SSID_3COM_3C997SX 0x1005
564 /* Dell subsystem/subvendor IDs. */
566 #define T3_SVID_DELL 0x1028
568 #define T3_SSID_DELL_VIPER 0x00d1
569 #define T3_SSID_DELL_JAGUAR 0x0106
570 #define T3_SSID_DELL_MERLOT 0x0109
571 #define T3_SSID_DELL_SLIM_MERLOT 0x010a
573 /* Compaq subsystem/subvendor IDs */
575 #define T3_SVID_COMPAQ 0x0e11
577 #define T3_SSID_COMPAQ_BANSHEE 0x007c
578 #define T3_SSID_COMPAQ_BANSHEE_2 0x009a
579 #define T3_SSID_COMPAQ_CHANGELING 0x007d
580 #define T3_SSID_COMPAQ_NC7780 0x0085
581 #define T3_SSID_COMPAQ_NC7780_2 0x0099
583 #define T3_PCIE_CAPABILITY_ID_REG 0xD0
584 #define T3_PCIE_CAPABILITY_ID 0x10
586 #define T3_PCIE_CAPABILITY_REG 0xD2
588 /******************************************************************************/
590 /******************************************************************************/
592 /* Control register. */
593 #define PHY_CTRL_REG 0x00
595 #define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13)
596 #define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE
597 #define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13
598 #define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6
599 #define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7
600 #define PHY_CTRL_FULL_DUPLEX_MODE BIT_8
601 #define PHY_CTRL_RESTART_AUTO_NEG BIT_9
602 #define PHY_CTRL_ISOLATE_PHY BIT_10
603 #define PHY_CTRL_LOWER_POWER_MODE BIT_11
604 #define PHY_CTRL_AUTO_NEG_ENABLE BIT_12
605 #define PHY_CTRL_LOOPBACK_MODE BIT_14
606 #define PHY_CTRL_PHY_RESET BIT_15
609 /* Status register. */
610 #define PHY_STATUS_REG 0x01
612 #define PHY_STATUS_LINK_PASS BIT_2
613 #define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5
616 /* Phy Id registers. */
617 #define PHY_ID1_REG 0x02
618 #define PHY_ID1_OUI_MASK 0xffff
620 #define PHY_ID2_REG 0x03
621 #define PHY_ID2_REV_MASK 0x000f
622 #define PHY_ID2_MODEL_MASK 0x03f0
623 #define PHY_ID2_OUI_MASK 0xfc00
626 /* Auto-negotiation advertisement register. */
627 #define PHY_AN_AD_REG 0x04
629 #define PHY_AN_AD_ASYM_PAUSE BIT_11
630 #define PHY_AN_AD_PAUSE_CAPABLE BIT_10
631 #define PHY_AN_AD_10BASET_HALF BIT_5
632 #define PHY_AN_AD_10BASET_FULL BIT_6
633 #define PHY_AN_AD_100BASETX_HALF BIT_7
634 #define PHY_AN_AD_100BASETX_FULL BIT_8
635 #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01
637 /* Defines for 5714 family fiber on the 546x phy*/
639 #define PHY_AN_AD_1000XFULL 0x20
640 #define PHY_AN_AD_1000XHALF 0x40
641 #define PHY_AN_AD_1000XPAUSE 0x80
642 #define PHY_AN_AD_1000XPSE_ASYM 0x100
643 #define PHY_AN_AD_1000XREM_FAULT_OFFLINE 0x2000
644 #define PHY_AN_AD_1000XREM_FAULT_AN_ERROR 0x3000
646 #define PHY_AN_AD_ALL_SPEEDS (PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |\
647 PHY_AN_AD_100BASETX_HALF | PHY_AN_AD_100BASETX_FULL)
649 /* Auto-negotiation Link Partner Ability register. */
650 #define PHY_LINK_PARTNER_ABILITY_REG 0x05
652 #define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11
653 #define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10
656 /* Auto-negotiation expansion register. */
657 #define PHY_AN_EXPANSION_REG 0x06
661 /******************************************************************************/
662 /* BCM5400 and BCM5401 phy info. */
663 /******************************************************************************/
665 #define PHY_DEVICE_ID 1
667 /* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */
668 #define PHY_UNKNOWN_PHY 0x00000000
669 #define PHY_BCM5400_PHY_ID 0x60008040
670 #define PHY_BCM5401_PHY_ID 0x60008050
671 #define PHY_BCM5411_PHY_ID 0x60008070
672 #define PHY_BCM5701_PHY_ID 0x60008110
673 #define PHY_BCM5703_PHY_ID 0x60008160
674 #define PHY_BCM5704_PHY_ID 0x60008190
675 #define PHY_BCM5705_PHY_ID 0x600081a0
676 #define PHY_BCM5750_PHY_ID 0x60008180
677 #define PHY_BCM8002_PHY_ID 0x60010140
678 #define PHY_BCM5714_PHY_ID 0x60008340
679 #define PHY_BCM5780_PHY_ID 0x60008350
680 #define PHY_BCM5752_PHY_ID 0x60008100
682 #define PHY_BCM5401_B0_REV 0x1
683 #define PHY_BCM5401_B2_REV 0x3
684 #define PHY_BCM5401_C0_REV 0x6
686 #define PHY_ID_OUI_MASK 0xfffffc00
687 #define PHY_ID_MODEL_MASK 0x000003f0
688 #define PHY_ID_REV_MASK 0x0000000f
689 #define PHY_ID_MASK (PHY_ID_OUI_MASK | \
692 #define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
693 (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
694 (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
695 (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \
696 (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \
697 (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
698 (((x) & PHY_ID_MASK) != PHY_BCM5705_PHY_ID) && \
699 (((x) & PHY_ID_MASK) != PHY_BCM5750_PHY_ID) && \
700 (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID) && \
701 (((x) & PHY_ID_MASK) != PHY_BCM5714_PHY_ID) && \
702 (((x) & PHY_ID_MASK) != PHY_BCM5780_PHY_ID) && \
703 (((x) & PHY_ID_MASK) != PHY_BCM5752_PHY_ID))
705 /* 1000Base-T control register. */
706 #define BCM540X_1000BASET_CTRL_REG 0x09
708 #define BCM540X_AN_AD_1000BASET_HALF BIT_8
709 #define BCM540X_AN_AD_1000BASET_FULL BIT_9
710 #define BCM540X_CONFIG_AS_MASTER BIT_11
711 #define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12
713 #define BCM540X_AN_AD_ALL_1G_SPEEDS (BCM540X_AN_AD_1000BASET_HALF | \
714 BCM540X_AN_AD_1000BASET_FULL)
716 /* Extended control register. */
717 #define BCM540X_EXT_CTRL_REG 0x10
719 #define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1
720 #define BCM540X_EXT_CTRL_FORCE_LED_OFF BIT_3
721 #define BCM540X_EXT_CTRL_TBI BIT_15
723 /* PHY extended status register. */
724 #define BCM540X_EXT_STATUS_REG 0x11
726 #define BCM540X_EXT_STATUS_LINK_PASS BIT_8
729 /* DSP Coefficient Read/Write Port. */
730 #define BCM540X_DSP_RW_PORT 0x15
733 /* DSP Coeficient Address Register. */
734 #define BCM540X_DSP_ADDRESS_REG 0x17
736 #define BCM540X_DSP_TAP_NUMBER_MASK 0x00
737 #define BCM540X_DSP_AGC_A 0x00
738 #define BCM540X_DSP_AGC_B 0x01
739 #define BCM540X_DSP_MSE_PAIR_STATUS 0x02
740 #define BCM540X_DSP_SOFT_DECISION 0x03
741 #define BCM540X_DSP_PHASE_REG 0x04
742 #define BCM540X_DSP_SKEW 0x05
743 #define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06
744 #define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07
745 #define BCM540X_DSP_LAST_ECHO 0x08
746 #define BCM540X_DSP_FREQUENCY 0x09
747 #define BCM540X_DSP_PLL_BANDWIDTH 0x0a
748 #define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b
750 #define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11)
751 #define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11)
752 #define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11)
753 #define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11)
754 #define BCM540X_DSP_FILTER_FEXT0 BIT_11
755 #define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10)
756 #define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10)
757 #define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10)
758 #define BCM540X_DSP_FILTER_NEXT0 BIT_10
759 #define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9)
760 #define BCM540X_DSP_FILTER_DFE BIT_9
761 #define BCM540X_DSP_FILTER_FFE BIT_8
763 #define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12
765 #define BCM540X_DSP_SEL_CH_0 BIT_NONE
766 #define BCM540X_DSP_SEL_CH_1 BIT_13
767 #define BCM540X_DSP_SEL_CH_2 BIT_14
768 #define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14)
770 #define BCM540X_CONTROL_ALL_CHANNELS BIT_15
773 /* Auxilliary Control Register (Shadow Register) */
774 #define BCM5401_AUX_CTRL 0x18
776 #define BCM5401_SHADOW_SEL_MASK 0x7
777 #define BCM5401_SHADOW_SEL_NORMAL 0x00
778 #define BCM5401_SHADOW_SEL_10BASET 0x01
779 #define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02
780 #define BCM5401_SHADOW_SEL_IP_PHONE 0x03
781 #define BCM5401_SHADOW_SEL_MISC_TEST1 0x04
782 #define BCM5401_SHADOW_SEL_MISC_TEST2 0x05
783 #define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06
786 /* Shadow register selector == '000' */
787 #define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3
788 #define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4
789 #define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5
790 #define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6
791 #define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7
792 #define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE
793 #define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8
794 #define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9
795 #define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9)
796 #define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10
797 #define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11
798 #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE
799 #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12
800 #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13
801 #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13)
802 #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14
803 #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15
806 /* Auxilliary status summary. */
807 #define BCM540X_AUX_STATUS_REG 0x19
809 #define BCM540X_AUX_LINK_PASS BIT_2
810 #define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10)
811 #define BCM540X_AUX_10BASET_HD BIT_8
812 #define BCM540X_AUX_10BASET_FD BIT_9
813 #define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9)
814 #define BCM540X_AUX_100BASET4 BIT_10
815 #define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10)
816 #define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10)
817 #define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10)
820 /* Interrupt status. */
821 #define BCM540X_INT_STATUS_REG 0x1a
823 #define BCM540X_INT_LINK_CHANGE BIT_1
824 #define BCM540X_INT_SPEED_CHANGE BIT_2
825 #define BCM540X_INT_DUPLEX_CHANGE BIT_3
826 #define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10
829 /* Interrupt mask register. */
830 #define BCM540X_INT_MASK_REG 0x1b
834 /******************************************************************************/
835 /* Register definitions. */
836 /******************************************************************************/
838 typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER;
839 typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER;
840 typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;
843 /* Big endian format. */
844 T3_32BIT_REGISTER High;
845 T3_32BIT_REGISTER Low;
846 } T3_64BIT_REGISTER, *PT3_64BIT_REGISTER;
848 typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
850 #define T3_NUM_OF_DMA_DESC 256
851 #define T3_NUM_OF_MBUF 768
855 T3_64BIT_REGISTER host_addr;
856 T3_32BIT_REGISTER nic_mbuf;
857 T3_16BIT_REGISTER len;
858 T3_16BIT_REGISTER cqid_sqid;
859 T3_32BIT_REGISTER flags;
860 T3_32BIT_REGISTER opaque1;
861 T3_32BIT_REGISTER opaque2;
862 T3_32BIT_REGISTER opaque3;
863 }T3_DMA_DESC, *PT3_DMA_DESC;
867 /******************************************************************************/
868 /* Ring control block. */
869 /******************************************************************************/
872 T3_64BIT_REGISTER HostRingAddr;
876 #ifdef BIG_ENDIAN_HOST
877 T3_16BIT_REGISTER MaxLen;
878 T3_16BIT_REGISTER Flags;
879 #else /* BIG_ENDIAN_HOST */
880 T3_16BIT_REGISTER Flags;
881 T3_16BIT_REGISTER MaxLen;
885 T3_32BIT_REGISTER MaxLen_Flags;
888 T3_32BIT_REGISTER NicRingAddr;
891 #define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0
892 #define T3_RCB_FLAG_RING_DISABLED BIT_1
896 /******************************************************************************/
898 /******************************************************************************/
901 * Size of status block is actually 0x50 bytes. Use 0x80 bytes for
902 * cache line alignment.
904 #define T3_STATUS_BLOCK_SIZE 0x80
907 volatile LM_UINT32 Status;
908 #define STATUS_BLOCK_UPDATED BIT_0
909 #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1
910 #define STATUS_BLOCK_ERROR BIT_2
912 volatile LM_UINT32 StatusTag;
914 #ifdef BIG_ENDIAN_HOST
915 volatile LM_UINT16 RcvStdConIdx;
916 volatile LM_UINT16 RcvJumboConIdx;
918 volatile LM_UINT16 Reserved2;
919 volatile LM_UINT16 RcvMiniConIdx;
922 volatile LM_UINT16 SendConIdx; /* Send consumer index. */
923 volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
925 #else /* BIG_ENDIAN_HOST */
926 volatile LM_UINT16 RcvJumboConIdx;
927 volatile LM_UINT16 RcvStdConIdx;
929 volatile LM_UINT16 RcvMiniConIdx;
930 volatile LM_UINT16 Reserved2;
933 volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
934 volatile LM_UINT16 SendConIdx; /* Send consumer index. */
937 } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
941 /******************************************************************************/
942 /* Receive buffer descriptors. */
943 /******************************************************************************/
946 T3_64BIT_HOST_ADDR HostAddr;
948 #ifdef BIG_ENDIAN_HOST
949 volatile LM_UINT16 Index;
950 volatile LM_UINT16 Len;
952 volatile LM_UINT16 Type;
953 volatile LM_UINT16 Flags;
955 volatile LM_UINT16 IpCksum;
956 volatile LM_UINT16 TcpUdpCksum;
958 volatile LM_UINT16 ErrorFlag;
959 volatile LM_UINT16 VlanTag;
960 #else /* BIG_ENDIAN_HOST */
961 volatile LM_UINT16 Len;
962 volatile LM_UINT16 Index;
964 volatile LM_UINT16 Flags;
965 volatile LM_UINT16 Type;
967 volatile LM_UINT16 TcpUdpCksum;
968 volatile LM_UINT16 IpCksum;
970 volatile LM_UINT16 VlanTag;
971 volatile LM_UINT16 ErrorFlag;
974 volatile LM_UINT32 Reserved;
975 volatile LM_UINT32 Opaque;
976 } T3_RCV_BD, *PT3_RCV_BD;
980 T3_64BIT_HOST_ADDR HostAddr[3];
982 #ifdef BIG_ENDIAN_HOST
988 #else /* BIG_ENDIAN_HOST */
997 } T3_EXT_RCV_BD, *PT3_EXT_RCV_BD;
1001 #define RCV_BD_ERR_BAD_CRC 0x0001
1002 #define RCV_BD_ERR_COLL_DETECT 0x0002
1003 #define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004
1004 #define RCV_BD_ERR_PHY_DECODE_ERR 0x0008
1005 #define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010
1006 #define RCV_BD_ERR_MAC_ABORT 0x0020
1007 #define RCV_BD_ERR_LEN_LT_64 0x0040
1008 #define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080
1009 #define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100
1012 /* Buffer descriptor flags. */
1013 #define RCV_BD_FLAG_END 0x0004
1014 #define RCV_BD_FLAG_JUMBO_RING 0x0020
1015 #define RCV_BD_FLAG_VLAN_TAG 0x0040
1016 #define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400
1017 #define RCV_BD_FLAG_MINI_RING 0x0800
1018 #define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000
1019 #define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000
1020 #define RCV_BD_FLAG_TCP_PACKET 0x4000
1024 /******************************************************************************/
1025 /* Send buffer descriptor. */
1026 /******************************************************************************/
1029 T3_64BIT_HOST_ADDR HostAddr;
1033 #ifdef BIG_ENDIAN_HOST
1036 #else /* BIG_ENDIAN_HOST */
1042 LM_UINT32 Len_Flags;
1047 #ifdef BIG_ENDIAN_HOST
1050 #else /* BIG_ENDIAN_HOST */
1058 } T3_SND_BD, *PT3_SND_BD;
1061 /* Send buffer descriptor flags. */
1062 #define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001
1063 #define SND_BD_FLAG_IP_CKSUM 0x0002
1064 #define SND_BD_FLAG_END 0x0004
1065 #define SND_BD_FLAG_IP_FRAG 0x0008
1066 #define SND_BD_FLAG_IP_FRAG_END 0x0010
1067 #define SND_BD_FLAG_VLAN_TAG 0x0040
1068 #define SND_BD_FLAG_COAL_NOW 0x0080
1069 #define SND_BD_FLAG_CPU_PRE_DMA 0x0100
1070 #define SND_BD_FLAG_CPU_POST_DMA 0x0200
1071 #define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000
1072 #define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000
1073 #define SND_BD_FLAG_DONT_GEN_CRC 0x8000
1076 typedef struct T3_MBUF_FRAME_DESC {
1077 #ifdef BIG_ENDIAN_HOST
1078 LM_UINT32 status_control;
1090 LM_UINT16 ip_hdr_start;
1091 LM_UINT16 tcp_udp_hdr_start;
1099 LM_UINT16 data_start;
1108 LM_UINT16 ip_checksum;
1109 LM_UINT16 tcp_udp_checksum;
1117 LM_UINT16 pseudo_checksum;
1118 LM_UINT16 checksum_status;
1126 LM_UINT16 rule_match;
1136 LM_UINT16 reserved2;
1143 LM_UINT32 reserved3;
1144 LM_UINT32 reserved4;
1146 LM_UINT32 status_control;
1158 LM_UINT16 tcp_udp_hdr_start;
1159 LM_UINT16 ip_hdr_start;
1168 LM_UINT16 data_start;
1176 LM_UINT16 tcp_udp_checksum;
1177 LM_UINT16 ip_checksum;
1185 LM_UINT16 checksum_status;
1186 LM_UINT16 pseudo_checksum;
1196 LM_UINT16 rule_match;
1205 LM_UINT16 reserved2;
1211 LM_UINT32 reserved3;
1212 LM_UINT32 reserved4;
1214 }T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC;
1216 typedef struct T3_MBUF_HDR {
1221 unsigned int reserved1:7;
1222 unsigned int next_mbuf:16;
1223 unsigned int length:7;
1229 LM_UINT32 next_frame_ptr;
1230 }T3_MBUF_HDR, *PT3_MBUF_HDR;
1232 typedef struct T3_MBUF
1238 T3_MBUF_FRAME_DESC frame_hdr;
1246 }T3_MBUF, *PT3_MBUF;
1248 #define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7)
1249 #define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
1253 /******************************************************************************/
1254 /* Statistics block. */
1255 /******************************************************************************/
1258 LM_UINT8 Reserved0[0x400-0x300];
1260 /* Statistics maintained by Receive MAC. */
1261 T3_64BIT_REGISTER ifHCInOctets;
1262 T3_64BIT_REGISTER Reserved1;
1263 T3_64BIT_REGISTER etherStatsFragments;
1264 T3_64BIT_REGISTER ifHCInUcastPkts;
1265 T3_64BIT_REGISTER ifHCInMulticastPkts;
1266 T3_64BIT_REGISTER ifHCInBroadcastPkts;
1267 T3_64BIT_REGISTER dot3StatsFCSErrors;
1268 T3_64BIT_REGISTER dot3StatsAlignmentErrors;
1269 T3_64BIT_REGISTER xonPauseFramesReceived;
1270 T3_64BIT_REGISTER xoffPauseFramesReceived;
1271 T3_64BIT_REGISTER macControlFramesReceived;
1272 T3_64BIT_REGISTER xoffStateEntered;
1273 T3_64BIT_REGISTER dot3StatsFramesTooLong;
1274 T3_64BIT_REGISTER etherStatsJabbers;
1275 T3_64BIT_REGISTER etherStatsUndersizePkts;
1276 T3_64BIT_REGISTER inRangeLengthError;
1277 T3_64BIT_REGISTER outRangeLengthError;
1278 T3_64BIT_REGISTER etherStatsPkts64Octets;
1279 T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
1280 T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
1281 T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
1282 T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
1283 T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
1284 T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
1285 T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
1286 T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
1287 T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
1289 T3_64BIT_REGISTER Unused1[37];
1291 /* Statistics maintained by Transmit MAC. */
1292 T3_64BIT_REGISTER ifHCOutOctets;
1293 T3_64BIT_REGISTER Reserved2;
1294 T3_64BIT_REGISTER etherStatsCollisions;
1295 T3_64BIT_REGISTER outXonSent;
1296 T3_64BIT_REGISTER outXoffSent;
1297 T3_64BIT_REGISTER flowControlDone;
1298 T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
1299 T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
1300 T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
1301 T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
1302 T3_64BIT_REGISTER Reserved3;
1303 T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
1304 T3_64BIT_REGISTER dot3StatsLateCollisions;
1305 T3_64BIT_REGISTER dot3Collided2Times;
1306 T3_64BIT_REGISTER dot3Collided3Times;
1307 T3_64BIT_REGISTER dot3Collided4Times;
1308 T3_64BIT_REGISTER dot3Collided5Times;
1309 T3_64BIT_REGISTER dot3Collided6Times;
1310 T3_64BIT_REGISTER dot3Collided7Times;
1311 T3_64BIT_REGISTER dot3Collided8Times;
1312 T3_64BIT_REGISTER dot3Collided9Times;
1313 T3_64BIT_REGISTER dot3Collided10Times;
1314 T3_64BIT_REGISTER dot3Collided11Times;
1315 T3_64BIT_REGISTER dot3Collided12Times;
1316 T3_64BIT_REGISTER dot3Collided13Times;
1317 T3_64BIT_REGISTER dot3Collided14Times;
1318 T3_64BIT_REGISTER dot3Collided15Times;
1319 T3_64BIT_REGISTER ifHCOutUcastPkts;
1320 T3_64BIT_REGISTER ifHCOutMulticastPkts;
1321 T3_64BIT_REGISTER ifHCOutBroadcastPkts;
1322 T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
1323 T3_64BIT_REGISTER ifOutDiscards;
1324 T3_64BIT_REGISTER ifOutErrors;
1326 T3_64BIT_REGISTER Unused2[31];
1328 /* Statistics maintained by Receive List Placement. */
1329 T3_64BIT_REGISTER COSIfHCInPkts[16];
1330 T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
1331 T3_64BIT_REGISTER nicDmaWriteQueueFull;
1332 T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
1333 T3_64BIT_REGISTER nicNoMoreRxBDs;
1334 T3_64BIT_REGISTER ifInDiscards;
1335 T3_64BIT_REGISTER ifInErrors;
1336 T3_64BIT_REGISTER nicRecvThresholdHit;
1338 T3_64BIT_REGISTER Unused3[9];
1340 /* Statistics maintained by Send Data Initiator. */
1341 T3_64BIT_REGISTER COSIfHCOutPkts[16];
1342 T3_64BIT_REGISTER nicDmaReadQueueFull;
1343 T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
1344 T3_64BIT_REGISTER nicSendDataCompQueueFull;
1346 /* Statistics maintained by Host Coalescing. */
1347 T3_64BIT_REGISTER nicRingSetSendProdIndex;
1348 T3_64BIT_REGISTER nicRingStatusUpdate;
1349 T3_64BIT_REGISTER nicInterrupts;
1350 T3_64BIT_REGISTER nicAvoidedInterrupts;
1351 T3_64BIT_REGISTER nicSendThresholdHit;
1353 LM_UINT8 Reserved4[0xb00-0x9c0];
1354 } T3_STATS_BLOCK, *PT3_STATS_BLOCK;
1358 /******************************************************************************/
1359 /* PCI configuration registers. */
1360 /******************************************************************************/
1363 T3_16BIT_REGISTER VendorId;
1364 T3_16BIT_REGISTER DeviceId;
1366 T3_16BIT_REGISTER Command;
1367 T3_16BIT_REGISTER Status;
1369 T3_32BIT_REGISTER ClassCodeRevId;
1371 T3_8BIT_REGISTER CacheLineSize;
1372 T3_8BIT_REGISTER LatencyTimer;
1373 T3_8BIT_REGISTER HeaderType;
1374 T3_8BIT_REGISTER Bist;
1376 T3_32BIT_REGISTER MemBaseAddrLow;
1377 T3_32BIT_REGISTER MemBaseAddrHigh;
1379 LM_UINT8 Unused1[20];
1381 T3_16BIT_REGISTER SubsystemVendorId;
1382 T3_16BIT_REGISTER SubsystemId;
1384 T3_32BIT_REGISTER RomBaseAddr;
1386 T3_8BIT_REGISTER PciXCapiblityPtr;
1387 LM_UINT8 Unused2[7];
1389 T3_8BIT_REGISTER IntLine;
1390 T3_8BIT_REGISTER IntPin;
1391 T3_8BIT_REGISTER MinGnt;
1392 T3_8BIT_REGISTER MaxLat;
1394 T3_8BIT_REGISTER PciXCapabilities;
1395 T3_8BIT_REGISTER PmCapabilityPtr;
1396 T3_16BIT_REGISTER PciXCommand;
1397 #define PXC_MAX_READ_BYTE_COUNT_MASK (BIT_3 | BIT_2)
1398 #define PXC_MAX_READ_BYTE_COUNT_512 (0)
1399 #define PXC_MAX_READ_BYTE_COUNT_1024 (BIT_2)
1400 #define PXC_MAX_READ_BYTE_COUNT_2048 (BIT_3)
1401 #define PXC_MAX_READ_BYTE_COUNT_4096 (BIT_3 | BIT_2)
1403 T3_32BIT_REGISTER PciXStatus;
1405 T3_8BIT_REGISTER PmCapabilityId;
1406 T3_8BIT_REGISTER VpdCapabilityPtr;
1407 T3_16BIT_REGISTER PmCapabilities;
1409 T3_16BIT_REGISTER PmCtrlStatus;
1410 #define PM_CTRL_PME_STATUS BIT_15
1411 #define PM_CTRL_PME_ENABLE BIT_8
1412 #define PM_CTRL_PME_POWER_STATE_D0 0
1413 #define PM_CTRL_PME_POWER_STATE_D1 1
1414 #define PM_CTRL_PME_POWER_STATE_D2 2
1415 #define PM_CTRL_PME_POWER_STATE_D3H 3
1417 T3_8BIT_REGISTER BridgeSupportExt;
1418 T3_8BIT_REGISTER PmData;
1420 T3_8BIT_REGISTER VpdCapabilityId;
1421 T3_8BIT_REGISTER MsiCapabilityPtr;
1422 T3_16BIT_REGISTER VpdAddrFlag;
1423 #define VPD_FLAG_WRITE (1 << 15)
1424 #define VPD_FLAG_RW_MASK (1 << 15)
1425 #define VPD_FLAG_READ 0
1428 T3_32BIT_REGISTER VpdData;
1430 T3_8BIT_REGISTER MsiCapabilityId;
1431 T3_8BIT_REGISTER NextCapabilityPtr;
1432 T3_16BIT_REGISTER MsiCtrl;
1433 #define MSI_CTRL_64BIT_CAP (1 << 7)
1434 #define MSI_CTRL_MSG_ENABLE(x) (x << 4)
1435 #define MSI_CTRL_MSG_CAP(x) (x << 1)
1436 #define MSI_CTRL_ENABLE (1 << 0)
1439 T3_32BIT_REGISTER MsiAddrLow;
1440 T3_32BIT_REGISTER MsiAddrHigh;
1442 T3_16BIT_REGISTER MsiData;
1443 T3_16BIT_REGISTER Unused3;
1445 T3_32BIT_REGISTER MiscHostCtrl;
1446 #define MISC_HOST_CTRL_CLEAR_INT BIT_0
1447 #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1
1448 #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2
1449 #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3
1450 #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4
1451 #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5
1452 #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6
1453 #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7
1454 #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8
1455 #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9
1457 T3_32BIT_REGISTER DmaReadWriteCtrl;
1458 #define DMA_CTRL_WRITE_CMD 0x70000000
1459 #define DMA_CTRL_WRITE_BOUNDARY_64_PCIE 0x10000000
1460 #define DMA_CTRL_WRITE_BOUNDARY_128_PCIE 0x30000000
1461 #define DMA_CTRL_WRITE_BOUNDARY_DISABLE_PCIE 0x70000000
1462 #define DMA_CTRL_READ_CMD 0x06000000
1465 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000
1466 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000
1468 #define DMA_CTRL_PCIX_READ_WATERMARK_MASK (BIT_18 | BIT_17 | BIT_16)
1469 #define DMA_CTRL_PCIX_READ_WATERMARK_64 (0)
1470 #define DMA_CTRL_PCIX_READ_WATERMARK_128 (BIT_16)
1471 #define DMA_CTRL_PCIX_READ_WATERMARK_256 (BIT_17)
1472 #define DMA_CTRL_PCIX_READ_WATERMARK_384 (BIT_17 | BIT_16)
1473 #define DMA_CTRL_PCIX_READ_WATERMARK_512 (BIT_18)
1474 #define DMA_CTRL_PCIX_READ_WATERMARK_1024 (BIT_18 | BIT_16)
1475 #define DMA_CTRL_PCIX_READ_WATERMARK_1536X (BIT_18 | BIT_17)
1476 #define DMA_CTRL_PCIX_READ_WATERMARK_1536 (BIT_18 | BIT_17 | BIT_16)
1478 #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13)
1479 #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0
1480 #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11
1481 #define DMA_CTRL_WRITE_BOUNDARY_128_PCIX BIT_11
1482 #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12
1483 #define DMA_CTRL_WRITE_BOUNDARY_256_PCIX BIT_12
1484 #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11)
1485 #define DMA_CTRL_WRITE_BOUNDARY_384_PCIX (BIT_12 | BIT_11)
1486 #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13
1487 #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11)
1488 #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12)
1489 #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11)
1490 #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14
1492 #define DMA_CTRL_READ_BOUNDARY_MASK (BIT_10 | BIT_9 | BIT_8)
1493 #define DMA_CTRL_READ_BOUNDARY_DISABLE 0
1494 #define DMA_CTRL_READ_BOUNDARY_16 BIT_8
1495 #define DMA_CTRL_READ_BOUNDARY_128_PCIX BIT_8
1496 #define DMA_CTRL_READ_BOUNDARY_32 BIT_9
1497 #define DMA_CTRL_READ_BOUNDARY_256_PCIX BIT_9
1498 #define DMA_CTRL_READ_BOUNDARY_64 (BIT_9 | BIT_8)
1499 #define DMA_CTRL_READ_BOUNDARY_384_PCIX (BIT_9 | BIT_8)
1500 #define DMA_CTRL_READ_BOUNDARY_128 BIT_10
1501 #define DMA_CTRL_READ_BOUNDARY_256 (BIT_10 | BIT_8)
1502 #define DMA_CTRL_READ_BOUNDARY_512 (BIT_10 | BIT_9)
1503 #define DMA_CTRL_READ_BOUNDARY_1024 (BIT_10 | BIT_9 | BIT_8)
1505 T3_32BIT_REGISTER PciState;
1506 #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0
1507 #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1
1508 #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2
1509 #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3
1510 #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
1511 #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5
1512 #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6
1513 #define T3_PCI_STATE_FLAT_VIEW BIT_8
1514 #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13
1516 T3_32BIT_REGISTER ClockCtrl;
1517 #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11
1518 #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10
1519 #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9
1521 T3_32BIT_REGISTER RegBaseAddr;
1523 T3_32BIT_REGISTER MemWindowBaseAddr;
1526 /* These registers are ONLY visible to NIC CPU */
1527 T3_32BIT_REGISTER PowerConsumed;
1528 T3_32BIT_REGISTER PowerDissipated;
1529 #else /* NIC_CPU_VIEW */
1530 T3_32BIT_REGISTER RegData;
1531 T3_32BIT_REGISTER MemWindowData;
1532 #endif /* !NIC_CPU_VIEW */
1534 T3_32BIT_REGISTER ModeCtrl;
1536 T3_32BIT_REGISTER MiscCfg;
1538 T3_32BIT_REGISTER MiscLocalCtrl;
1540 T3_32BIT_REGISTER Unused4;
1542 /* NOTE: Big/Little-endian clarification needed. Are these register */
1543 /* in big or little endian formate. */
1544 T3_64BIT_REGISTER StdRingProdIdx;
1545 T3_64BIT_REGISTER RcvRetRingConIdx;
1546 T3_64BIT_REGISTER SndProdIdx;
1548 T3_32BIT_REGISTER Unused5[2]; /* 0xb0-0xb7 */
1550 T3_32BIT_REGISTER DualMacCtrl; /* 0xb8 */
1551 #define T3_DUAL_MAC_CH_CTRL_MASK (BIT_1 | BIT_0)
1552 #define T3_DUAL_MAC_ID BIT_2
1554 T3_32BIT_REGISTER MacMessageExchangeOutput; /* 0xbc */
1555 T3_32BIT_REGISTER MacMessageExchangeInput; /* 0xc0 */
1557 T3_32BIT_REGISTER FunctionEventMask; /* 0xc4 */
1559 T3_32BIT_REGISTER Unused6[4]; /* 0xc8-0xd7 */
1561 T3_32BIT_REGISTER DeviceCtrl; /* 0xd8 */
1562 #define MAX_PAYLOAD_SIZE_MASK 0x0e0
1564 LM_UINT8 Unused7[36];
1566 } T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION;
1568 #define PCIX_CMD_MAX_SPLIT_MASK 0x00700000
1569 #define PCIX_CMD_MAX_SPLIT_SHL 20
1570 #define PCIX_CMD_MAX_BURST_MASK 0x000c0000
1571 #define PCIX_CMD_MAX_BURST_SHL 18
1572 #define PCIX_CMD_MAX_BURST_CPIOB 2
1574 /******************************************************************************/
1575 /* Mac control registers. */
1576 /******************************************************************************/
1579 /* MAC mode control. */
1580 T3_32BIT_REGISTER Mode;
1581 #define MAC_MODE_GLOBAL_RESET BIT_0
1582 #define MAC_MODE_HALF_DUPLEX BIT_1
1583 #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3)
1584 #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3)
1585 #define MAC_MODE_PORT_MODE_GMII BIT_3
1586 #define MAC_MODE_PORT_MODE_MII BIT_2
1587 #define MAC_MODE_PORT_MODE_NONE BIT_NONE
1588 #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4
1589 #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7
1590 #define MAC_MODE_TX_BURSTING BIT_8
1591 #define MAC_MODE_MAX_DEFER BIT_9
1592 #define MAC_MODE_LINK_POLARITY BIT_10
1593 #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11
1594 #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12
1595 #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13
1596 #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14
1597 #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15
1598 #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16
1599 #define MAC_MODE_SEND_CONFIGS BIT_17
1600 #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18
1601 #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19
1602 #define MAC_MODE_ENABLE_MIP BIT_20
1603 #define MAC_MODE_ENABLE_TDE BIT_21
1604 #define MAC_MODE_ENABLE_RDE BIT_22
1605 #define MAC_MODE_ENABLE_FHDE BIT_23
1608 T3_32BIT_REGISTER Status;
1609 #define MAC_STATUS_PCS_SYNCED BIT_0
1610 #define MAC_STATUS_SIGNAL_DETECTED BIT_1
1611 #define MAC_STATUS_RECEIVING_CFG BIT_2
1612 #define MAC_STATUS_CFG_CHANGED BIT_3
1613 #define MAC_STATUS_SYNC_CHANGED BIT_4
1614 #define MAC_STATUS_PORT_DECODE_ERROR BIT_10
1615 #define MAC_STATUS_LINK_STATE_CHANGED BIT_12
1616 #define MAC_STATUS_MI_COMPLETION BIT_22
1617 #define MAC_STATUS_MI_INTERRUPT BIT_23
1618 #define MAC_STATUS_AP_ERROR BIT_24
1619 #define MAC_STATUS_ODI_ERROR BIT_25
1620 #define MAC_STATUS_RX_STATS_OVERRUN BIT_26
1621 #define MAC_STATUS_TX_STATS_OVERRUN BIT_27
1624 T3_32BIT_REGISTER MacEvent;
1625 #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10
1626 #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12
1627 #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22
1628 #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23
1629 #define MAC_EVENT_ENABLE_AP_ERROR BIT_24
1630 #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25
1631 #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26
1632 #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27
1635 T3_32BIT_REGISTER LedCtrl;
1636 #define LED_CTRL_OVERRIDE_LINK_LED BIT_0
1637 #define LED_CTRL_1000MBPS_LED_ON BIT_1
1638 #define LED_CTRL_100MBPS_LED_ON BIT_2
1639 #define LED_CTRL_10MBPS_LED_ON BIT_3
1640 #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4
1641 #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5
1642 #define LED_CTRL_TRAFFIC_LED BIT_6
1643 #define LED_CTRL_1000MBPS_LED_STATUS BIT_7
1644 #define LED_CTRL_100MBPS_LED_STATUS BIT_8
1645 #define LED_CTRL_10MBPS_LED_STATUS BIT_9
1646 #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10
1647 #define LED_CTRL_MAC_MODE BIT_NONE
1648 #define LED_CTRL_PHY_MODE_1 BIT_11
1649 #define LED_CTRL_PHY_MODE_2 BIT_12
1650 #define LED_CTRL_SHASTA_MAC_MODE BIT_13
1651 #define LED_CTRL_SHARED_TRAFFIC_LINK BIT_14
1652 #define LED_CTRL_WIRELESS_COMBO BIT_15
1653 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
1654 #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19
1655 #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31
1657 /* MAC addresses. */
1659 T3_32BIT_REGISTER High; /* Upper 2 bytes. */
1660 T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
1663 /* ACPI Mbuf pointer. */
1664 T3_32BIT_REGISTER AcpiMbufPtr;
1666 /* ACPI Length and Offset. */
1667 T3_32BIT_REGISTER AcpiLengthOffset;
1668 #define ACPI_LENGTH_MASK 0xffff
1669 #define ACPI_OFFSET_MASK 0x0fff0000
1670 #define ACPI_LENGTH(x) x
1671 #define ACPI_OFFSET(x) ((x) << 16)
1673 /* Transmit random backoff. */
1674 T3_32BIT_REGISTER TxBackoffSeed;
1675 #define MAC_TX_BACKOFF_SEED_MASK 0x3ff
1678 T3_32BIT_REGISTER MtuSize;
1679 #define MAC_RX_MTU_MASK 0xffff
1681 /* Gigabit PCS Test. */
1682 T3_32BIT_REGISTER PcsTest;
1683 #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff
1684 #define MAC_PCS_TEST_ENABLE BIT_20
1686 /* Transmit Gigabit Auto-Negotiation. */
1687 T3_32BIT_REGISTER TxAutoNeg;
1688 #define MAC_AN_TX_AN_DATA_MASK 0xffff
1690 /* Receive Gigabit Auto-Negotiation. */
1691 T3_32BIT_REGISTER RxAutoNeg;
1692 #define MAC_AN_RX_AN_DATA_MASK 0xffff
1694 /* MI Communication. */
1695 T3_32BIT_REGISTER MiCom;
1696 #define MI_COM_CMD_MASK (BIT_26 | BIT_27)
1697 #define MI_COM_CMD_WRITE BIT_26
1698 #define MI_COM_CMD_READ BIT_27
1699 #define MI_COM_READ_FAILED BIT_28
1700 #define MI_COM_START BIT_29
1701 #define MI_COM_BUSY BIT_29
1703 #define MI_COM_PHY_ADDR_MASK 0x1f
1704 #define MI_COM_FIRST_PHY_ADDR_BIT 21
1706 #define MI_COM_PHY_REG_ADDR_MASK 0x1f
1707 #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16
1709 #define MI_COM_PHY_DATA_MASK 0xffff
1712 T3_32BIT_REGISTER MiStatus;
1713 #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0
1714 #define MI_STATUS_10MBPS BIT_1
1717 T3_32BIT_REGISTER MiMode;
1718 #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0
1719 #define MI_MODE_USE_SHORT_PREAMBLE BIT_1
1720 #define MI_MODE_AUTO_POLLING_ENABLE BIT_4
1721 #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15
1723 /* Auto-polling status. */
1724 T3_32BIT_REGISTER AutoPollStatus;
1725 #define AUTO_POLL_ERROR BIT_0
1727 /* Transmit MAC mode. */
1728 T3_32BIT_REGISTER TxMode;
1729 #define TX_MODE_RESET BIT_0
1730 #define TX_MODE_ENABLE BIT_1
1731 #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4
1732 #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5
1733 #define TX_MODE_ENABLE_LONG_PAUSE BIT_6
1735 /* Transmit MAC status. */
1736 T3_32BIT_REGISTER TxStatus;
1737 #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0
1738 #define TX_STATUS_SENT_XOFF BIT_1
1739 #define TX_STATUS_SENT_XON BIT_2
1740 #define TX_STATUS_LINK_UP BIT_3
1741 #define TX_STATUS_ODI_UNDERRUN BIT_4
1742 #define TX_STATUS_ODI_OVERRUN BIT_5
1744 /* Transmit MAC length. */
1745 T3_32BIT_REGISTER TxLengths;
1746 #define TX_LEN_SLOT_TIME_MASK 0xff
1747 #define TX_LEN_IPG_MASK 0x0f00
1748 #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13)
1750 /* Receive MAC mode. */
1751 T3_32BIT_REGISTER RxMode;
1752 #define RX_MODE_RESET BIT_0
1753 #define RX_MODE_ENABLE BIT_1
1754 #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2
1755 #define RX_MODE_KEEP_MAC_CONTROL BIT_3
1756 #define RX_MODE_KEEP_PAUSE BIT_4
1757 #define RX_MODE_ACCEPT_OVERSIZED BIT_5
1758 #define RX_MODE_ACCEPT_RUNTS BIT_6
1759 #define RX_MODE_LENGTH_CHECK BIT_7
1760 #define RX_MODE_PROMISCUOUS_MODE BIT_8
1761 #define RX_MODE_NO_CRC_CHECK BIT_9
1762 #define RX_MODE_KEEP_VLAN_TAG BIT_10
1764 /* Receive MAC status. */
1765 T3_32BIT_REGISTER RxStatus;
1766 #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0
1767 #define RX_STATUS_XOFF_RECEIVED BIT_1
1768 #define RX_STATUS_XON_RECEIVED BIT_2
1770 /* Hash registers. */
1771 T3_32BIT_REGISTER HashReg[4];
1773 /* Receive placement rules registers. */
1775 T3_32BIT_REGISTER Rule;
1776 T3_32BIT_REGISTER Value;
1779 #define RCV_DISABLE_RULE_MASK 0x7fffffff
1781 #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00
1782 #define REJECT_BROADCAST_RULE1_RULE 0xc2000000
1783 #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff
1785 #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01
1786 #define REJECT_BROADCAST_RULE2_RULE 0x86000004
1787 #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff
1789 #if INCLUDE_5701_AX_FIX
1790 #define RCV_LAST_RULE_IDX 0x04
1792 #define RCV_LAST_RULE_IDX 0x02
1795 T3_32BIT_REGISTER RcvRuleCfg;
1796 #define RX_RULE_DEFAULT_CLASS (1 << 3)
1798 T3_32BIT_REGISTER LowWaterMarkMaxRxFrame;
1800 LM_UINT8 Reserved1[24];
1802 T3_32BIT_REGISTER HashRegU[4];
1805 T3_32BIT_REGISTER High;
1806 T3_32BIT_REGISTER Low;
1809 T3_32BIT_REGISTER SerdesCfg;
1810 T3_32BIT_REGISTER SerdesStatus;
1812 LM_UINT8 Reserved2[24];
1814 T3_32BIT_REGISTER SgDigControl;
1815 T3_32BIT_REGISTER SgDigStatus;
1817 LM_UINT8 Reserved3[72];
1819 volatile LM_UINT8 TxMacState[16];
1820 volatile LM_UINT8 RxMacState[20];
1822 LM_UINT8 Reserved4[476];
1824 T3_32BIT_REGISTER ifHCOutOctets;
1825 T3_32BIT_REGISTER Reserved5;
1826 T3_32BIT_REGISTER etherStatsCollisions;
1827 T3_32BIT_REGISTER outXonSent;
1828 T3_32BIT_REGISTER outXoffSent;
1829 T3_32BIT_REGISTER Reserved6;
1830 T3_32BIT_REGISTER dot3StatsInternalMacTransmitErrors;
1831 T3_32BIT_REGISTER dot3StatsSingleCollisionFrames;
1832 T3_32BIT_REGISTER dot3StatsMultipleCollisionFrames;
1833 T3_32BIT_REGISTER dot3StatsDeferredTransmissions;
1834 T3_32BIT_REGISTER Reserved7;
1835 T3_32BIT_REGISTER dot3StatsExcessiveCollisions;
1836 T3_32BIT_REGISTER dot3StatsLateCollisions;
1837 T3_32BIT_REGISTER Reserved8[14];
1838 T3_32BIT_REGISTER ifHCOutUcastPkts;
1839 T3_32BIT_REGISTER ifHCOutMulticastPkts;
1840 T3_32BIT_REGISTER ifHCOutBroadcastPkts;
1841 T3_32BIT_REGISTER Reserved9[2];
1842 T3_32BIT_REGISTER ifHCInOctets;
1843 T3_32BIT_REGISTER Reserved10;
1844 T3_32BIT_REGISTER etherStatsFragments;
1845 T3_32BIT_REGISTER ifHCInUcastPkts;
1846 T3_32BIT_REGISTER ifHCInMulticastPkts;
1847 T3_32BIT_REGISTER ifHCInBroadcastPkts;
1848 T3_32BIT_REGISTER dot3StatsFCSErrors;
1849 T3_32BIT_REGISTER dot3StatsAlignmentErrors;
1850 T3_32BIT_REGISTER xonPauseFramesReceived;
1851 T3_32BIT_REGISTER xoffPauseFramesReceived;
1852 T3_32BIT_REGISTER macControlFramesReceived;
1853 T3_32BIT_REGISTER xoffStateEntered;
1854 T3_32BIT_REGISTER dot3StatsFramesTooLong;
1855 T3_32BIT_REGISTER etherStatsJabbers;
1856 T3_32BIT_REGISTER etherStatsUndersizePkts;
1858 T3_32BIT_REGISTER Reserved11[209];
1860 } T3_MAC_CONTROL, *PT3_MAC_CONTROL;
1864 /******************************************************************************/
1865 /* Send data initiator control registers. */
1866 /******************************************************************************/
1869 T3_32BIT_REGISTER Mode;
1870 #define T3_SND_DATA_IN_MODE_RESET BIT_0
1871 #define T3_SND_DATA_IN_MODE_ENABLE BIT_1
1872 #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2
1874 T3_32BIT_REGISTER Status;
1875 #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2
1877 T3_32BIT_REGISTER StatsCtrl;
1878 #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0
1879 #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1
1880 #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2
1881 #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3
1882 #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4
1884 T3_32BIT_REGISTER StatsEnableMask;
1886 T3_32BIT_REGISTER StatsIncMask;
1888 LM_UINT8 Reserved[108];
1890 T3_32BIT_REGISTER ClassOfServCnt[16];
1891 T3_32BIT_REGISTER DmaReadQFullCnt;
1892 T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
1893 T3_32BIT_REGISTER SdcQFullCnt;
1895 T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
1896 T3_32BIT_REGISTER StatusUpdatedCnt;
1897 T3_32BIT_REGISTER InterruptsCnt;
1898 T3_32BIT_REGISTER AvoidInterruptsCnt;
1899 T3_32BIT_REGISTER SendThresholdHitCnt;
1902 LM_UINT8 Unused[800];
1903 } T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
1907 /******************************************************************************/
1908 /* Send data completion control registers. */
1909 /******************************************************************************/
1912 T3_32BIT_REGISTER Mode;
1913 #define SND_DATA_COMP_MODE_RESET BIT_0
1914 #define SND_DATA_COMP_MODE_ENABLE BIT_1
1917 LM_UINT8 Unused[1020];
1918 } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
1922 /******************************************************************************/
1923 /* Send BD Ring Selector Control Registers. */
1924 /******************************************************************************/
1927 T3_32BIT_REGISTER Mode;
1928 #define SND_BD_SEL_MODE_RESET BIT_0
1929 #define SND_BD_SEL_MODE_ENABLE BIT_1
1930 #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2
1932 T3_32BIT_REGISTER Status;
1933 #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2
1935 T3_32BIT_REGISTER HwDiag;
1938 LM_UINT8 Unused1[52];
1940 /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
1941 T3_32BIT_REGISTER NicSendBdSelConIdx[16];
1944 LM_UINT8 Unused2[896];
1945 } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
1949 /******************************************************************************/
1950 /* Send BD initiator control registers. */
1951 /******************************************************************************/
1954 T3_32BIT_REGISTER Mode;
1955 #define SND_BD_IN_MODE_RESET BIT_0
1956 #define SND_BD_IN_MODE_ENABLE BIT_1
1957 #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2
1959 T3_32BIT_REGISTER Status;
1960 #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2
1962 /* Send BD initiator local NIC send BD producer index. */
1963 T3_32BIT_REGISTER NicSendBdInProdIdx[16];
1966 LM_UINT8 Unused2[952];
1967 } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
1971 /******************************************************************************/
1972 /* Send BD Completion Control. */
1973 /******************************************************************************/
1976 T3_32BIT_REGISTER Mode;
1977 #define SND_BD_COMP_MODE_RESET BIT_0
1978 #define SND_BD_COMP_MODE_ENABLE BIT_1
1979 #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2
1982 LM_UINT8 Unused2[1020];
1983 } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
1987 /******************************************************************************/
1988 /* Receive list placement control registers. */
1989 /******************************************************************************/
1993 T3_32BIT_REGISTER Mode;
1994 #define RCV_LIST_PLMT_MODE_RESET BIT_0
1995 #define RCV_LIST_PLMT_MODE_ENABLE BIT_1
1996 #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2
1997 #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3
1998 #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4
2001 T3_32BIT_REGISTER Status;
2002 #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2
2003 #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3
2004 #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4
2006 /* Receive selector list lock register. */
2007 T3_32BIT_REGISTER Lock;
2008 #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff
2009 #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000
2011 /* Selector non-empty bits. */
2012 T3_32BIT_REGISTER NonEmptyBits;
2013 #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff
2015 /* Receive list placement configuration register. */
2016 T3_32BIT_REGISTER Config;
2018 /* Receive List Placement statistics Control. */
2019 T3_32BIT_REGISTER StatsCtrl;
2020 #define RCV_LIST_STATS_ENABLE BIT_0
2021 #define RCV_LIST_STATS_FAST_UPDATE BIT_1
2023 /* Receive List Placement statistics Enable Mask. */
2024 T3_32BIT_REGISTER StatsEnableMask;
2025 #define T3_DISABLE_LONG_BURST_READ_DYN_FIX BIT_22
2027 /* Receive List Placement statistics Increment Mask. */
2028 T3_32BIT_REGISTER StatsIncMask;
2031 LM_UINT8 Unused1[224];
2034 T3_32BIT_REGISTER Head;
2035 T3_32BIT_REGISTER Tail;
2036 T3_32BIT_REGISTER Count;
2040 } RcvSelectorList[16];
2042 /* Local statistics counter. */
2043 T3_32BIT_REGISTER ClassOfServCnt[16];
2045 T3_32BIT_REGISTER DropDueToFilterCnt;
2046 T3_32BIT_REGISTER DmaWriteQFullCnt;
2047 T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
2048 T3_32BIT_REGISTER NoMoreReceiveBdCnt;
2049 T3_32BIT_REGISTER IfInDiscardsCnt;
2050 T3_32BIT_REGISTER IfInErrorsCnt;
2051 T3_32BIT_REGISTER RcvThresholdHitCnt;
2053 /* Another unused space. */
2054 LM_UINT8 Unused2[420];
2055 } T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
2059 /******************************************************************************/
2060 /* Receive Data and Receive BD Initiator Control. */
2061 /******************************************************************************/
2065 T3_32BIT_REGISTER Mode;
2066 #define RCV_DATA_BD_IN_MODE_RESET BIT_0
2067 #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1
2068 #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2
2069 #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3
2070 #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4
2073 T3_32BIT_REGISTER Status;
2074 #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2
2075 #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3
2076 #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4
2078 /* Split frame minium size. */
2079 T3_32BIT_REGISTER SplitFrameMinSize;
2082 LM_UINT8 Unused1[0x2440-0x240c];
2089 /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
2090 /* BD Consumber Index. */
2091 T3_32BIT_REGISTER NicJumboConIdx;
2092 T3_32BIT_REGISTER NicStdConIdx;
2093 T3_32BIT_REGISTER NicMiniConIdx;
2096 LM_UINT8 Unused2[4];
2098 /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
2099 T3_32BIT_REGISTER RcvDataBdProdIdx[16];
2101 /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
2102 T3_32BIT_REGISTER HwDiag;
2105 LM_UINT8 Unused3[828];
2106 } T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
2110 /******************************************************************************/
2111 /* Receive Data Completion Control Registes. */
2112 /******************************************************************************/
2115 T3_32BIT_REGISTER Mode;
2116 #define RCV_DATA_COMP_MODE_RESET BIT_0
2117 #define RCV_DATA_COMP_MODE_ENABLE BIT_1
2118 #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2
2120 /* Unused spaced. */
2121 LM_UINT8 Unused[1020];
2122 } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
2126 /******************************************************************************/
2127 /* Receive BD Initiator Control. */
2128 /******************************************************************************/
2131 T3_32BIT_REGISTER Mode;
2132 #define RCV_BD_IN_MODE_RESET BIT_0
2133 #define RCV_BD_IN_MODE_ENABLE BIT_1
2134 #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2
2136 T3_32BIT_REGISTER Status;
2137 #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2
2139 T3_32BIT_REGISTER NicJumboRcvProdIdx;
2140 T3_32BIT_REGISTER NicStdRcvProdIdx;
2141 T3_32BIT_REGISTER NicMiniRcvProdIdx;
2143 T3_32BIT_REGISTER MiniRcvThreshold;
2144 T3_32BIT_REGISTER StdRcvThreshold;
2145 T3_32BIT_REGISTER JumboRcvThreshold;
2148 LM_UINT8 Unused[992];
2149 } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
2153 /******************************************************************************/
2154 /* Receive BD Completion Control Registers. */
2155 /******************************************************************************/
2158 T3_32BIT_REGISTER Mode;
2159 #define RCV_BD_COMP_MODE_RESET BIT_0
2160 #define RCV_BD_COMP_MODE_ENABLE BIT_1
2161 #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2
2163 T3_32BIT_REGISTER Status;
2164 #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2
2166 T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
2167 T3_32BIT_REGISTER NicStdRcvBdProdIdx;
2168 T3_32BIT_REGISTER NicMiniRcvBdProdIdx;
2171 LM_UINT8 Unused[1004];
2172 } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
2176 /******************************************************************************/
2177 /* Receive list selector control register. */
2178 /******************************************************************************/
2181 T3_32BIT_REGISTER Mode;
2182 #define RCV_LIST_SEL_MODE_RESET BIT_0
2183 #define RCV_LIST_SEL_MODE_ENABLE BIT_1
2184 #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2
2186 T3_32BIT_REGISTER Status;
2187 #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2
2190 LM_UINT8 Unused[1016];
2191 } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
2195 /******************************************************************************/
2196 /* Mbuf cluster free registers. */
2197 /******************************************************************************/
2200 T3_32BIT_REGISTER Mode;
2201 #define MBUF_CLUSTER_FREE_MODE_RESET BIT_0
2202 #define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1
2204 T3_32BIT_REGISTER Status;
2207 LM_UINT8 Unused[1016];
2208 } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
2212 /******************************************************************************/
2213 /* Host coalescing control registers. */
2214 /******************************************************************************/
2218 T3_32BIT_REGISTER Mode;
2219 #define HOST_COALESCE_RESET BIT_0
2220 #define HOST_COALESCE_ENABLE BIT_1
2221 #define HOST_COALESCE_ATTN BIT_2
2222 #define HOST_COALESCE_NOW BIT_3
2223 #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE
2224 #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7
2225 #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8
2226 #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9
2227 #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10
2228 #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11
2229 #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12
2232 T3_32BIT_REGISTER Status;
2233 #define HOST_COALESCE_ERROR_ATTN BIT_2
2235 /* Receive coalescing ticks. */
2236 T3_32BIT_REGISTER RxCoalescingTicks;
2238 /* Send coalescing ticks. */
2239 T3_32BIT_REGISTER TxCoalescingTicks;
2241 /* Receive max coalesced frames. */
2242 T3_32BIT_REGISTER RxMaxCoalescedFrames;
2244 /* Send max coalesced frames. */
2245 T3_32BIT_REGISTER TxMaxCoalescedFrames;
2247 /* Receive coalescing ticks during interrupt. */
2248 T3_32BIT_REGISTER RxCoalescedTickDuringInt;
2250 /* Send coalescing ticks during interrupt. */
2251 T3_32BIT_REGISTER TxCoalescedTickDuringInt;
2253 /* Receive max coalesced frames during interrupt. */
2254 T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;
2256 /* Send max coalesced frames during interrupt. */
2257 T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;
2259 /* Statistics tick. */
2260 T3_32BIT_REGISTER StatsCoalescingTicks;
2263 LM_UINT8 Unused2[4];
2265 /* Statistics host address. */
2266 T3_64BIT_REGISTER StatsBlkHostAddr;
2268 /* Status block host address.*/
2269 T3_64BIT_REGISTER StatusBlkHostAddr;
2271 /* Statistics NIC address. */
2272 T3_32BIT_REGISTER StatsBlkNicAddr;
2274 /* Statust block NIC address. */
2275 T3_32BIT_REGISTER StatusBlkNicAddr;
2277 /* Flow attention registers. */
2278 T3_32BIT_REGISTER FlowAttn;
2281 LM_UINT8 Unused3[4];
2283 T3_32BIT_REGISTER NicJumboRcvBdConIdx;
2284 T3_32BIT_REGISTER NicStdRcvBdConIdx;
2285 T3_32BIT_REGISTER NicMiniRcvBdConIdx;
2288 LM_UINT8 Unused4[36];
2290 T3_32BIT_REGISTER NicRetProdIdx[16];
2291 T3_32BIT_REGISTER NicSndBdConIdx[16];
2294 LM_UINT8 Unused5[768];
2295 } T3_HOST_COALESCING, *PT3_HOST_COALESCING;
2299 /******************************************************************************/
2300 /* Memory arbiter registers. */
2301 /******************************************************************************/
2304 T3_32BIT_REGISTER Mode;
2305 #define T3_MEM_ARBITER_MODE_RESET BIT_0
2306 #define T3_MEM_ARBITER_MODE_ENABLE BIT_1
2308 T3_32BIT_REGISTER Status;
2310 T3_32BIT_REGISTER ArbTrapAddrLow;
2311 T3_32BIT_REGISTER ArbTrapAddrHigh;
2314 LM_UINT8 Unused[1008];
2315 } T3_MEM_ARBITER, *PT3_MEM_ARBITER;
2319 /******************************************************************************/
2320 /* Buffer manager control register. */
2321 /******************************************************************************/
2324 T3_32BIT_REGISTER Mode;
2325 #define BUFMGR_MODE_RESET BIT_0
2326 #define BUFMGR_MODE_ENABLE BIT_1
2327 #define BUFMGR_MODE_ATTN_ENABLE BIT_2
2328 #define BUFMGR_MODE_BM_TEST BIT_3
2329 #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4
2331 T3_32BIT_REGISTER Status;
2332 #define BUFMGR_STATUS_ERROR BIT_2
2333 #define BUFMGR_STATUS_MBUF_LOW BIT_4
2335 T3_32BIT_REGISTER MbufPoolAddr;
2336 T3_32BIT_REGISTER MbufPoolSize;
2337 T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
2338 T3_32BIT_REGISTER MbufMacRxLowWaterMark;
2339 T3_32BIT_REGISTER MbufHighWaterMark;
2341 T3_32BIT_REGISTER RxCpuMbufAllocReq;
2342 #define BUFMGR_MBUF_ALLOC_BIT BIT_31
2343 T3_32BIT_REGISTER RxCpuMbufAllocResp;
2344 T3_32BIT_REGISTER TxCpuMbufAllocReq;
2345 T3_32BIT_REGISTER TxCpuMbufAllocResp;
2347 T3_32BIT_REGISTER DmaDescPoolAddr;
2348 T3_32BIT_REGISTER DmaDescPoolSize;
2349 T3_32BIT_REGISTER DmaLowWaterMark;
2350 T3_32BIT_REGISTER DmaHighWaterMark;
2352 T3_32BIT_REGISTER RxCpuDmaAllocReq;
2353 T3_32BIT_REGISTER RxCpuDmaAllocResp;
2354 T3_32BIT_REGISTER TxCpuDmaAllocReq;
2355 T3_32BIT_REGISTER TxCpuDmaAllocResp;
2357 T3_32BIT_REGISTER Hwdiag[3];
2360 LM_UINT8 Unused[936];
2361 } T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
2365 /******************************************************************************/
2366 /* Read DMA control registers. */
2367 /******************************************************************************/
2370 T3_32BIT_REGISTER Mode;
2371 #define DMA_READ_MODE_RESET BIT_0
2372 #define DMA_READ_MODE_ENABLE BIT_1
2373 #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
2374 #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
2375 #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
2376 #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
2377 #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
2378 #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
2379 #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
2380 #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9
2381 #define DMA_READ_MODE_MULTI_SPLIT_ENABLE BIT_11
2382 #define DMA_READ_MODE_MULTI_SPLIT_RESET BIT_12
2383 #define DMA_READ_MODE_FIFO_SIZE_128 BIT_17
2384 #define DMA_READ_MODE_FIFO_LONG_BURST (BIT_16 | BIT_17)
2386 T3_32BIT_REGISTER Status;
2387 #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2
2388 #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3
2389 #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4
2390 #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5
2391 #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6
2392 #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7
2393 #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8
2394 #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9
2397 LM_UINT8 Unused[1016];
2398 } T3_DMA_READ, *PT3_DMA_READ;
2400 typedef union T3_CPU
2404 T3_32BIT_REGISTER mode;
2405 #define CPU_MODE_HALT BIT_10
2406 #define CPU_MODE_RESET BIT_0
2407 T3_32BIT_REGISTER state;
2408 T3_32BIT_REGISTER EventMask;
2409 T3_32BIT_REGISTER reserved1[4];
2410 T3_32BIT_REGISTER PC;
2411 T3_32BIT_REGISTER Instruction;
2412 T3_32BIT_REGISTER SpadUnderflow;
2413 T3_32BIT_REGISTER WatchdogClear;
2414 T3_32BIT_REGISTER WatchdogVector;
2415 T3_32BIT_REGISTER WatchdogSavedPC;
2416 T3_32BIT_REGISTER HardwareBp;
2417 T3_32BIT_REGISTER reserved2[3];
2418 T3_32BIT_REGISTER WatchdogSavedState;
2419 T3_32BIT_REGISTER LastBrchAddr;
2420 T3_32BIT_REGISTER SpadUnderflowSet;
2421 T3_32BIT_REGISTER reserved3[(0x200-0x50)/4];
2422 T3_32BIT_REGISTER Regs[32];
2423 T3_32BIT_REGISTER reserved4[(0x400-0x280)/4];
2427 /******************************************************************************/
2428 /* Write DMA control registers. */
2429 /******************************************************************************/
2432 T3_32BIT_REGISTER Mode;
2433 #define DMA_WRITE_MODE_RESET BIT_0
2434 #define DMA_WRITE_MODE_ENABLE BIT_1
2435 #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
2436 #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
2437 #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
2438 #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
2439 #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
2440 #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
2441 #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
2442 #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9
2443 #define DMA_WRITE_MODE_RECEIVE_ACCELERATE BIT_10
2445 T3_32BIT_REGISTER Status;
2446 #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2
2447 #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3
2448 #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4
2449 #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5
2450 #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6
2451 #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7
2452 #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8
2453 #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9
2456 LM_UINT8 Unused[1016];
2457 } T3_DMA_WRITE, *PT3_DMA_WRITE;
2461 /******************************************************************************/
2462 /* Mailbox registers. */
2463 /******************************************************************************/
2466 /* Interrupt mailbox registers. */
2467 T3_64BIT_REGISTER Interrupt[4];
2469 /* General mailbox registers. */
2470 T3_64BIT_REGISTER General[8];
2472 /* Reload statistics mailbox. */
2473 T3_64BIT_REGISTER ReloadStat;
2475 /* Receive BD ring producer index registers. */
2476 T3_64BIT_REGISTER RcvStdProdIdx;
2477 T3_64BIT_REGISTER RcvJumboProdIdx;
2478 T3_64BIT_REGISTER RcvMiniProdIdx;
2480 /* Receive return ring consumer index registers. */
2481 T3_64BIT_REGISTER RcvRetConIdx[16];
2483 /* Send BD ring host producer index registers. */
2484 T3_64BIT_REGISTER SendHostProdIdx[16];
2486 /* Send BD ring nic producer index registers. */
2487 T3_64BIT_REGISTER SendNicProdIdx[16];
2488 }T3_MAILBOX, *PT3_MAILBOX;
2493 /* Priority mailbox registers. */
2494 T3_32BIT_REGISTER HighPriorityEventVector;
2495 T3_32BIT_REGISTER HighPriorityEventMask;
2496 T3_32BIT_REGISTER LowPriorityEventVector;
2497 T3_32BIT_REGISTER LowPriorityEventMask;
2500 LM_UINT8 Unused[496];
2501 } T3_GRC_MAILBOX, *PT3_GRC_MAILBOX;
2504 /******************************************************************************/
2505 /* Flow through queues. */
2506 /******************************************************************************/
2509 T3_32BIT_REGISTER Reset;
2511 LM_UINT8 Unused[12];
2513 T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
2514 T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
2515 T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
2516 T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
2518 T3_32BIT_REGISTER DmaHighReadFtqCtrl;
2519 T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
2520 T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
2521 T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
2523 T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
2524 T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
2525 T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
2526 T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
2528 T3_32BIT_REGISTER SendBdCompFtqCtrl;
2529 T3_32BIT_REGISTER SendBdCompFtqFullCnt;
2530 T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
2531 T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
2533 T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
2534 T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
2535 T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
2536 T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
2538 T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
2539 T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
2540 T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
2541 T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
2543 T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
2544 T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
2545 T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
2546 T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
2548 T3_32BIT_REGISTER SwType1FtqCtrl;
2549 T3_32BIT_REGISTER SwType1FtqFullCnt;
2550 T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
2551 T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
2553 T3_32BIT_REGISTER SendDataCompFtqCtrl;
2554 T3_32BIT_REGISTER SendDataCompFtqFullCnt;
2555 T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
2556 T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
2558 T3_32BIT_REGISTER HostCoalesceFtqCtrl;
2559 T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
2560 T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
2561 T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
2563 T3_32BIT_REGISTER MacTxFtqCtrl;
2564 T3_32BIT_REGISTER MacTxFtqFullCnt;
2565 T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
2566 T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
2568 T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
2569 T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
2570 T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
2571 T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
2573 T3_32BIT_REGISTER RcvBdCompFtqCtrl;
2574 T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
2575 T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
2576 T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
2578 T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
2579 T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
2580 T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
2581 T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
2583 T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
2584 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
2585 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
2586 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
2588 T3_32BIT_REGISTER RcvDataCompFtqCtrl;
2589 T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
2590 T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
2591 T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
2593 T3_32BIT_REGISTER SwType2FtqCtrl;
2594 T3_32BIT_REGISTER SwType2FtqFullCnt;
2595 T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
2596 T3_32BIT_REGISTER SwType2FtqFifoWritePeek;
2599 LM_UINT8 Unused2[736];
2604 /******************************************************************************/
2605 /* Message signaled interrupt registers. */
2606 /******************************************************************************/
2609 T3_32BIT_REGISTER Mode;
2610 #define MSI_MODE_RESET BIT_0
2611 #define MSI_MODE_ENABLE BIT_1
2612 T3_32BIT_REGISTER Status;
2614 T3_32BIT_REGISTER MsiFifoAccess;
2617 LM_UINT8 Unused[1012];
2618 } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
2622 /******************************************************************************/
2623 /* DMA Completion registes. */
2624 /******************************************************************************/
2627 T3_32BIT_REGISTER Mode;
2628 #define DMA_COMP_MODE_RESET BIT_0
2629 #define DMA_COMP_MODE_ENABLE BIT_1
2632 LM_UINT8 Unused[1020];
2633 } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
2637 /******************************************************************************/
2638 /* GRC registers. */
2639 /******************************************************************************/
2642 /* Mode control register. */
2643 T3_32BIT_REGISTER Mode;
2644 #define GRC_MODE_UPDATE_ON_COALESCING BIT_0
2645 #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1
2646 #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2
2647 #define GRC_MODE_BYTE_SWAP_DATA BIT_4
2648 #define GRC_MODE_WORD_SWAP_DATA BIT_5
2649 #define GRC_MODE_SPLIT_HEADER_MODE BIT_8
2650 #define GRC_MODE_NO_FRAME_CRACKING BIT_9
2651 #define GRC_MODE_INCLUDE_CRC BIT_10
2652 #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11
2653 #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13
2654 #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14
2655 #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15
2656 #define GRC_MODE_HOST_STACK_UP BIT_16
2657 #define GRC_MODE_HOST_SEND_BDS BIT_17
2658 #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20
2659 #define GRC_MODE_NVRAM_WRITE_ENABLE BIT_21
2660 #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23
2661 #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24
2662 #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25
2663 #define GRC_MODE_INT_ON_MAC_ATTN BIT_26
2664 #define GRC_MODE_INT_ON_DMA_ATTN BIT_27
2665 #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28
2666 #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29
2667 #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30
2669 /* Misc configuration register. */
2670 T3_32BIT_REGISTER MiscCfg;
2671 #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0
2672 #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe
2673 #define GRC_MISC_BD_ID_MASK 0x0001e000
2674 #define GRC_MISC_BD_ID_5700 0x0001e000
2675 #define GRC_MISC_BD_ID_5701 0x00000000
2676 #define GRC_MISC_BD_ID_5703 0x00000000
2677 #define GRC_MISC_BD_ID_5703S 0x00002000
2678 #define GRC_MISC_BD_ID_5702FE 0x00004000
2679 #define GRC_MISC_BD_ID_5704 0x00000000
2680 #define GRC_MISC_BD_ID_5704CIOBE 0x00004000
2681 #define GRC_MISC_BD_ID_5788 0x00010000
2682 #define GRC_MISC_BD_ID_5788M 0x00018000
2683 #define GRC_MISC_GPHY_KEEP_POWER_DURING_RESET BIT_26
2685 /* Miscellaneous local control register. */
2686 T3_32BIT_REGISTER LocalCtrl;
2687 #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0
2688 #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1
2689 #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2
2690 #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3
2692 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT3 BIT_5
2693 #define GRC_MISC_LOCAL_CTRL_GPIO_OE3 BIT_6
2694 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT3 BIT_7
2696 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8
2697 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9
2698 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10
2699 #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11
2700 #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12
2701 #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13
2702 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14
2703 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15
2704 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16
2705 #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17
2706 #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21
2707 #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22
2709 #define GRC_MISC_MEMSIZE_256K 0
2710 #define GRC_MISC_MEMSIZE_512K (1 << 18)
2711 #define GRC_MISC_MEMSIZE_1024K (2 << 18)
2712 #define GRC_MISC_MEMSIZE_2048K (3 << 18)
2713 #define GRC_MISC_MEMSIZE_4096K (4 << 18)
2714 #define GRC_MISC_MEMSIZE_8192K (5 << 18)
2715 #define GRC_MISC_MEMSIZE_16M (6 << 18)
2716 #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24
2719 T3_32BIT_REGISTER Timer;
2721 T3_32BIT_REGISTER RxCpuEvent;
2722 T3_32BIT_REGISTER RxTimerRef;
2723 T3_32BIT_REGISTER RxCpuSemaphore;
2724 T3_32BIT_REGISTER RemoteRxCpuAttn;
2726 T3_32BIT_REGISTER TxCpuEvent;
2727 T3_32BIT_REGISTER TxTimerRef;
2728 T3_32BIT_REGISTER TxCpuSemaphore;
2729 T3_32BIT_REGISTER RemoteTxCpuAttn;
2731 T3_64BIT_REGISTER MemoryPowerUp;
2733 T3_32BIT_REGISTER EepromAddr;
2734 #define SEEPROM_ADDR_WRITE 0
2735 #define SEEPROM_ADDR_READ (1 << 31)
2736 #define SEEPROM_ADDR_RW_MASK 0x80000000
2737 #define SEEPROM_ADDR_COMPLETE (1 << 30)
2738 #define SEEPROM_ADDR_FSM_RESET (1 << 29)
2739 #define SEEPROM_ADDR_DEV_ID(x) (x << 26)
2740 #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
2741 #define SEEPROM_ADDR_START (1 << 25)
2742 #define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
2743 #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc)
2744 #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
2746 #define SEEPROM_CLOCK_PERIOD 60
2747 #define SEEPROM_CHIP_SIZE (64 * 1024)
2749 T3_32BIT_REGISTER EepromData;
2750 T3_32BIT_REGISTER EepromCtrl;
2752 T3_32BIT_REGISTER MdiCtrl;
2753 T3_32BIT_REGISTER SepromDelay;
2756 LM_UINT8 Unused[948];
2760 /******************************************************************************/
2761 /* NVRAM control registers. */
2762 /******************************************************************************/
2766 T3_32BIT_REGISTER Cmd;
2767 #define NVRAM_CMD_RESET BIT_0
2768 #define NVRAM_CMD_DONE BIT_3
2769 #define NVRAM_CMD_DO_IT BIT_4
2770 #define NVRAM_CMD_WR BIT_5
2771 #define NVRAM_CMD_RD BIT_NONE
2772 #define NVRAM_CMD_ERASE BIT_6
2773 #define NVRAM_CMD_FIRST BIT_7
2774 #define NVRAM_CMD_LAST BIT_8
2775 #define NVRAM_CMD_WRITE_ENABLE BIT_16
2776 #define NVRAM_CMD_WRITE_DISABLE BIT_17
2777 #define NVRAM_CMD_EN_WR_SR BIT_18
2778 #define NVRAM_CMD_DO_WR_SR BIT_19
2780 T3_32BIT_REGISTER Status;
2781 T3_32BIT_REGISTER WriteData;
2783 T3_32BIT_REGISTER Addr;
2784 #define NVRAM_ADDRESS_MASK 0xffffff
2786 T3_32BIT_REGISTER ReadData;
2788 /* Flash config 1 register. */
2789 T3_32BIT_REGISTER Config1;
2790 #define FLASH_INTERFACE_ENABLE BIT_0
2791 #define FLASH_SSRAM_BUFFERED_MODE BIT_1
2792 #define FLASH_PASS_THRU_MODE BIT_2
2793 #define FLASH_BIT_BANG_MODE BIT_3
2794 #define FLASH_STATUS_BITS_MASK (BIT_4 | BIT_5 | BIT_6)
2795 #define FLASH_SIZE BIT_25
2796 #define FLASH_COMPAT_BYPASS BIT_31
2797 #define FLASH_VENDOR_MASK (BIT_25 | BIT_24 | BIT_1 | BIT_0)
2798 #define FLASH_VENDOR_ATMEL_EEPROM BIT_25
2799 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED (BIT_25 | BIT_1 | BIT_0)
2800 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED (BIT_1 | BIT_0)
2801 #define FLASH_VENDOR_ST (BIT_25 | BIT_24 | BIT_0)
2802 #define FLASH_VENDOR_SAIFUN (BIT_24 | BIT_1 | BIT_0)
2803 #define FLASH_VENDOR_SST_SMALL BIT_0
2804 #define FLASH_VENDOR_SST_LARGE (BIT_25 | BIT_0)
2806 #define BUFFERED_FLASH (FLASH_INTERFACE_ENABLE | FLASH_SSRAM_BUFFERED_MODE)
2808 /* Buffered flash (Atmel: AT45DB011B) specific information */
2809 #define BUFFERED_FLASH_PAGE_POS 9
2810 #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
2811 #define BUFFERED_FLASH_PAGE_SIZE 264
2812 #define BUFFERED_FLASH_PHY_PAGE_SIZE 512
2814 /* Bleh! Definitions for Baxter. */
2815 #define FLASH_PART_5750_TYPEMASK \
2816 (BIT_25 | BIT_24 | BIT_1 | BIT_0)
2818 #define FLASH_PART_5752_TYPEMASK \
2819 (BIT_25 | BIT_24 | BIT_23 | BIT_22 | BIT_1 | BIT_0)
2821 #define FLASH_PART_5752_EEPROM_ATMEL_64K BIT_NONE
2822 #define FLASH_PART_5752_EEPROM_ATMEL_376K BIT_25
2823 #define FLASH_PART_5752_FLASH_ATMEL_AT45DB041 (BIT_25 | BIT_1 | BIT_0)
2824 #define FLASH_PART_5752_FLASH_ATMEL_AT25F512 (BIT_1 | BIT_0)
2825 #define FLASH_PART_5752_FLASH_SST_45VF010 (BIT_25 | BIT_0)
2826 #define FLASH_PART_5752_FLASH_SST_25F512 (BIT_0)
2827 #define FLASH_PART_5752_FLASH_ST_M25P10A (BIT_25 | BIT_24 | BIT_0)
2828 #define FLASH_PART_5752_FLASH_ST_M25P05A (BIT_24 | BIT_0)
2829 #define FLASH_PART_5752_FLASH_SAIFUN_SA25F010 (BIT_22)
2830 #define FLASH_PART_5752_FLASH_SAIFUN_SA25F020 (BIT_22 | BIT_1)
2831 #define FLASH_PART_5752_FLASH_SAIFUN_SA25F040 (BIT_22 | BIT_0)
2832 #define FLASH_PART_5752_FLASH_SST_25VF010 (BIT_24 | BIT_22)
2833 #define FLASH_PART_5752_FLASH_SST_25VF020 (BIT_24 | BIT_22 | BIT_1)
2834 #define FLASH_PART_5752_FLASH_SST_25VF040 (BIT_24 | BIT_22 | BIT_0)
2835 #define FLASH_PART_5752_FLASH_ST_M45PE10 (BIT_25 | BIT_22)
2836 #define FLASH_PART_5752_FLASH_ST_M45PE20 (BIT_25 | BIT_22 | BIT_1)
2837 #define FLASH_PART_5752_FLASH_ST_M45PE40 (BIT_25 | BIT_22 | BIT_0)
2839 #define FLASH_PART_5752_PAGEMASK \
2840 (BIT_30 | BIT_29 | BIT_28)
2842 #define FLASH_PART_5752_PAGE_SIZE_256B BIT_NONE
2843 #define FLASH_PART_5752_PAGE_SIZE_512B BIT_28
2844 #define FLASH_PART_5752_PAGE_SIZE_1K BIT_29
2845 #define FLASH_PART_5752_PAGE_SIZE_2K (BIT_29 | BIT_28)
2846 #define FLASH_PART_5752_PAGE_SIZE_4K BIT_30
2847 #define FLASH_PART_5752_PAGE_SIZE_264B (BIT_30 | BIT_28)
2850 T3_32BIT_REGISTER Config2;
2851 #define NVRAM_COMMAND_MASK 0x000000ff
2852 #define NVRAM_STATUS_COMMAND(x) ((x) << 16)
2853 #define NVRAM_ERASE_COMMAND(x) (x)
2855 T3_32BIT_REGISTER Config3;
2856 #define NVRAM_COMMAND_MASK 0x000000ff
2857 #define NVRAM_READ_COMMAND(x) ((x) << 24)
2858 #define NVRAM_WRITE_UNBUFFERED_COMMAND(x) ((x) << 8)
2859 #define NVRAM_WRITE_BUFFERED_COMMAND(x) ((x) << 16)
2860 #define NVRAM_RESET_COMMAND(x) (x)
2862 T3_32BIT_REGISTER SwArb;
2863 #define SW_ARB_REQ_SET0 BIT_0
2864 #define SW_ARB_REQ_SET1 BIT_1
2865 #define SW_ARB_REQ_SET2 BIT_2
2866 #define SW_ARB_REQ_SET3 BIT_3
2867 #define SW_ARB_REQ_CLR0 BIT_4
2868 #define SW_ARB_REQ_CLR1 BIT_5
2869 #define SW_ARB_REQ_CLR2 BIT_6
2870 #define SW_ARB_REQ_CLR3 BIT_7
2871 #define SW_ARB_GNT0 BIT_8
2872 #define SW_ARB_GNT1 BIT_9
2873 #define SW_ARB_GNT2 BIT_10
2874 #define SW_ARB_GNT3 BIT_11
2875 #define SW_ARB_REQ0 BIT_12
2876 #define SW_ARB_REQ1 BIT_13
2877 #define SW_ARB_REQ2 BIT_14
2878 #define SW_ARB_REQ3 BIT_15
2880 T3_32BIT_REGISTER NvmAccess;
2881 #define ACCESS_EN BIT_0
2882 #define ACCESS_WR_EN BIT_1
2883 #define NVRAM_ACCESS_ENABLE BIT_0
2884 #define NVRAM_ACCESS_WRITE_ENABLE BIT_1
2886 T3_32BIT_REGISTER Write1;
2887 #define NVRAM_WRITE1_WRENA_CMD(x) (x)
2888 #define NVRAM_WRITE1_WRDIS_CMD(x) ((x) << 8)
2890 T3_32BIT_REGISTER WatchTimer;
2892 T3_32BIT_REGISTER Config4;
2895 LM_UINT8 Unused[972];
2896 } T3_NVRAM, *PT3_NVRAM;
2899 /******************************************************************************/
2900 /* NIC's internal memory. */
2901 /******************************************************************************/
2904 /* Page zero for the internal CPUs. */
2905 LM_UINT8 PageZero[0x100]; /* 0x0000 */
2908 T3_RCB SendRcb[16]; /* 0x0100 */
2910 /* Receive Return RCBs. */
2911 T3_RCB RcvRetRcb[16]; /* 0x0200 */
2913 /* Statistics block. */
2914 T3_STATS_BLOCK StatsBlk; /* 0x0300 */
2917 T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */
2919 /* Reserved for software. */
2920 LM_UINT8 Reserved[1200]; /* 0x0b50 */
2922 /* Unmapped region. */
2923 LM_UINT8 Unmapped[4096]; /* 0x1000 */
2925 /* DMA descriptors. */
2926 LM_UINT8 DmaDesc[8192]; /* 0x2000 */
2928 /* Buffer descriptors. */
2929 LM_UINT8 BufferDesc[16384]; /* 0x4000 */
2930 } T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
2934 /******************************************************************************/
2935 /* Memory layout. */
2936 /******************************************************************************/
2939 /* PCI configuration registers. */
2940 T3_PCI_CONFIGURATION PciCfg;
2943 LM_UINT8 Unused1[0x100]; /* 0x0100 */
2946 T3_MAILBOX Mailbox; /* 0x0200 */
2948 /* MAC control registers. */
2949 T3_MAC_CONTROL MacCtrl; /* 0x0400 */
2951 /* Send data initiator control registers. */
2952 T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */
2954 /* Send data completion Control registers. */
2955 T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */
2957 /* Send BD ring selector. */
2958 T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */
2960 /* Send BD initiator control registers. */
2961 T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */
2963 /* Send BD completion control registers. */
2964 T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */
2966 /* Receive list placement control registers. */
2967 T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */
2969 /* Receive Data and Receive BD Initiator Control. */
2970 T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */
2972 /* Receive Data Completion Control */
2973 T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */
2975 /* Receive BD Initiator Control Registers. */
2976 T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */
2978 /* Receive BD Completion Control Registers. */
2979 T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */
2981 /* Receive list selector control registers. */
2982 T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */
2984 /* Mbuf cluster free registers. */
2985 T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */
2987 /* Host coalescing control registers. */
2988 T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */
2990 /* Memory arbiter control registers. */
2991 T3_MEM_ARBITER MemArbiter; /* 0x4000 */
2993 /* Buffer manger control registers. */
2994 T3_BUFFER_MANAGER BufMgr; /* 0x4400 */
2996 /* Read DMA control registers. */
2997 T3_DMA_READ DmaRead; /* 0x4800 */
2999 /* Write DMA control registers. */
3000 T3_DMA_WRITE DmaWrite; /* 0x4c00 */
3002 T3_CPU rxCpu; /* 0x5000 */
3003 T3_CPU txCpu; /* 0x5400 */
3006 T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */
3008 /* Flow Through queues. */
3009 T3_FTQ Ftq; /* 0x5c00 */
3011 /* Message signaled interrupt registes. */
3012 T3_MSG_SIGNALED_INT Msi; /* 0x6000 */
3014 /* DMA completion registers. */
3015 T3_DMA_COMPLETION DmaComp; /* 0x6400 */
3017 /* GRC registers. */
3018 T3_GRC Grc; /* 0x6800 */
3021 LM_UINT8 Unused2[1024]; /* 0x6c00 */
3023 /* NVRAM registers. */
3024 T3_NVRAM Nvram; /* 0x7000 */
3027 LM_UINT8 Unused3[3072]; /* 0x7400 */
3029 /* The 32k memory window into the NIC's */
3030 /* internal memory. The memory window is */
3031 /* controlled by the Memory Window Base */
3032 /* Address register. This register is located */
3033 /* in the PCI configuration space. */
3034 union { /* 0x8000 */
3035 T3_FIRST_32K_SRAM First32k;
3037 /* Use the memory window base address register to determine the */
3039 LM_UINT32 Mbuf[32768/4];
3040 LM_UINT32 MemBlock32K[32768/4];
3042 } T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
3045 /******************************************************************************/
3047 /******************************************************************************/
3054 LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */
3055 } LM_ADAPTER_INFO, *PLM_ADAPTER_INFO;
3058 /******************************************************************************/
3060 /******************************************************************************/
3065 #define ROM_TYPE_EEPROM 0x1
3066 #define ROM_TYPE_FLASH 0x2
3074 #define JEDEC_ATMEL 0x1f
3075 #define JEDEC_ST 0x20
3076 #define JEDEC_SAIFUN 0x4f
3077 #define JEDEC_SST 0xbf
3079 #define ATMEL_AT24C64_CHIP_SIZE (64 * 1024)
3080 #define ATMEL_AT24C64_PAGE_SIZE (32)
3081 #define ATMEL_AT24C64_PAGE_MASK (ATMEL_AT24C64_PAGE_SIZE - 1)
3083 #define ATMEL_AT24C512_CHIP_SIZE (512 * 1024)
3084 #define ATMEL_AT24C512_PAGE_SIZE (128)
3085 #define ATMEL_AT24C512_PAGE_MASK (ATMEL_AT24C512_PAGE_SIZE - 1)
3087 #define ATMEL_AT45DB0X1B_PAGE_POS 9
3088 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3089 #define ATMEL_AT45DB0X1B_PAGE_MASK 0x1ff
3090 #define ATMEL_AT45DB0X1B_BUFFER_WRITE_CMD 0x83
3092 /* Currently unsupported flash type */
3093 #define ATMEL_AT25F512_PAGE_SIZE 256
3094 #define ATMEL_AT25F512_PAGE_MASK (ATMEL_AT25F512_PAGE_SIZE - 1)
3096 #define ST_M45PEX0_PAGE_SIZE 256
3097 #define ST_M45PEX0_PAGE_MASK (ST_M45PEX0_PAGE_SIZE - 1)
3098 #define ST_M45PEX0_READ_STATUS_CMD 0x05
3099 #define ST_M45PEX0_PAGE_ERASE_CMD 0xDB
3100 #define ST_M45PEX0_PAGE_PRGM_CMD 0x0A
3101 #define ST_M45PEX0_WRENA_CMD 0x06
3102 #define ST_M45PEX0_WRDIS_CMD 0x04
3104 #define SAIFUN_SA25F0XX_PAGE_SIZE 256
3105 #define SAIFUN_SA25F0XX_PAGE_MASK (SAIFUN_SA25F0XX_PAGE_SIZE - 1)
3106 #define SAIFUN_SA25F0XX_READ_STATUS_CMD 0x05
3107 #define SAIFUN_SA25F0XX_PAGE_ERASE_CMD 0x81
3108 #define SAIFUN_SA25F0XX_PAGE_WRITE_CMD 0x02
3109 #define SAIFUN_SA25F0XX_WRENA_CMD 0x06
3111 /* Currently unsupported flash type */
3112 #define SST_25VF0X0_PAGE_SIZE 4098
3113 #define SST_25VF0X0_PAGE_MASK (SST_25VF0X0_PAGE_SIZE - 1)
3116 /******************************************************************************/
3117 /* Packet queues. */
3118 /******************************************************************************/
3120 DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
3121 DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
3125 /******************************************************************************/
3127 /******************************************************************************/
3130 LM_COUNTER TxPacketGoodCnt;
3131 LM_COUNTER TxBytesGoodCnt;
3132 LM_COUNTER TxPacketAbortedCnt;
3133 LM_COUNTER NoSendBdLeftCnt;
3134 LM_COUNTER NoMapRegisterLeftCnt;
3135 LM_COUNTER TooManyFragmentsCnt;
3136 LM_COUNTER NoTxPacketDescCnt;
3137 } LM_TX_COUNTERS, *PLM_TX_COUNTERS;
3141 /******************************************************************************/
3143 /******************************************************************************/
3146 LM_COUNTER RxPacketGoodCnt;
3147 LM_COUNTER RxBytesGoodCnt;
3148 LM_COUNTER RxPacketErrCnt;
3149 LM_COUNTER RxErrCrcCnt;
3150 LM_COUNTER RxErrCollCnt;
3151 LM_COUNTER RxErrLinkLostCnt;
3152 LM_COUNTER RxErrPhyDecodeCnt;
3153 LM_COUNTER RxErrOddNibbleCnt;
3154 LM_COUNTER RxErrMacAbortCnt;
3155 LM_COUNTER RxErrShortPacketCnt;
3156 LM_COUNTER RxErrNoResourceCnt;
3157 LM_COUNTER RxErrLargePacketCnt;
3158 } LM_RX_COUNTERS, *PLM_RX_COUNTERS;
3162 /******************************************************************************/
3163 /* Receive producer rings. */
3164 /******************************************************************************/
3167 T3_UNKNOWN_RCV_PROD_RING = 0,
3168 T3_STD_RCV_PROD_RING = 1,
3169 T3_MINI_RCV_PROD_RING = 2,
3170 T3_JUMBO_RCV_PROD_RING = 3
3171 } T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
3175 /******************************************************************************/
3176 /* Packet descriptor. */
3177 /******************************************************************************/
3179 #define LM_PACKET_SIGNATURE_TX 0x6861766b
3180 #define LM_PACKET_SIGNATURE_RX 0x6b766168
3182 typedef struct _LM_PACKET {
3184 LM_STATUS PacketStatus;
3186 /* Set in LM for Rx, in UM for Tx. */
3187 LM_UINT32 PacketSize;
3197 LM_UINT32 FragCount;
3199 #if INCLUDE_TCP_SEG_SUPPORT
3200 LM_UINT32 MaxSegmentSize;
3206 /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
3207 LM_UINT16 RcvProdRing;
3208 LM_UINT16 RcvRingProdIdx;
3210 /* Receive buffer size */
3211 LM_UINT32 RxBufferSize;
3213 /* Checksum information. */
3214 LM_UINT16 IpChecksum;
3215 LM_UINT16 TcpUdpChecksum;
3223 /******************************************************************************/
3224 /* Tigon3 device block. */
3225 /******************************************************************************/
3227 typedef struct _LM_DEVICE_BLOCK {
3229 PT3_STD_MEM_MAP pMemView;
3231 /* Base address of the block of memory in which the LM_PACKET descriptors */
3232 /* are allocated from. */
3233 PLM_VOID pPacketDescBase;
3235 LM_UINT32 MiscHostCtrl;
3236 LM_UINT32 GrcLocalCtrl;
3237 LM_UINT32 DmaReadWriteCtrl;
3239 LM_UINT32 ClockCtrl;
3240 LM_UINT32 DmaReadFifoSize;
3243 LM_UINT32 PowerLevel;
3247 #define MINI_PCI_FLAG 0x1
3248 #define PCI_EXPRESS_FLAG 0x2
3249 #define BCM5788_FLAG 0x4
3250 #define FIBER_WOL_CAPABLE_FLAG 0x8
3251 #define WOL_LIMIT_10MBPS_FLAG 0x10
3252 #define ENABLE_MWI_FLAG 0x20
3253 #define USE_TAGGED_STATUS_FLAG 0x40
3255 /* NIC will not compute the pseudo header checksum. The driver or OS */
3256 /* must seed the checksum field with the pseudo checksum. */
3257 #define NO_TX_PSEUDO_HDR_CSUM_FLAG 0x80
3259 /* The receive checksum in the BD does not include the pseudo checksum. */
3260 /* The OS or the driver must calculate the pseudo checksum and add it to */
3261 /* the checksum in the BD. */
3262 #define NO_RX_PSEUDO_HDR_CSUM_FLAG 0x100
3264 #define ENABLE_PCIX_FIX_FLAG 0x200
3266 #define TX_4G_WORKAROUND_FLAG 0x400
3267 #define UNDI_FIX_FLAG 0x800
3268 #define FLUSH_POSTED_WRITE_FLAG 0x1000
3269 #define REG_RD_BACK_FLAG 0x2000
3271 /* Use NIC or Host based send BD. */
3272 #define NIC_SEND_BD_FLAG 0x4000
3275 #define DELAY_PCI_GRANT_FLAG 0x8000
3277 /* Enable OneDmaAtOnce */
3278 #define ONE_DMA_AT_ONCE_FLAG 0x10000
3280 /* Enable PCI-X multi split */
3281 #define MULTI_SPLIT_ENABLE_FLAG 0x20000
3283 #define RX_BD_LIMIT_64_FLAG 0x40000
3285 #define DMA_WR_MODE_RX_ACCELERATE_FLAG 0x80000
3288 #define EEPROM_WP_FLAG 0x100000
3289 #define FLASH_DETECTED_FLAG 0x200000
3291 #define DISABLE_D3HOT_FLAG 0x400000
3293 /* 5753 should not output gpio2 */
3294 #define GPIO2_DONOT_OUTPUT 0x800000
3296 #define USING_MSI_FLAG 0x1000000
3297 #define JUMBO_CAPABLE_FLAG 0x2000000
3298 #define PROTECTED_NVRAM_FLAG 0x4000000
3299 #define T3_HAS_TWO_CPUS 0x8000000
3300 #define HOST_COALESCING_BUG_FIX 0x10000000
3303 LM_UINT32 RxStdDescCnt;
3304 LM_UINT32 RxStdQueuedCnt;
3305 LM_UINT32 RxStdProdIdx;
3307 PT3_RCV_BD pRxStdBdVirt;
3308 LM_PHYSICAL_ADDRESS RxStdBdPhy;
3310 LM_UINT32 RxPacketDescCnt;
3311 LM_RX_PACKET_Q RxPacketFreeQ;
3312 LM_RX_PACKET_Q RxPacketReceivedQ;
3314 LM_PACKET *RxStdRing[T3_STD_RCV_RCB_ENTRY_COUNT];
3315 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3316 LM_PACKET *RxJumboRing[T3_JUMBO_RCV_RCB_ENTRY_COUNT];
3320 PT3_RCV_BD pRcvRetBdVirt;
3321 LM_PHYSICAL_ADDRESS RcvRetBdPhy;
3322 LM_UINT32 RcvRetConIdx;
3323 LM_UINT32 RcvRetRcbEntryCount;
3324 LM_UINT32 RcvRetRcbEntryCountMask;
3326 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3327 LM_UINT32 RxJumboDescCnt;
3328 LM_UINT32 RxJumboBufferSize;
3329 LM_UINT32 RxJumboQueuedCnt;
3331 LM_UINT32 RxJumboProdIdx;
3333 PT3_RCV_BD pRxJumboBdVirt;
3334 LM_PHYSICAL_ADDRESS RxJumboBdPhy;
3335 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3337 /* These values are used by the upper module to inform the protocol */
3338 /* of the maximum transmit/receive packet size. */
3339 LM_UINT32 TxMtu; /* Does not include CRC. */
3340 LM_UINT32 RxMtu; /* Does not include CRC. */
3342 #if INCLUDE_TCP_SEG_SUPPORT
3343 LM_UINT32 LargeSendMaxSize;
3344 LM_UINT32 LargeSendMinNumSeg;
3347 /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */
3348 /* we may have problems reading any MAC registers in 10mb mode. */
3353 /* MiMode register. */
3356 /* Host coalesce mode register. */
3357 LM_UINT32 CoalesceMode;
3360 LM_UINT32 TxPacketDescCnt;
3363 LM_TX_PACKET_Q TxPacketFreeQ;
3364 LM_TX_PACKET_Q TxPacketXmittedQ;
3366 /* Pointers to SendBd. */
3367 PT3_SND_BD pSendBdVirt;
3368 LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */
3370 /* Send producer and consumer indices. */
3371 LM_UINT32 SendProdIdx;
3372 LM_UINT32 SendConIdx;
3374 /* Number of BD left. */
3375 MM_ATOMIC_T SendBdLeft;
3377 T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
3378 LM_PACKET *SendRing[T3_SEND_RCB_ENTRY_COUNT];
3381 LM_RX_COUNTERS RxCounters;
3382 LM_TX_COUNTERS TxCounters;
3384 /* Host coalescing parameters. */
3385 LM_UINT32 RxCoalescingTicks;
3386 LM_UINT32 TxCoalescingTicks;
3387 LM_UINT32 RxMaxCoalescedFrames;
3388 LM_UINT32 TxMaxCoalescedFrames;
3389 LM_UINT32 StatsCoalescingTicks;
3390 LM_UINT32 RxCoalescingTicksDuringInt;
3391 LM_UINT32 TxCoalescingTicksDuringInt;
3392 LM_UINT32 RxMaxCoalescedFramesDuringInt;
3393 LM_UINT32 TxMaxCoalescedFramesDuringInt;
3395 /* DMA water marks. */
3396 LM_UINT32 DmaMbufLowMark;
3397 LM_UINT32 RxMacMbufLowMark;
3398 LM_UINT32 MbufHighMark;
3401 PT3_STATUS_BLOCK pStatusBlkVirt;
3402 LM_PHYSICAL_ADDRESS StatusBlkPhy;
3404 /* Statistics block. */
3405 PT3_STATS_BLOCK pStatsBlkVirt;
3406 LM_PHYSICAL_ADDRESS StatsBlkPhy;
3408 /* Current receive mask. */
3409 LM_UINT32 ReceiveMask;
3411 /* Task offload capabilities. */
3412 LM_TASK_OFFLOAD TaskOffloadCap;
3414 /* Task offload selected. */
3415 LM_TASK_OFFLOAD TaskToOffload;
3417 /* Wake up capability. */
3418 LM_WAKE_UP_MODE WakeUpModeCap;
3420 /* Wake up capability. */
3421 LM_WAKE_UP_MODE WakeUpMode;
3424 LM_FLOW_CONTROL FlowControlCap;
3425 LM_FLOW_CONTROL FlowControl;
3427 /* interrupt status tag */
3430 /* Current node address. */
3431 LM_UINT8 NodeAddress[8];
3433 /* The adapter's node address. */
3434 LM_UINT8 PermanentNodeAddress[8];
3437 LM_UINT16 BusNum; // Init by the upper module.
3438 LM_UINT8 DevNum; // Init by the upper module.
3439 LM_UINT8 FunctNum; // Init by the upper module.
3440 LM_UINT16 PciVendorId;
3441 LM_UINT16 PciDeviceId;
3445 LM_UINT8 CacheLineSize;
3447 LM_UINT32 PciCommandStatusWords;
3448 LM_UINT32 ChipRevId;
3449 LM_UINT16 SubsystemVendorId;
3450 LM_UINT16 SubsystemId;
3451 PLM_UINT8 pMappedMemBase;
3453 /* Saved PCI configuration registers for restoring after a reset. */
3454 LM_UINT32 SavedCacheLineReg;
3460 /* Requested phy settings. */
3461 LM_LINE_SPEED RequestedLineSpeed;
3462 LM_DUPLEX_MODE RequestedDuplexMode;
3464 /* Disable auto-negotiation. */
3465 LM_UINT32 DisableAutoNeg;
3467 LM_UINT32 AutoNegJustInited;
3469 /* Ways for the MAC to get link change interrupt. */
3470 LM_UINT32 PhyIntMode;
3471 #define T3_PHY_INT_MODE_AUTO 0
3472 #define T3_PHY_INT_MODE_MI_INTERRUPT 1
3473 #define T3_PHY_INT_MODE_LINK_READY 2
3474 #define T3_PHY_INT_MODE_AUTO_POLLING 3
3476 /* Ways to determine link change status. */
3477 LM_UINT32 LinkChngMode;
3478 #define T3_LINK_CHNG_MODE_AUTO 0
3479 #define T3_LINK_CHNG_MODE_USE_STATUS_REG 1
3480 #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2
3486 #define WOL_SPEED_10MB 1
3487 #define WOL_SPEED_100MB 2
3490 #define PHY_RESET_ON_INIT 0x01
3491 #define PHY_RESET_ON_LINKDOWN 0x02
3492 #define PHY_ADC_FIX 0x04
3493 #define PHY_CHECK_TAPS_AFTER_RESET 0x08
3494 #define PHY_5704_A0_FIX 0x10
3495 #define PHY_ETHERNET_WIRESPEED 0x20
3496 #define PHY_5705_5750_FIX 0x40
3497 #define PHY_NO_GIGABIT 0x80
3498 #define PHY_CAPACITIVE_COUPLING 0x100
3499 #define PHY_IS_FIBER 0x200
3500 #define PHY_FIBER_FALLBACK 0x400
3503 LM_UINT32 RestoreOnWakeUp;
3504 LM_LINE_SPEED WakeUpRequestedLineSpeed;
3505 LM_DUPLEX_MODE WakeUpRequestedDuplexMode;
3506 LM_UINT32 WakeUpDisableAutoNeg;
3508 /* Current phy settings. */
3509 LM_LINE_SPEED LineSpeed;
3510 LM_LINE_SPEED OldLineSpeed;
3511 LM_DUPLEX_MODE DuplexMode;
3512 LM_STATUS LinkStatus;
3513 LM_UINT32 advertising;
3514 LM_UINT32 advertising1000;
3516 LM_UINT32 LoopBackMode;
3518 #define LM_MAC_LOOP_BACK_MODE 1
3519 #define LM_PHY_LOOP_BACK_MODE 2
3520 #define LM_EXT_LOOP_BACK_MODE 3
3522 LM_LINE_SPEED SavedRequestedLineSpeed;
3523 LM_DUPLEX_MODE SavedRequestedDuplexMode;
3524 LM_UINT32 SavedDisableAutoNeg;
3526 LM_UINT32 MulticastHash[4];
3530 #define ASF_ENABLED 1
3531 #define ASF_NEW_HANDSHAKE 2 /* if set, this bit implies ASF enabled as well */
3533 /* Split Mode flags */
3534 LM_UINT32 SplitModeMaxReq;
3536 #define SPLIT_MODE_5704_MAX_REQ 3
3541 /* Shutdown flag. Set by the upper module. */
3542 LM_BOOL ShuttingDown;
3544 /* Flag to determine whether to call LM_QueueRxPackets or not in */
3545 /* LM_ResetAdapter routine. */
3546 LM_BOOL QueueRxPackets;
3552 LM_UINT32 NvramSize;
3554 #if INCLUDE_TBI_SUPPORT
3555 /* Autoneg state info. */
3556 AN_STATE_INFO AnInfo;
3559 /* set if we have a SERDES PHY. */
3560 #define ENABLE_TBI_FLAG 0x1
3561 #define TBI_POLLING_INTR_FLAG 0x2
3562 #define TBI_PURE_POLLING_FLAG 0x4
3563 #define TBI_POLLING_FLAGS (TBI_POLLING_INTR_FLAG | TBI_PURE_POLLING_FLAG)
3564 #define TBI_DO_PREEMPHASIS 0x8
3566 LM_UINT32 IgnoreTbiLinkChange;
3568 #ifdef BCM_NAPI_RXPOLL
3569 volatile LM_UINT32 RxPoll;
3572 char BootCodeVer[16];
3573 char IPMICodeVer[24];
3574 char BusSpeedStr[24];
3576 FLASHINFO flashinfo;
3577 LM_UINT8 flashbuffer[256];
3581 #define T3_REG_CPU_VIEW 0xc0000000
3583 #define T3_BLOCK_DMA_RD (1 << 0)
3584 #define T3_BLOCK_DMA_COMP (1 << 1)
3585 #define T3_BLOCK_RX_BD_INITIATOR (1 << 2)
3586 #define T3_BLOCK_RX_BD_COMP (1 << 3)
3587 #define T3_BLOCK_DMA_WR (1 << 4)
3588 #define T3_BLOCK_MSI_HANDLER (1 << 5)
3589 #define T3_BLOCK_RX_LIST_PLMT (1 << 6)
3590 #define T3_BLOCK_RX_LIST_SELECTOR (1 << 7)
3591 #define T3_BLOCK_RX_DATA_INITIATOR (1 << 8)
3592 #define T3_BLOCK_RX_DATA_COMP (1 << 9)
3593 #define T3_BLOCK_HOST_COALESING (1 << 10)
3594 #define T3_BLOCK_MAC_RX_ENGINE (1 << 11)
3595 #define T3_BLOCK_MBUF_CLUSTER_FREE (1 << 12)
3596 #define T3_BLOCK_SEND_BD_INITIATOR (1 << 13)
3597 #define T3_BLOCK_SEND_BD_COMP (1 << 14)
3598 #define T3_BLOCK_SEND_BD_SELECTOR (1 << 15)
3599 #define T3_BLOCK_SEND_DATA_INITIATOR (1 << 16)
3600 #define T3_BLOCK_SEND_DATA_COMP (1 << 17)
3601 #define T3_BLOCK_MAC_TX_ENGINE (1 << 18)
3602 #define T3_BLOCK_MEM_ARBITOR (1 << 19)
3603 #define T3_BLOCK_MBUF_MANAGER (1 << 20)
3604 #define T3_BLOCK_MAC_GLOBAL (1 << 21)
3607 #define LM_DISABLE 2
3609 #define RX_CPU_EVT_SW0 0
3610 #define RX_CPU_EVT_SW1 1
3611 #define RX_CPU_EVT_RLP 2
3612 #define RX_CPU_EVT_SW3 3
3613 #define RX_CPU_EVT_RLS 4
3614 #define RX_CPU_EVT_SW4 5
3615 #define RX_CPU_EVT_RX_BD_COMP 6
3616 #define RX_CPU_EVT_SW5 7
3617 #define RX_CPU_EVT_RDI 8
3618 #define RX_CPU_EVT_DMA_WR 9
3619 #define RX_CPU_EVT_DMA_RD 10
3620 #define RX_CPU_EVT_SWQ 11
3621 #define RX_CPU_EVT_SW6 12
3622 #define RX_CPU_EVT_RDC 13
3623 #define RX_CPU_EVT_SW7 14
3624 #define RX_CPU_EVT_HOST_COALES 15
3625 #define RX_CPU_EVT_SW8 16
3626 #define RX_CPU_EVT_HIGH_DMA_WR 17
3627 #define RX_CPU_EVT_HIGH_DMA_RD 18
3628 #define RX_CPU_EVT_SW9 19
3629 #define RX_CPU_EVT_DMA_ATTN 20
3630 #define RX_CPU_EVT_LOW_P_MBOX 21
3631 #define RX_CPU_EVT_HIGH_P_MBOX 22
3632 #define RX_CPU_EVT_SW10 23
3633 #define RX_CPU_EVT_TX_CPU_ATTN 24
3634 #define RX_CPU_EVT_MAC_ATTN 25
3635 #define RX_CPU_EVT_RX_CPU_ATTN 26
3636 #define RX_CPU_EVT_FLOW_ATTN 27
3637 #define RX_CPU_EVT_SW11 28
3638 #define RX_CPU_EVT_TIMER 29
3639 #define RX_CPU_EVT_SW12 30
3640 #define RX_CPU_EVT_SW13 31
3643 #define RX_CPU_EVENT_SW_EVENT0 (1 << RX_CPU_EVT_SW0)
3644 #define RX_CPU_EVENT_SW_EVENT1 (1 << RX_CPU_EVT_SW1)
3645 #define RX_CPU_EVENT_RLP (1 << RX_CPU_EVT_RLP)
3646 #define RX_CPU_EVENT_SW_EVENT3 (1 << RX_CPU_EVT_SW3)
3647 #define RX_CPU_EVENT_RLS (1 << RX_CPU_EVT_RLS)
3648 #define RX_CPU_EVENT_SW_EVENT4 (1 << RX_CPU_EVT_SW4)
3649 #define RX_CPU_EVENT_RX_BD_COMP (1 << RX_CPU_EVT_RX_BD_COMP)
3650 #define RX_CPU_EVENT_SW_EVENT5 (1 << RX_CPU_EVT_SW5)
3651 #define RX_CPU_EVENT_RDI (1 << RX_CPU_EVT_RDI)
3652 #define RX_CPU_EVENT_DMA_WR (1 << RX_CPU_EVT_DMA_WR)
3653 #define RX_CPU_EVENT_DMA_RD (1 << RX_CPU_EVT_DMA_RD)
3654 #define RX_CPU_EVENT_SWQ (1 << RX_CPU_EVT_SWQ)
3655 #define RX_CPU_EVENT_SW_EVENT6 (1 << RX_CPU_EVT_SW6)
3656 #define RX_CPU_EVENT_RDC (1 << RX_CPU_EVT_RDC)
3657 #define RX_CPU_EVENT_SW_EVENT7 (1 << RX_CPU_EVT_SW7)
3658 #define RX_CPU_EVENT_HOST_COALES (1 << RX_CPU_EVT_HOST_COALES)
3659 #define RX_CPU_EVENT_SW_EVENT8 (1 << RX_CPU_EVT_SW8)
3660 #define RX_CPU_EVENT_HIGH_DMA_WR (1 << RX_CPU_EVT_HIGH_DMA_WR)
3661 #define RX_CPU_EVENT_HIGH_DMA_RD (1 << RX_CPU_EVT_HIGH_DMA_RD)
3662 #define RX_CPU_EVENT_SW_EVENT9 (1 << RX_CPU_EVT_SW9)
3663 #define RX_CPU_EVENT_DMA_ATTN (1 << RX_CPU_EVT_DMA_ATTN)
3664 #define RX_CPU_EVENT_LOW_P_MBOX (1 << RX_CPU_EVT_LOW_P_MBOX)
3665 #define RX_CPU_EVENT_HIGH_P_MBOX (1 << RX_CPU_EVT_HIGH_P_MBOX)
3666 #define RX_CPU_EVENT_SW_EVENT10 (1 << RX_CPU_EVT_SW10)
3667 #define RX_CPU_EVENT_TX_CPU_ATTN (1 << RX_CPU_EVT_TX_CPU_ATTN)
3668 #define RX_CPU_EVENT_MAC_ATTN (1 << RX_CPU_EVT_MAC_ATTN)
3669 #define RX_CPU_EVENT_RX_CPU_ATTN (1 << RX_CPU_EVT_RX_CPU_ATTN)
3670 #define RX_CPU_EVENT_FLOW_ATTN (1 << RX_CPU_EVT_FLOW_ATTN)
3671 #define RX_CPU_EVENT_SW_EVENT11 (1 << RX_CPU_EVT_SW11)
3672 #define RX_CPU_EVENT_TIMER (1 << RX_CPU_EVT_TIMER)
3673 #define RX_CPU_EVENT_SW_EVENT12 (1 << RX_CPU_EVT_SW12)
3674 #define RX_CPU_EVENT_SW_EVENT13 (1 << RX_CPU_EVT_SW13)
3676 #define RX_CPU_MASK (RX_CPU_EVENT_SW_EVENT0 | \
3677 RX_CPU_EVENT_RLP | \
3678 RX_CPU_EVENT_RDI | \
3681 #define TX_CPU_EVT_SW0 0
3682 #define TX_CPU_EVT_SW1 1
3683 #define TX_CPU_EVT_SW2 2
3684 #define TX_CPU_EVT_SW3 3
3685 #define TX_CPU_EVT_TX_MAC 4
3686 #define TX_CPU_EVT_SW4 5
3687 #define TX_CPU_EVT_SBDC 6
3688 #define TX_CPU_EVT_SW5 7
3689 #define TX_CPU_EVT_SDI 8
3690 #define TX_CPU_EVT_DMA_WR 9
3691 #define TX_CPU_EVT_DMA_RD 10
3692 #define TX_CPU_EVT_SWQ 11
3693 #define TX_CPU_EVT_SW6 12
3694 #define TX_CPU_EVT_SDC 13
3695 #define TX_CPU_EVT_SW7 14
3696 #define TX_CPU_EVT_HOST_COALES 15
3697 #define TX_CPU_EVT_SW8 16
3698 #define TX_CPU_EVT_HIGH_DMA_WR 17
3699 #define TX_CPU_EVT_HIGH_DMA_RD 18
3700 #define TX_CPU_EVT_SW9 19
3701 #define TX_CPU_EVT_DMA_ATTN 20
3702 #define TX_CPU_EVT_LOW_P_MBOX 21
3703 #define TX_CPU_EVT_HIGH_P_MBOX 22
3704 #define TX_CPU_EVT_SW10 23
3705 #define TX_CPU_EVT_RX_CPU_ATTN 24
3706 #define TX_CPU_EVT_MAC_ATTN 25
3707 #define TX_CPU_EVT_TX_CPU_ATTN 26
3708 #define TX_CPU_EVT_FLOW_ATTN 27
3709 #define TX_CPU_EVT_SW11 28
3710 #define TX_CPU_EVT_TIMER 29
3711 #define TX_CPU_EVT_SW12 30
3712 #define TX_CPU_EVT_SW13 31
3716 #define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0)
3717 #define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1)
3718 #define TX_CPU_EVENT_SW_EVENT2 (1 << TX_CPU_EVT_SW2)
3719 #define TX_CPU_EVENT_SW_EVENT3 (1 << TX_CPU_EVT_SW3)
3720 #define TX_CPU_EVENT_TX_MAC (1 << TX_CPU_EVT_TX_MAC)
3721 #define TX_CPU_EVENT_SW_EVENT4 (1 << TX_CPU_EVT_SW4)
3722 #define TX_CPU_EVENT_SBDC (1 << TX_CPU_EVT_SBDC)
3723 #define TX_CPU_EVENT_SW_EVENT5 (1 << TX_CPU_EVT_SW5)
3724 #define TX_CPU_EVENT_SDI (1 << TX_CPU_EVT_SDI)
3725 #define TX_CPU_EVENT_DMA_WR (1 << TX_CPU_EVT_DMA_WR)
3726 #define TX_CPU_EVENT_DMA_RD (1 << TX_CPU_EVT_DMA_RD)
3727 #define TX_CPU_EVENT_SWQ (1 << TX_CPU_EVT_SWQ)
3728 #define TX_CPU_EVENT_SW_EVENT6 (1 << TX_CPU_EVT_SW6)
3729 #define TX_CPU_EVENT_SDC (1 << TX_CPU_EVT_SDC)
3730 #define TX_CPU_EVENT_SW_EVENT7 (1 << TX_CPU_EVT_SW7)
3731 #define TX_CPU_EVENT_HOST_COALES (1 << TX_CPU_EVT_HOST_COALES)
3732 #define TX_CPU_EVENT_SW_EVENT8 (1 << TX_CPU_EVT_SW8)
3733 #define TX_CPU_EVENT_HIGH_DMA_WR (1 << TX_CPU_EVT_HIGH_DMA_WR)
3734 #define TX_CPU_EVENT_HIGH_DMA_RD (1 << TX_CPU_EVT_HIGH_DMA_RD)
3735 #define TX_CPU_EVENT_SW_EVENT9 (1 << TX_CPU_EVT_SW9)
3736 #define TX_CPU_EVENT_DMA_ATTN (1 << TX_CPU_EVT_DMA_ATTN)
3737 #define TX_CPU_EVENT_LOW_P_MBOX (1 << TX_CPU_EVT_LOW_P_MBOX)
3738 #define TX_CPU_EVENT_HIGH_P_MBOX (1 << TX_CPU_EVT_HIGH_P_MBOX)
3739 #define TX_CPU_EVENT_SW_EVENT10 (1 << TX_CPU_EVT_SW10)
3740 #define TX_CPU_EVENT_RX_CPU_ATTN (1 << TX_CPU_EVT_RX_CPU_ATTN)
3741 #define TX_CPU_EVENT_MAC_ATTN (1 << TX_CPU_EVT_MAC_ATTN)
3742 #define TX_CPU_EVENT_TX_CPU_ATTN (1 << TX_CPU_EVT_TX_CPU_ATTN)
3743 #define TX_CPU_EVENT_FLOW_ATTN (1 << TX_CPU_EVT_FLOW_ATTN)
3744 #define TX_CPU_EVENT_SW_EVENT11 (1 << TX_CPU_EVT_SW11)
3745 #define TX_CPU_EVENT_TIMER (1 << TX_CPU_EVT_TIMER)
3746 #define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12)
3747 #define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13)
3750 #define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \
3751 TX_CPU_EVENT_SDI | \
3755 #define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29)
3756 #define T3_FTQ_TYPE1_PASS_BIT (1 << 30)
3757 #define T3_FTQ_TYPE1_SKIP_BIT (1 << 31)
3759 #define T3_FTQ_TYPE2_UNDERFLOW_BIT (1 << 13)
3760 #define T3_FTQ_TYPE2_PASS_BIT (1 << 14)
3761 #define T3_FTQ_TYPE2_SKIP_BIT (1 << 15)
3763 #define T3_QID_DMA_READ 1
3764 #define T3_QID_DMA_HIGH_PRI_READ 2
3765 #define T3_QID_DMA_COMP_DX 3
3766 #define T3_QID_SEND_BD_COMP 4
3767 #define T3_QID_SEND_DATA_INITIATOR 5
3768 #define T3_QID_DMA_WRITE 6
3769 #define T3_QID_DMA_HIGH_PRI_WRITE 7
3770 #define T3_QID_SW_TYPE_1 8
3771 #define T3_QID_SEND_DATA_COMP 9
3772 #define T3_QID_HOST_COALESCING 10
3773 #define T3_QID_MAC_TX 11
3774 #define T3_QID_MBUF_CLUSTER_FREE 12
3775 #define T3_QID_RX_BD_COMP 13
3776 #define T3_QID_RX_LIST_PLM 14
3777 #define T3_QID_RX_DATA_BD_INITIATOR 15
3778 #define T3_QID_RX_DATA_COMP 16
3779 #define T3_QID_SW_TYPE2 17
3781 LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
3782 PT3_FWIMG_INFO pFwImg,
3784 LM_UINT32 StartCpu);
3786 /******************************************************************************/
3787 /* NIC register read/write macros. */
3788 /******************************************************************************/
3790 /* MAC register access. */
3791 LM_UINT32 LM_RegRd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
3793 LM_VOID LM_RegRdBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
3795 LM_VOID LM_RegWr(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
3796 LM_UINT32 Value32, LM_UINT32 ReadBack);
3798 LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
3799 LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
3802 /* MAC memory access. */
3803 LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
3805 LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
3808 #define MB_REG_WR(pDevice, OffsetName, Value32) \
3809 ((pDevice)->Flags & UNDI_FIX_FLAG) ? \
3810 LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \
3812 (void) MM_MEMWRITEL(&((pDevice)->pMemView->OffsetName), Value32)
3814 #define MB_REG_RD(pDevice, OffsetName) \
3815 (((pDevice)->Flags & UNDI_FIX_FLAG) ? \
3816 LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \
3817 MM_MEMREADL(&((pDevice)->pMemView->OffsetName)))
3819 #define REG_RD(pDevice, OffsetName) \
3820 LM_RegRd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName))
3822 #define REG_RD_BACK(pDevice, OffsetName) \
3823 LM_RegRdBack(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName))
3825 #define REG_WR(pDevice, OffsetName, Value32) \
3826 LM_RegWr(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32, TRUE)
3828 #define RAW_REG_WR(pDevice, OffsetName, Value32) \
3829 LM_RegWr(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32, FALSE)
3831 #define REG_RD_OFFSET(pDevice, Offset) \
3832 MM_MEMREADL(((LM_UINT8 *) (pDevice)->pMemView + Offset))
3834 #define REG_WR_OFFSET(pDevice, Offset, Value32) \
3835 MM_MEMWRITEL(((LM_UINT8 *) (pDevice)->pMemView + Offset), Value32)
3837 #define MEM_RD(pDevice, AddrName) \
3838 LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName))
3839 #define MEM_WR(pDevice, AddrName, Value32) \
3840 LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32)
3842 #define MEM_RD_OFFSET(pDevice, Offset) \
3843 LM_MemRdInd(pDevice, Offset)
3844 #define MEM_WR_OFFSET(pDevice, Offset, Value32) \
3845 LM_MemWrInd(pDevice, Offset, Value32)
3848 #endif /* TIGON3_H */