5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
18 * The original author:
19 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
22 * macro Maciej W. Rozycki <macro@ds2.pg.gda.pl>
25 * I'd like to thank Patricia Cross for helping me get started with
26 * Linux, David Davies for a lot of help upgrading and configuring
27 * my development system and for answering many OS and driver
28 * development questions, and Alan Cox for recommendations and
29 * integration help on getting FDDI support into Linux. LVS
31 * Driver Architecture:
32 * The driver architecture is largely based on previous driver work
33 * for other operating systems. The upper edge interface and
34 * functions were largely taken from existing Linux device drivers
35 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
39 * The driver scans for supported EISA adapters by reading the
40 * SLOT ID register for each EISA slot and making a match
41 * against the expected value.
43 * Bus-Specific Initialization -
44 * This driver currently supports both EISA and PCI controller
45 * families. While the custom DMA chip and FDDI logic is similar
46 * or identical, the bus logic is very different. After
47 * initialization, the only bus-specific differences is in how the
48 * driver enables and disables interrupts. Other than that, the
49 * run-time critical code behaves the same on both families.
50 * It's important to note that both adapter families are configured
51 * to I/O map, rather than memory map, the adapter registers.
54 * In the driver open routine, the driver ISR (interrupt service
55 * routine) is registered and the adapter is brought to an
56 * operational state. In the driver close routine, the opposite
57 * occurs; the driver ISR is deregistered and the adapter is
58 * brought to a safe, but closed state. Users may use consecutive
59 * commands to bring the adapter up and down as in the following
66 * Apparently, there is no shutdown or halt routine support under
67 * Linux. This routine would be called during "reboot" or
68 * "shutdown" to allow the driver to place the adapter in a safe
69 * state before a warm reboot occurs. To be really safe, the user
70 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
71 * to ensure that the adapter DMA engine is taken off-line. However,
72 * the current driver code anticipates this problem and always issues
73 * a soft reset of the adapter at the beginning of driver initialization.
74 * A future driver enhancement in this area may occur in 2.1.X where
75 * Alan indicated that a shutdown handler may be implemented.
77 * Interrupt Service Routine -
78 * The driver supports shared interrupts, so the ISR is registered for
79 * each board with the appropriate flag and the pointer to that board's
80 * device structure. This provides the context during interrupt
81 * processing to support shared interrupts and multiple boards.
83 * Interrupt enabling/disabling can occur at many levels. At the host
84 * end, you can disable system interrupts, or disable interrupts at the
85 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
86 * have a bus-logic chip interrupt enable/disable as well as a DMA
87 * controller interrupt enable/disable.
89 * The driver currently enables and disables adapter interrupts at the
90 * bus-logic chip and assumes that Linux will take care of clearing or
91 * acknowledging any host-based interrupt chips.
94 * Control functions are those used to support functions such as adding
95 * or deleting multicast addresses, enabling or disabling packet
96 * reception filters, or other custom/proprietary commands. Presently,
97 * the driver supports the "get statistics", "set multicast list", and
98 * "set mac address" functions defined by Linux. A list of possible
99 * enhancements include:
101 * - Custom ioctl interface for executing port interface commands
102 * - Custom ioctl interface for adding unicast addresses to
103 * adapter CAM (to support bridge functions).
104 * - Custom ioctl interface for supporting firmware upgrades.
106 * Hardware (port interface) Support Routines -
107 * The driver function names that start with "dfx_hw_" represent
108 * low-level port interface routines that are called frequently. They
109 * include issuing a DMA or port control command to the adapter,
110 * resetting the adapter, or reading the adapter state. Since the
111 * driver initialization and run-time code must make calls into the
112 * port interface, these routines were written to be as generic and
113 * usable as possible.
116 * The adapter DMA engine supports a 256 entry receive descriptor block
117 * of which up to 255 entries can be used at any given time. The
118 * architecture is a standard producer, consumer, completion model in
119 * which the driver "produces" receive buffers to the adapter, the
120 * adapter "consumes" the receive buffers by DMAing incoming packet data,
121 * and the driver "completes" the receive buffers by servicing the
122 * incoming packet, then "produces" a new buffer and starts the cycle
123 * again. Receive buffers can be fragmented in up to 16 fragments
124 * (descriptor entries). For simplicity, this driver posts
125 * single-fragment receive buffers of 4608 bytes, then allocates a
126 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
127 * utilization, a better approach would be to pass up the receive
128 * buffer (no extra copy) then allocate and post a replacement buffer.
129 * This is a performance enhancement that should be looked into at
133 * Like the receive path, the adapter DMA engine supports a 256 entry
134 * transmit descriptor block of which up to 255 entries can be used at
135 * any given time. Transmit buffers can be fragmented in up to 255
136 * fragments (descriptor entries). This driver always posts one
137 * fragment per transmit packet request.
139 * The fragment contains the entire packet from FC to end of data.
140 * Before posting the buffer to the adapter, the driver sets a three-byte
141 * packet request header (PRH) which is required by the Motorola MAC chip
142 * used on the adapters. The PRH tells the MAC the type of token to
143 * receive/send, whether or not to generate and append the CRC, whether
144 * synchronous or asynchronous framing is used, etc. Since the PRH
145 * definition is not necessarily consistent across all FDDI chipsets,
146 * the driver, rather than the common FDDI packet handler routines,
149 * To reduce the amount of descriptor fetches needed per transmit request,
150 * the driver takes advantage of the fact that there are at least three
151 * bytes available before the skb->data field on the outgoing transmit
152 * request. This is guaranteed by having fddi_setup() in net_init.c set
153 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
154 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
155 * bytes which we'll use to store the PRH.
157 * There's a subtle advantage to adding these pad bytes to the
158 * hard_header_len, it ensures that the data portion of the packet for
159 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
160 * implementations may not need the extra padding and can start copying
161 * or DMAing directly from the FC byte which starts at skb->data. Should
162 * another driver implementation need ADDITIONAL padding, the net_init.c
163 * module should be updated and dev->hard_header_len should be increased.
164 * NOTE: To maintain the alignment on the data portion of the packet,
165 * dev->hard_header_len should always be evenly divisible by 4 and at
166 * least 24 bytes in size.
168 * Modification History:
169 * Date Name Description
170 * 16-Aug-96 LVS Created.
171 * 20-Aug-96 LVS Updated dfx_probe so that version information
172 * string is only displayed if 1 or more cards are
173 * found. Changed dfx_rcv_queue_process to copy
174 * 3 NULL bytes before FC to ensure that data is
175 * longword aligned in receive buffer.
176 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
177 * LLC group promiscuous mode if multicast list
178 * is too large. LLC individual/group promiscuous
179 * mode is now disabled if IFF_PROMISC flag not set.
180 * dfx_xmt_queue_pkt no longer checks for NULL skb
181 * on Alan Cox recommendation. Added node address
183 * 12-Sep-96 LVS Reset current address to factory address during
184 * device open. Updated transmit path to post a
185 * single fragment which includes PRH->end of data.
186 * Mar 2000 AC Did various cleanups for 2.3.x
187 * Jun 2000 jgarzik PCI and resource alloc cleanups
188 * Jul 2000 tjeerd Much cleanup and some bug fixes
189 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
190 * Feb 2001 Skb allocation fixes
191 * Feb 2001 davej PCI enable cleanups.
192 * 04 Aug 2003 macro Converted to the DMA API.
197 #include <linux/module.h>
198 #include <linux/kernel.h>
199 #include <linux/string.h>
200 #include <linux/errno.h>
201 #include <linux/ioport.h>
202 #include <linux/slab.h>
203 #include <linux/interrupt.h>
204 #include <linux/pci.h>
205 #include <linux/delay.h>
206 #include <linux/init.h>
207 #include <linux/netdevice.h>
208 #include <linux/fddidevice.h>
209 #include <linux/skbuff.h>
211 #include <asm/byteorder.h>
212 #include <asm/bitops.h>
217 /* Version information string - should be updated prior to each new release!!! */
219 static char version[] __devinitdata =
220 "defxx.c:v1.06 2003/08/04 Lawrence V. Stefani and others\n";
222 #define DYNAMIC_BUFFERS 1
224 #define SKBUFF_RX_COPYBREAK 200
226 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
227 * alignment for compatibility with old EISA boards.
229 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
231 /* Define module-wide (static) routines */
233 static void dfx_bus_init(struct net_device *dev);
234 static void dfx_bus_config_check(DFX_board_t *bp);
236 static int dfx_driver_init(struct net_device *dev);
237 static int dfx_adap_init(DFX_board_t *bp, int get_buffers);
239 static int dfx_open(struct net_device *dev);
240 static int dfx_close(struct net_device *dev);
242 static void dfx_int_pr_halt_id(DFX_board_t *bp);
243 static void dfx_int_type_0_process(DFX_board_t *bp);
244 static void dfx_int_common(struct net_device *dev);
245 static void dfx_interrupt(int irq, void *dev_id, struct pt_regs *regs);
247 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
248 static void dfx_ctl_set_multicast_list(struct net_device *dev);
249 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
250 static int dfx_ctl_update_cam(DFX_board_t *bp);
251 static int dfx_ctl_update_filters(DFX_board_t *bp);
253 static int dfx_hw_dma_cmd_req(DFX_board_t *bp);
254 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
255 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
256 static int dfx_hw_adap_state_rd(DFX_board_t *bp);
257 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
259 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers);
260 static void dfx_rcv_queue_process(DFX_board_t *bp);
261 static void dfx_rcv_flush(DFX_board_t *bp);
263 static int dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev);
264 static int dfx_xmt_done(DFX_board_t *bp);
265 static void dfx_xmt_flush(DFX_board_t *bp);
267 /* Define module-wide (static) variables */
269 static struct net_device *root_dfx_eisa_dev;
273 * =======================
274 * = dfx_port_write_byte =
275 * = dfx_port_read_byte =
276 * = dfx_port_write_long =
277 * = dfx_port_read_long =
278 * =======================
281 * Routines for reading and writing values from/to adapter
287 * bp - pointer to board information
288 * offset - register offset from base I/O address
289 * data - for dfx_port_write_byte and dfx_port_write_long, this
290 * is a value to write.
291 * for dfx_port_read_byte and dfx_port_read_byte, this
292 * is a pointer to store the read value.
294 * Functional Description:
295 * These routines perform the correct operation to read or write
296 * the adapter register.
298 * EISA port block base addresses are based on the slot number in which the
299 * controller is installed. For example, if the EISA controller is installed
300 * in slot 4, the port block base address is 0x4000. If the controller is
301 * installed in slot 2, the port block base address is 0x2000, and so on.
302 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
303 * registers using the register offsets defined in DEFXX.H.
305 * PCI port block base addresses are assigned by the PCI BIOS or system
306 * firmware. There is one 128 byte port block which can be accessed. It
307 * allows for I/O mapping of both PDQ and PFI registers using the register
308 * offsets defined in DEFXX.H.
314 * bp->base_addr is a valid base I/O address for this adapter.
315 * offset is a valid register offset for this adapter.
318 * Rather than produce macros for these functions, these routines
319 * are defined using "inline" to ensure that the compiler will
320 * generate inline code and not waste a procedure call and return.
321 * This provides all the benefits of macros, but with the
322 * advantage of strict data type checking.
325 static inline void dfx_port_write_byte(
332 u16 port = bp->base_addr + offset;
337 static inline void dfx_port_read_byte(
344 u16 port = bp->base_addr + offset;
349 static inline void dfx_port_write_long(
356 u16 port = bp->base_addr + offset;
361 static inline void dfx_port_read_long(
368 u16 port = bp->base_addr + offset;
376 * = dfx_init_one_pci_or_eisa =
380 * Initializes a supported FDDI EISA or PCI controller
386 * pdev - pointer to pci device information (NULL for EISA)
387 * ioaddr - pointer to port (NULL for PCI)
389 * Functional Description:
392 * 0 - This device (fddi0, fddi1, etc) configured successfully
393 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
396 * It compiles so it should work :-( (PCI cards do :-)
399 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
400 * initialized and the board resources are read and stored in
401 * the device structure.
403 static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, long ioaddr)
405 struct net_device *dev;
406 DFX_board_t *bp; /* board pointer */
407 int alloc_size; /* total buffer size used */
411 static int version_disp;
413 if (!version_disp) /* display version info if adapter is found */
415 version_disp = 1; /* set display flag to TRUE so that */
416 printk(version); /* we only display this string ONCE */
420 dev = alloc_fddidev(sizeof(*bp));
422 printk (KERN_ERR "defxx: unable to allocate fddidev, aborting\n");
426 /* Enable PCI device. */
428 err = pci_enable_device (pdev);
429 if (err) goto err_out;
430 ioaddr = pci_resource_start (pdev, 1);
433 SET_MODULE_OWNER(dev);
434 SET_NETDEV_DEV(dev, &pdev->dev);
438 if (!request_region (ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, dev->name)) {
439 printk (KERN_ERR "%s: Cannot reserve I/O resource 0x%x @ 0x%lx, aborting\n",
440 dev->name, PFI_K_CSR_IO_LEN, ioaddr);
445 /* Initialize new device structure */
447 dev->base_addr = ioaddr; /* save port (I/O) base address */
449 dev->get_stats = dfx_ctl_get_stats;
450 dev->open = dfx_open;
451 dev->stop = dfx_close;
452 dev->hard_start_xmit = dfx_xmt_queue_pkt;
453 dev->set_multicast_list = dfx_ctl_set_multicast_list;
454 dev->set_mac_address = dfx_ctl_set_mac_address;
458 bp->bus_type = DFX_BUS_TYPE_EISA;
459 bp->next = root_dfx_eisa_dev;
460 root_dfx_eisa_dev = dev;
463 bp->bus_type = DFX_BUS_TYPE_PCI;
465 pci_set_drvdata (pdev, dev);
466 pci_set_master (pdev);
469 if (dfx_driver_init(dev) != DFX_K_SUCCESS) {
474 err = register_netdev(dev);
481 alloc_size = sizeof(PI_DESCR_BLOCK) +
482 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
483 #ifndef DYNAMIC_BUFFERS
484 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
486 sizeof(PI_CONSUMER_BLOCK) +
487 (PI_ALIGN_K_DESC_BLK - 1);
489 pci_free_consistent(pdev, alloc_size,
490 bp->kmalloced, bp->kmalloced_dma);
492 release_region(ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN);
498 static int __devinit dfx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
500 return dfx_init_one_pci_or_eisa(pdev, 0);
503 static int __init dfx_eisa_init(void)
506 int i; /* used in for loops */
507 u16 port; /* temporary I/O (port) address */
508 u32 slot_id; /* EISA hardware (slot) ID read from adapter */
510 DBG_printk("In dfx_eisa_init...\n");
512 /* Scan for FDDI EISA controllers */
514 for (i=0; i < DFX_MAX_EISA_SLOTS; i++) /* only scan for up to 16 EISA slots */
516 port = (i << 12) + PI_ESIC_K_SLOT_ID; /* port = I/O address for reading slot ID */
517 slot_id = inl(port); /* read EISA HW (slot) ID */
518 if ((slot_id & 0xF0FFFFFF) == DEFEA_PRODUCT_ID)
520 port = (i << 12); /* recalc base addr */
522 if (dfx_init_one_pci_or_eisa(NULL, port) == 0) rc = 0;
534 * Initializes EISA and PCI controller bus-specific logic.
540 * dev - pointer to device information
542 * Functional Description:
543 * Determine and save adapter IRQ in device table,
544 * then perform bus-specific logic initialization.
550 * dev->base_addr has already been set with the proper
551 * base I/O address for this device.
554 * Interrupts are enabled at the adapter bus-specific logic.
555 * Note: Interrupts at the DMA engine (PDQ chip) are not
559 static void __devinit dfx_bus_init(struct net_device *dev)
561 DFX_board_t *bp = dev->priv;
562 u8 val; /* used for I/O read/writes */
564 DBG_printk("In dfx_bus_init...\n");
567 * Initialize base I/O address field in bp structure
569 * Note: bp->base_addr is the same as dev->base_addr.
570 * It's useful because often we'll need to read
571 * or write registers where we already have the
572 * bp pointer instead of the dev pointer. Having
573 * the base address in the bp structure will
574 * save a pointer dereference.
576 * IMPORTANT!! This field must be defined before
577 * any of the dfx_port_* inline functions are
581 bp->base_addr = dev->base_addr;
583 /* And a pointer back to the net_device struct */
586 /* Initialize adapter based on bus type */
588 if (bp->bus_type == DFX_BUS_TYPE_EISA)
590 /* Get the interrupt level from the ESIC chip */
592 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
593 switch ((val & PI_CONFIG_STAT_0_M_IRQ) >> PI_CONFIG_STAT_0_V_IRQ)
595 case PI_CONFIG_STAT_0_IRQ_K_9:
599 case PI_CONFIG_STAT_0_IRQ_K_10:
603 case PI_CONFIG_STAT_0_IRQ_K_11:
607 case PI_CONFIG_STAT_0_IRQ_K_15:
612 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
614 dfx_port_write_byte(bp, PI_ESIC_K_FUNCTION_CNTRL, PI_ESIC_K_FUNCTION_CNTRL_IO_ENB);
616 /* Set the I/O decode range of the board */
618 val = ((dev->base_addr >> 12) << PI_IO_CMP_V_SLOT);
619 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_0_1, val);
620 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_1_1, val);
622 /* Enable access to rest of module (including PDQ and packet memory) */
624 dfx_port_write_byte(bp, PI_ESIC_K_SLOT_CNTRL, PI_SLOT_CNTRL_M_ENB);
627 * Map PDQ registers into I/O space. This is done by clearing a bit
628 * in Burst Holdoff register.
631 dfx_port_read_byte(bp, PI_ESIC_K_BURST_HOLDOFF, &val);
632 dfx_port_write_byte(bp, PI_ESIC_K_BURST_HOLDOFF, (val & ~PI_BURST_HOLDOFF_M_MEM_MAP));
634 /* Enable interrupts at EISA bus interface chip (ESIC) */
636 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
637 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, (val | PI_CONFIG_STAT_0_M_INT_ENB));
641 struct pci_dev *pdev = bp->pci_dev;
643 /* Get the interrupt level from the PCI Configuration Table */
645 dev->irq = pdev->irq;
647 /* Check Latency Timer and set if less than minimal */
649 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
650 if (val < PFI_K_LAT_TIMER_MIN) /* if less than min, override with default */
652 val = PFI_K_LAT_TIMER_DEF;
653 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
656 /* Enable interrupts at PCI bus interface chip (PFI) */
658 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, (PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB));
664 * ========================
665 * = dfx_bus_config_check =
666 * ========================
669 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
670 * are illegal, then this routine will set new defaults.
676 * bp - pointer to board information
678 * Functional Description:
679 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
680 * PDQ, and all FDDI PCI controllers, all values are legal.
686 * dfx_adap_init has NOT been called yet so burst size and other items have
693 static void __devinit dfx_bus_config_check(DFX_board_t *bp)
695 int status; /* return code from adapter port control call */
696 u32 slot_id; /* EISA-bus hardware id (DEC3001, DEC3002,...) */
697 u32 host_data; /* LW data returned from port control call */
699 DBG_printk("In dfx_bus_config_check...\n");
701 /* Configuration check only valid for EISA adapter */
703 if (bp->bus_type == DFX_BUS_TYPE_EISA)
705 dfx_port_read_long(bp, PI_ESIC_K_SLOT_ID, &slot_id);
708 * First check if revision 2 EISA controller. Rev. 1 cards used
709 * PDQ revision B, so no workaround needed in this case. Rev. 3
710 * cards used PDQ revision E, so no workaround needed in this
711 * case, either. Only Rev. 2 cards used either Rev. D or E
712 * chips, so we must verify the chip revision on Rev. 2 cards.
715 if (slot_id == DEFEA_PROD_ID_2)
718 * Revision 2 FDDI EISA controller found, so let's check PDQ
719 * revision of adapter.
722 status = dfx_hw_port_ctrl_req(bp,
724 PI_SUB_CMD_K_PDQ_REV_GET,
727 if ((status != DFX_K_SUCCESS) || (host_data == 2))
730 * Either we couldn't determine the PDQ revision, or
731 * we determined that it is at revision D. In either case,
732 * we need to implement the workaround.
735 /* Ensure that the burst size is set to 8 longwords or less */
737 switch (bp->burst_size)
739 case PI_PDATA_B_DMA_BURST_SIZE_32:
740 case PI_PDATA_B_DMA_BURST_SIZE_16:
741 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
748 /* Ensure that full-duplex mode is not enabled */
750 bp->full_duplex_enb = PI_SNMP_K_FALSE;
758 * ===================
759 * = dfx_driver_init =
760 * ===================
763 * Initializes remaining adapter board structure information
764 * and makes sure adapter is in a safe state prior to dfx_open().
770 * dev - pointer to device information
772 * Functional Description:
773 * This function allocates additional resources such as the host memory
774 * blocks needed by the adapter (eg. descriptor and consumer blocks).
775 * Remaining bus initialization steps are also completed. The adapter
776 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
777 * must call dfx_open() to open the adapter and bring it on-line.
780 * DFX_K_SUCCESS - initialization succeeded
781 * DFX_K_FAILURE - initialization failed - could not allocate memory
782 * or read adapter MAC address
785 * Memory allocated from pci_alloc_consistent() call is physically
786 * contiguous, locked memory.
789 * Adapter is reset and should be in DMA_UNAVAILABLE state before
790 * returning from this routine.
793 static int __devinit dfx_driver_init(struct net_device *dev)
795 DFX_board_t *bp = dev->priv;
796 int alloc_size; /* total buffer size needed */
797 char *top_v, *curr_v; /* virtual addrs into memory block */
798 dma_addr_t top_p, curr_p; /* physical addrs into memory block */
799 u32 data; /* host data register value */
801 DBG_printk("In dfx_driver_init...\n");
803 /* Initialize bus-specific hardware registers */
808 * Initialize default values for configurable parameters
810 * Note: All of these parameters are ones that a user may
811 * want to customize. It'd be nice to break these
812 * out into Space.c or someplace else that's more
813 * accessible/understandable than this file.
816 bp->full_duplex_enb = PI_SNMP_K_FALSE;
817 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */
818 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF;
819 bp->rcv_bufs_to_post = RCV_BUFS_DEF;
822 * Ensure that HW configuration is OK
824 * Note: Depending on the hardware revision, we may need to modify
825 * some of the configurable parameters to workaround hardware
826 * limitations. We'll perform this configuration check AFTER
827 * setting the parameters to their default values.
830 dfx_bus_config_check(bp);
832 /* Disable PDQ interrupts first */
834 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
836 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
838 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
840 /* Read the factory MAC address from the adapter then save it */
842 if (dfx_hw_port_ctrl_req(bp,
846 &data) != DFX_K_SUCCESS)
848 printk("%s: Could not read adapter factory MAC address!\n", dev->name);
849 return(DFX_K_FAILURE);
851 memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32));
853 if (dfx_hw_port_ctrl_req(bp,
857 &data) != DFX_K_SUCCESS)
859 printk("%s: Could not read adapter factory MAC address!\n", dev->name);
860 return(DFX_K_FAILURE);
862 memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16));
865 * Set current address to factory address
867 * Note: Node address override support is handled through
868 * dfx_ctl_set_mac_address.
871 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
872 if (bp->bus_type == DFX_BUS_TYPE_EISA)
873 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
884 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
896 * Get memory for descriptor block, consumer block, and other buffers
897 * that need to be DMA read or written to by the adapter.
900 alloc_size = sizeof(PI_DESCR_BLOCK) +
901 PI_CMD_REQ_K_SIZE_MAX +
902 PI_CMD_RSP_K_SIZE_MAX +
903 #ifndef DYNAMIC_BUFFERS
904 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
906 sizeof(PI_CONSUMER_BLOCK) +
907 (PI_ALIGN_K_DESC_BLK - 1);
908 bp->kmalloced = top_v = pci_alloc_consistent(bp->pci_dev, alloc_size,
912 printk("%s: Could not allocate memory for host buffers and structures!\n", dev->name);
913 return(DFX_K_FAILURE);
915 memset(top_v, 0, alloc_size); /* zero out memory before continuing */
916 top_p = bp->kmalloced_dma; /* get physical address of buffer */
919 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
920 * plus the amount of memory needed was allocated. The physical address
921 * is now 8K aligned. By carving up the memory in a specific order,
922 * we'll guarantee the alignment requirements for all other structures.
924 * Note: If the assumptions change regarding the non-paged, non-cached,
925 * physically contiguous nature of the memory block or the address
926 * alignments, then we'll need to implement a different algorithm
927 * for allocating the needed memory.
930 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK);
931 curr_v = top_v + (curr_p - top_p);
933 /* Reserve space for descriptor block */
935 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
936 bp->descr_block_phys = curr_p;
937 curr_v += sizeof(PI_DESCR_BLOCK);
938 curr_p += sizeof(PI_DESCR_BLOCK);
940 /* Reserve space for command request buffer */
942 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
943 bp->cmd_req_phys = curr_p;
944 curr_v += PI_CMD_REQ_K_SIZE_MAX;
945 curr_p += PI_CMD_REQ_K_SIZE_MAX;
947 /* Reserve space for command response buffer */
949 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
950 bp->cmd_rsp_phys = curr_p;
951 curr_v += PI_CMD_RSP_K_SIZE_MAX;
952 curr_p += PI_CMD_RSP_K_SIZE_MAX;
954 /* Reserve space for the LLC host receive queue buffers */
956 bp->rcv_block_virt = curr_v;
957 bp->rcv_block_phys = curr_p;
959 #ifndef DYNAMIC_BUFFERS
960 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
961 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
964 /* Reserve space for the consumer block */
966 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
967 bp->cons_block_phys = curr_p;
969 /* Display virtual and physical addresses if debug driver */
971 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", dev->name, (long)bp->descr_block_virt, bp->descr_block_phys);
972 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
973 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
974 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
975 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->cons_block_virt, bp->cons_block_phys);
977 return(DFX_K_SUCCESS);
987 * Brings the adapter to the link avail/link unavailable state.
993 * bp - pointer to board information
994 * get_buffers - non-zero if buffers to be allocated
996 * Functional Description:
997 * Issues the low-level firmware/hardware calls necessary to bring
998 * the adapter up, or to properly reset and restore adapter during
1002 * DFX_K_SUCCESS - Adapter brought up successfully
1003 * DFX_K_FAILURE - Adapter initialization failed
1006 * bp->reset_type should be set to a valid reset type value before
1007 * calling this routine.
1010 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1011 * upon a successful return of this routine.
1014 static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
1016 DBG_printk("In dfx_adap_init...\n");
1018 /* Disable PDQ interrupts first */
1020 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1022 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1024 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
1026 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
1027 return(DFX_K_FAILURE);
1031 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1032 * so we'll acknowledge all Type 0 interrupts now before continuing.
1035 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
1038 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1040 * Note: We only need to clear host copies of these registers. The PDQ reset
1041 * takes care of the on-board register values.
1044 bp->cmd_req_reg.lword = 0;
1045 bp->cmd_rsp_reg.lword = 0;
1046 bp->rcv_xmt_reg.lword = 0;
1048 /* Clear consumer block before going to DMA_AVAILABLE state */
1050 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1052 /* Initialize the DMA Burst Size */
1054 if (dfx_hw_port_ctrl_req(bp,
1056 PI_SUB_CMD_K_BURST_SIZE_SET,
1058 NULL) != DFX_K_SUCCESS)
1060 printk("%s: Could not set adapter burst size!\n", bp->dev->name);
1061 return(DFX_K_FAILURE);
1065 * Set base address of Consumer Block
1067 * Assumption: 32-bit physical address of consumer block is 64 byte
1068 * aligned. That is, bits 0-5 of the address must be zero.
1071 if (dfx_hw_port_ctrl_req(bp,
1072 PI_PCTRL_M_CONS_BLOCK,
1073 bp->cons_block_phys,
1075 NULL) != DFX_K_SUCCESS)
1077 printk("%s: Could not set consumer block address!\n", bp->dev->name);
1078 return(DFX_K_FAILURE);
1082 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1084 * Note: We also set the literal and data swapping requirements in this
1085 * command. Since this driver presently runs on Intel platforms
1086 * which are Little Endian, we'll tell the adapter to byte swap
1087 * data only. This code will need to change when we support
1088 * Big Endian systems (eg. PowerPC).
1090 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1091 * aligned. That is, bits 0-12 of the address must be zero.
1094 if (dfx_hw_port_ctrl_req(bp,
1096 (u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA),
1098 NULL) != DFX_K_SUCCESS)
1100 printk("%s: Could not set descriptor block address!\n", bp->dev->name);
1101 return(DFX_K_FAILURE);
1104 /* Set transmit flush timeout value */
1106 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
1107 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME;
1108 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */
1109 bp->cmd_req_virt->char_set.item[0].item_index = 0;
1110 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL;
1111 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1113 printk("%s: DMA command request failed!\n", bp->dev->name);
1114 return(DFX_K_FAILURE);
1117 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1119 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
1120 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS;
1121 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb;
1122 bp->cmd_req_virt->snmp_set.item[0].item_index = 0;
1123 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ;
1124 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt;
1125 bp->cmd_req_virt->snmp_set.item[1].item_index = 0;
1126 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL;
1127 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1129 printk("%s: DMA command request failed!\n", bp->dev->name);
1130 return(DFX_K_FAILURE);
1133 /* Initialize adapter CAM */
1135 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
1137 printk("%s: Adapter CAM update failed!\n", bp->dev->name);
1138 return(DFX_K_FAILURE);
1141 /* Initialize adapter filters */
1143 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
1145 printk("%s: Adapter filters update failed!\n", bp->dev->name);
1146 return(DFX_K_FAILURE);
1150 * Remove any existing dynamic buffers (i.e. if the adapter is being
1157 /* Initialize receive descriptor block and produce buffers */
1159 if (dfx_rcv_init(bp, get_buffers))
1161 printk("%s: Receive buffer allocation failed\n", bp->dev->name);
1164 return(DFX_K_FAILURE);
1167 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1169 bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
1170 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1172 printk("%s: Start command failed\n", bp->dev->name);
1175 return(DFX_K_FAILURE);
1178 /* Initialization succeeded, reenable PDQ interrupts */
1180 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
1181 return(DFX_K_SUCCESS);
1197 * dev - pointer to device information
1199 * Functional Description:
1200 * This function brings the adapter to an operational state.
1203 * 0 - Adapter was successfully opened
1204 * -EAGAIN - Could not register IRQ or adapter initialization failed
1207 * This routine should only be called for a device that was
1208 * initialized successfully.
1211 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1212 * if the open is successful.
1215 static int dfx_open(struct net_device *dev)
1218 DFX_board_t *bp = dev->priv;
1220 DBG_printk("In dfx_open...\n");
1222 /* Register IRQ - support shared interrupts by passing device ptr */
1224 ret = request_irq(dev->irq, (void *)dfx_interrupt, SA_SHIRQ, dev->name, dev);
1226 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
1231 * Set current address to factory MAC address
1233 * Note: We've already done this step in dfx_driver_init.
1234 * However, it's possible that a user has set a node
1235 * address override, then closed and reopened the
1236 * adapter. Unless we reset the device address field
1237 * now, we'll continue to use the existing modified
1241 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1243 /* Clear local unicast/multicast address tables and counts */
1245 memset(bp->uc_table, 0, sizeof(bp->uc_table));
1246 memset(bp->mc_table, 0, sizeof(bp->mc_table));
1250 /* Disable promiscuous filter settings */
1252 bp->ind_group_prom = PI_FSTATE_K_BLOCK;
1253 bp->group_prom = PI_FSTATE_K_BLOCK;
1255 spin_lock_init(&bp->lock);
1257 /* Reset and initialize adapter */
1259 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */
1260 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
1262 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
1263 free_irq(dev->irq, dev);
1267 /* Set device structure info */
1268 netif_start_queue(dev);
1279 * Closes the device/module.
1285 * dev - pointer to device information
1287 * Functional Description:
1288 * This routine closes the adapter and brings it to a safe state.
1289 * The interrupt service routine is deregistered with the OS.
1290 * The adapter can be opened again with another call to dfx_open().
1296 * No further requests for this adapter are made after this routine is
1297 * called. dfx_open() can be called to reset and reinitialize the
1301 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1305 static int dfx_close(struct net_device *dev)
1307 DFX_board_t *bp = dev->priv;
1309 DBG_printk("In dfx_close...\n");
1311 /* Disable PDQ interrupts first */
1313 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1315 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1317 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1320 * Flush any pending transmit buffers
1322 * Note: It's important that we flush the transmit buffers
1323 * BEFORE we clear our copy of the Type 2 register.
1324 * Otherwise, we'll have no idea how many buffers
1331 * Clear Type 1 and Type 2 registers after adapter reset
1333 * Note: Even though we're closing the adapter, it's
1334 * possible that an interrupt will occur after
1335 * dfx_close is called. Without some assurance to
1336 * the contrary we want to make sure that we don't
1337 * process receive and transmit LLC frames and update
1338 * the Type 2 register with bad information.
1341 bp->cmd_req_reg.lword = 0;
1342 bp->cmd_rsp_reg.lword = 0;
1343 bp->rcv_xmt_reg.lword = 0;
1345 /* Clear consumer block for the same reason given above */
1347 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1349 /* Release all dynamically allocate skb in the receive ring. */
1353 /* Clear device structure flags */
1355 netif_stop_queue(dev);
1357 /* Deregister (free) IRQ */
1359 free_irq(dev->irq, dev);
1366 * ======================
1367 * = dfx_int_pr_halt_id =
1368 * ======================
1371 * Displays halt id's in string form.
1377 * bp - pointer to board information
1379 * Functional Description:
1380 * Determine current halt id and display appropriate string.
1392 static void dfx_int_pr_halt_id(DFX_board_t *bp)
1394 PI_UINT32 port_status; /* PDQ port status register value */
1395 PI_UINT32 halt_id; /* PDQ port status halt ID */
1397 /* Read the latest port status */
1399 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1401 /* Display halt state transition information */
1403 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
1406 case PI_HALT_ID_K_SELFTEST_TIMEOUT:
1407 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
1410 case PI_HALT_ID_K_PARITY_ERROR:
1411 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
1414 case PI_HALT_ID_K_HOST_DIR_HALT:
1415 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
1418 case PI_HALT_ID_K_SW_FAULT:
1419 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
1422 case PI_HALT_ID_K_HW_FAULT:
1423 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
1426 case PI_HALT_ID_K_PC_TRACE:
1427 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
1430 case PI_HALT_ID_K_DMA_ERROR:
1431 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
1434 case PI_HALT_ID_K_IMAGE_CRC_ERROR:
1435 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
1438 case PI_HALT_ID_K_BUS_EXCEPTION:
1439 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
1443 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
1450 * ==========================
1451 * = dfx_int_type_0_process =
1452 * ==========================
1455 * Processes Type 0 interrupts.
1461 * bp - pointer to board information
1463 * Functional Description:
1464 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1465 * is a serious fault on the adapter, then an error message is displayed
1466 * and the adapter is reset.
1468 * One tricky potential timing window is the rapid succession of "link avail"
1469 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1470 * interrupt must be done before reading the state from the Port Status
1471 * register. This is true because a state change could occur after reading
1472 * the data, but before acknowledging the interrupt. If this state change
1473 * does happen, it would be lost because the driver is using the old state,
1474 * and it will never know about the new state because it subsequently
1475 * acknowledges the state change interrupt.
1478 * read type 0 int reasons read type 0 int reasons
1479 * read adapter state ack type 0 interrupts
1480 * ack type 0 interrupts read adapter state
1481 * ... process interrupt ... ... process interrupt ...
1490 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1491 * or if the port status indicates that the adapter is halted. The driver
1492 * is responsible for reinitializing the adapter with the current CAM
1493 * contents and adapter filter settings.
1496 static void dfx_int_type_0_process(DFX_board_t *bp)
1499 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */
1500 PI_UINT32 state; /* current adap state (from port status) */
1503 * Read host interrupt Type 0 register to determine which Type 0
1504 * interrupts are pending. Immediately write it back out to clear
1508 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
1509 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
1511 /* Check for Type 0 error interrupts */
1513 if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
1514 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1515 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1517 /* Check for Non-Existent Memory error */
1519 if (type_0_status & PI_TYPE_0_STAT_M_NXM)
1520 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
1522 /* Check for Packet Memory Parity error */
1524 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
1525 printk("%s: Packet Memory Parity Error\n", bp->dev->name);
1527 /* Check for Host Bus Parity error */
1529 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
1530 printk("%s: Host Bus Parity Error\n", bp->dev->name);
1532 /* Reset adapter and bring it back on-line */
1534 bp->link_available = PI_K_FALSE; /* link is no longer available */
1535 bp->reset_type = 0; /* rerun on-board diagnostics */
1536 printk("%s: Resetting adapter...\n", bp->dev->name);
1537 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1539 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1540 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1543 printk("%s: Adapter reset successful!\n", bp->dev->name);
1547 /* Check for transmit flush interrupt */
1549 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
1551 /* Flush any pending xmt's and acknowledge the flush interrupt */
1553 bp->link_available = PI_K_FALSE; /* link is no longer available */
1554 dfx_xmt_flush(bp); /* flush any outstanding packets */
1555 (void) dfx_hw_port_ctrl_req(bp,
1556 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1562 /* Check for adapter state change */
1564 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
1566 /* Get latest adapter state */
1568 state = dfx_hw_adap_state_rd(bp); /* get adapter state */
1569 if (state == PI_STATE_K_HALTED)
1572 * Adapter has transitioned to HALTED state, try to reset
1573 * adapter to bring it back on-line. If reset fails,
1574 * leave the adapter in the broken state.
1577 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
1578 dfx_int_pr_halt_id(bp); /* display halt id as string */
1580 /* Reset adapter and bring it back on-line */
1582 bp->link_available = PI_K_FALSE; /* link is no longer available */
1583 bp->reset_type = 0; /* rerun on-board diagnostics */
1584 printk("%s: Resetting adapter...\n", bp->dev->name);
1585 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1587 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1588 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1591 printk("%s: Adapter reset successful!\n", bp->dev->name);
1593 else if (state == PI_STATE_K_LINK_AVAIL)
1595 bp->link_available = PI_K_TRUE; /* set link available flag */
1602 * ==================
1603 * = dfx_int_common =
1604 * ==================
1607 * Interrupt service routine (ISR)
1613 * bp - pointer to board information
1615 * Functional Description:
1616 * This is the ISR which processes incoming adapter interrupts.
1622 * This routine assumes PDQ interrupts have not been disabled.
1623 * When interrupts are disabled at the PDQ, the Port Status register
1624 * is automatically cleared. This routine uses the Port Status
1625 * register value to determine whether a Type 0 interrupt occurred,
1626 * so it's important that adapter interrupts are not normally
1627 * enabled/disabled at the PDQ.
1629 * It's vital that this routine is NOT reentered for the
1630 * same board and that the OS is not in another section of
1631 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1635 * Pending interrupts are serviced. Depending on the type of
1636 * interrupt, acknowledging and clearing the interrupt at the
1637 * PDQ involves writing a register to clear the interrupt bit
1638 * or updating completion indices.
1641 static void dfx_int_common(struct net_device *dev)
1643 DFX_board_t *bp = dev->priv;
1644 PI_UINT32 port_status; /* Port Status register */
1646 /* Process xmt interrupts - frequent case, so always call this routine */
1648 if(dfx_xmt_done(bp)) /* free consumed xmt packets */
1649 netif_wake_queue(dev);
1651 /* Process rcv interrupts - frequent case, so always call this routine */
1653 dfx_rcv_queue_process(bp); /* service received LLC frames */
1656 * Transmit and receive producer and completion indices are updated on the
1657 * adapter by writing to the Type 2 Producer register. Since the frequent
1658 * case is that we'll be processing either LLC transmit or receive buffers,
1659 * we'll optimize I/O writes by doing a single register write here.
1662 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
1664 /* Read PDQ Port Status register to find out which interrupts need processing */
1666 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1668 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1670 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
1671 dfx_int_type_0_process(bp); /* process Type 0 interrupts */
1681 * Interrupt processing routine
1687 * irq - interrupt vector
1688 * dev_id - pointer to device information
1689 * regs - pointer to registers structure
1691 * Functional Description:
1692 * This routine calls the interrupt processing routine for this adapter. It
1693 * disables and reenables adapter interrupts, as appropriate. We can support
1694 * shared interrupts since the incoming dev_id pointer provides our device
1695 * structure context.
1701 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1702 * on Intel-based systems) is done by the operating system outside this
1705 * System interrupts are enabled through this call.
1708 * Interrupts are disabled, then reenabled at the adapter.
1711 static void dfx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1713 struct net_device *dev = dev_id;
1714 DFX_board_t *bp; /* private board structure pointer */
1715 u8 tmp; /* used for disabling/enabling ints */
1717 /* Get board pointer only if device structure is valid */
1721 spin_lock(&bp->lock);
1723 /* See if we're already servicing an interrupt */
1725 /* Service adapter interrupts */
1727 if (bp->bus_type == DFX_BUS_TYPE_PCI)
1729 /* Disable PDQ-PFI interrupts at PFI */
1731 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, PFI_MODE_M_DMA_ENB);
1733 /* Call interrupt service routine for this adapter */
1735 dfx_int_common(dev);
1737 /* Clear PDQ interrupt status bit and reenable interrupts */
1739 dfx_port_write_long(bp, PFI_K_REG_STATUS, PFI_STATUS_M_PDQ_INT);
1740 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1741 (PFI_MODE_M_PDQ_INT_ENB + PFI_MODE_M_DMA_ENB));
1745 /* Disable interrupts at the ESIC */
1747 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &tmp);
1748 tmp &= ~PI_CONFIG_STAT_0_M_INT_ENB;
1749 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, tmp);
1751 /* Call interrupt service routine for this adapter */
1753 dfx_int_common(dev);
1755 /* Reenable interrupts at the ESIC */
1757 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &tmp);
1758 tmp |= PI_CONFIG_STAT_0_M_INT_ENB;
1759 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, tmp);
1762 spin_unlock(&bp->lock);
1767 * =====================
1768 * = dfx_ctl_get_stats =
1769 * =====================
1772 * Get statistics for FDDI adapter
1775 * Pointer to FDDI statistics structure
1778 * dev - pointer to device information
1780 * Functional Description:
1781 * Gets current MIB objects from adapter, then
1782 * returns FDDI statistics structure as defined
1785 * Note: Since the FDDI statistics structure is
1786 * still new and the device structure doesn't
1787 * have an FDDI-specific get statistics handler,
1788 * we'll return the FDDI statistics structure as
1789 * a pointer to an Ethernet statistics structure.
1790 * That way, at least the first part of the statistics
1791 * structure can be decoded properly, and it allows
1792 * "smart" applications to perform a second cast to
1793 * decode the FDDI-specific statistics.
1795 * We'll have to pay attention to this routine as the
1796 * device structure becomes more mature and LAN media
1809 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
1811 DFX_board_t *bp = dev->priv;
1813 /* Fill the bp->stats structure with driver-maintained counters */
1815 bp->stats.rx_packets = bp->rcv_total_frames;
1816 bp->stats.tx_packets = bp->xmt_total_frames;
1817 bp->stats.rx_bytes = bp->rcv_total_bytes;
1818 bp->stats.tx_bytes = bp->xmt_total_bytes;
1819 bp->stats.rx_errors = (u32)(bp->rcv_crc_errors + bp->rcv_frame_status_errors + bp->rcv_length_errors);
1820 bp->stats.tx_errors = bp->xmt_length_errors;
1821 bp->stats.rx_dropped = bp->rcv_discards;
1822 bp->stats.tx_dropped = bp->xmt_discards;
1823 bp->stats.multicast = bp->rcv_multicast_frames;
1824 bp->stats.transmit_collision = 0; /* always zero (0) for FDDI */
1826 /* Get FDDI SMT MIB objects */
1828 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
1829 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1830 return((struct net_device_stats *) &bp->stats);
1832 /* Fill the bp->stats structure with the SMT MIB object values */
1834 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1835 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
1836 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
1837 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
1838 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1839 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
1840 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
1841 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
1842 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
1843 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
1844 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
1845 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
1846 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
1847 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
1848 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
1849 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
1850 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
1851 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
1852 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
1853 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1854 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
1855 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
1856 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
1857 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1858 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1859 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
1860 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
1861 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
1862 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
1863 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1864 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1865 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1866 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1867 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
1868 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
1869 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
1870 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1871 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
1872 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
1873 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
1874 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
1875 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
1876 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
1877 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
1878 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
1879 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
1880 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
1881 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
1882 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
1883 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
1884 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
1885 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
1886 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
1887 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1888 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
1889 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
1890 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
1891 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
1892 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1893 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1894 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
1895 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
1896 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
1897 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
1898 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1899 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1900 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
1901 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
1902 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
1903 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
1904 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
1905 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
1906 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1907 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1908 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
1909 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
1910 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
1911 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
1912 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
1913 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
1914 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
1915 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
1916 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
1917 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
1918 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
1919 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
1920 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
1921 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
1922 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
1923 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
1924 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
1925 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
1927 /* Get FDDI counters */
1929 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
1930 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1931 return((struct net_device_stats *) &bp->stats);
1933 /* Fill the bp->stats structure with the FDDI counter values */
1935 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
1936 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
1937 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
1938 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
1939 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
1940 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
1941 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
1942 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
1943 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
1944 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
1945 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
1947 return((struct net_device_stats *) &bp->stats);
1952 * ==============================
1953 * = dfx_ctl_set_multicast_list =
1954 * ==============================
1957 * Enable/Disable LLC frame promiscuous mode reception
1958 * on the adapter and/or update multicast address table.
1964 * dev - pointer to device information
1966 * Functional Description:
1967 * This routine follows a fairly simple algorithm for setting the
1968 * adapter filters and CAM:
1970 * if IFF_PROMISC flag is set
1971 * enable LLC individual/group promiscuous mode
1973 * disable LLC individual/group promiscuous mode
1974 * if number of incoming multicast addresses >
1975 * (CAM max size - number of unicast addresses in CAM)
1976 * enable LLC group promiscuous mode
1977 * set driver-maintained multicast address count to zero
1979 * disable LLC group promiscuous mode
1980 * set driver-maintained multicast address count to incoming count
1981 * update adapter CAM
1982 * update adapter filters
1988 * Multicast addresses are presented in canonical (LSB) format.
1991 * On-board adapter CAM and filters are updated.
1994 static void dfx_ctl_set_multicast_list(struct net_device *dev)
1996 DFX_board_t *bp = dev->priv;
1997 int i; /* used as index in for loop */
1998 struct dev_mc_list *dmi; /* ptr to multicast addr entry */
2000 /* Enable LLC frame promiscuous mode, if necessary */
2002 if (dev->flags & IFF_PROMISC)
2003 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */
2005 /* Else, update multicast address table */
2009 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */
2011 * Check whether incoming multicast address count exceeds table size
2013 * Note: The adapters utilize an on-board 64 entry CAM for
2014 * supporting perfect filtering of multicast packets
2015 * and bridge functions when adding unicast addresses.
2016 * There is no hash function available. To support
2017 * additional multicast addresses, the all multicast
2018 * filter (LLC group promiscuous mode) must be enabled.
2020 * The firmware reserves two CAM entries for SMT-related
2021 * multicast addresses, which leaves 62 entries available.
2022 * The following code ensures that we're not being asked
2023 * to add more than 62 addresses to the CAM. If we are,
2024 * the driver will enable the all multicast filter.
2025 * Should the number of multicast addresses drop below
2026 * the high water mark, the filter will be disabled and
2027 * perfect filtering will be used.
2030 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
2032 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2033 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2037 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */
2038 bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */
2041 /* Copy addresses to multicast address table, then update adapter CAM */
2043 dmi = dev->mc_list; /* point to first multicast addr */
2044 for (i=0; i < bp->mc_count; i++)
2046 memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN);
2047 dmi = dmi->next; /* point to next multicast addr */
2049 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2051 DBG_printk("%s: Could not update multicast address table!\n", dev->name);
2055 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2059 /* Update adapter filters */
2061 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2063 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2067 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2073 * ===========================
2074 * = dfx_ctl_set_mac_address =
2075 * ===========================
2078 * Add node address override (unicast address) to adapter
2079 * CAM and update dev_addr field in device table.
2085 * dev - pointer to device information
2086 * addr - pointer to sockaddr structure containing unicast address to add
2088 * Functional Description:
2089 * The adapter supports node address overrides by adding one or more
2090 * unicast addresses to the adapter CAM. This is similar to adding
2091 * multicast addresses. In this routine we'll update the driver and
2092 * device structures with the new address, then update the adapter CAM
2093 * to ensure that the adapter will copy and strip frames destined and
2094 * sourced by that address.
2097 * Always returns zero.
2100 * The address pointed to by addr->sa_data is a valid unicast
2101 * address and is presented in canonical (LSB) format.
2104 * On-board adapter CAM is updated. On-board adapter filters
2108 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
2110 DFX_board_t *bp = dev->priv;
2111 struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
2113 /* Copy unicast address to driver-maintained structs and update count */
2115 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */
2116 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */
2120 * Verify we're not exceeding the CAM size by adding unicast address
2122 * Note: It's possible that before entering this routine we've
2123 * already filled the CAM with 62 multicast addresses.
2124 * Since we need to place the node address override into
2125 * the CAM, we have to check to see that we're not
2126 * exceeding the CAM size. If we are, we have to enable
2127 * the LLC group (multicast) promiscuous mode filter as
2128 * in dfx_ctl_set_multicast_list.
2131 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
2133 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2134 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2136 /* Update adapter filters */
2138 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2140 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2144 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2148 /* Update adapter CAM with new unicast address */
2150 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2152 DBG_printk("%s: Could not set new MAC address!\n", dev->name);
2156 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
2158 return(0); /* always return zero */
2163 * ======================
2164 * = dfx_ctl_update_cam =
2165 * ======================
2168 * Procedure to update adapter CAM (Content Addressable Memory)
2169 * with desired unicast and multicast address entries.
2175 * bp - pointer to board information
2177 * Functional Description:
2178 * Updates adapter CAM with current contents of board structure
2179 * unicast and multicast address tables. Since there are only 62
2180 * free entries in CAM, this routine ensures that the command
2181 * request buffer is not overrun.
2184 * DFX_K_SUCCESS - Request succeeded
2185 * DFX_K_FAILURE - Request failed
2188 * All addresses being added (unicast and multicast) are in canonical
2192 * On-board adapter CAM is updated.
2195 static int dfx_ctl_update_cam(DFX_board_t *bp)
2197 int i; /* used as index */
2198 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */
2201 * Fill in command request information
2203 * Note: Even though both the unicast and multicast address
2204 * table entries are stored as contiguous 6 byte entries,
2205 * the firmware address filter set command expects each
2206 * entry to be two longwords (8 bytes total). We must be
2207 * careful to only copy the six bytes of each unicast and
2208 * multicast table entry into each command entry. This
2209 * is also why we must first clear the entire command
2213 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */
2214 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
2215 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
2217 /* Now add unicast addresses to command request buffer, if any */
2219 for (i=0; i < (int)bp->uc_count; i++)
2221 if (i < PI_CMD_ADDR_FILTER_K_SIZE)
2223 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2224 p_addr++; /* point to next command entry */
2228 /* Now add multicast addresses to command request buffer, if any */
2230 for (i=0; i < (int)bp->mc_count; i++)
2232 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
2234 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2235 p_addr++; /* point to next command entry */
2239 /* Issue command to update adapter CAM, then return */
2241 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2242 return(DFX_K_FAILURE);
2243 return(DFX_K_SUCCESS);
2248 * ==========================
2249 * = dfx_ctl_update_filters =
2250 * ==========================
2253 * Procedure to update adapter filters with desired
2260 * bp - pointer to board information
2262 * Functional Description:
2263 * Enables or disables filter using current filter settings.
2266 * DFX_K_SUCCESS - Request succeeded.
2267 * DFX_K_FAILURE - Request failed.
2270 * We must always pass up packets destined to the broadcast
2271 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2272 * broadcast filter enabled.
2275 * On-board adapter filters are updated.
2278 static int dfx_ctl_update_filters(DFX_board_t *bp)
2280 int i = 0; /* used as index */
2282 /* Fill in command request information */
2284 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
2286 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2288 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST;
2289 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS;
2291 /* Initialize LLC Individual/Group Promiscuous filter */
2293 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM;
2294 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom;
2296 /* Initialize LLC Group Promiscuous filter */
2298 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM;
2299 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom;
2301 /* Terminate the item code list */
2303 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL;
2305 /* Issue command to update adapter filters, then return */
2307 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2308 return(DFX_K_FAILURE);
2309 return(DFX_K_SUCCESS);
2314 * ======================
2315 * = dfx_hw_dma_cmd_req =
2316 * ======================
2319 * Sends PDQ DMA command to adapter firmware
2325 * bp - pointer to board information
2327 * Functional Description:
2328 * The command request and response buffers are posted to the adapter in the manner
2329 * described in the PDQ Port Specification:
2331 * 1. Command Response Buffer is posted to adapter.
2332 * 2. Command Request Buffer is posted to adapter.
2333 * 3. Command Request consumer index is polled until it indicates that request
2334 * buffer has been DMA'd to adapter.
2335 * 4. Command Response consumer index is polled until it indicates that response
2336 * buffer has been DMA'd from adapter.
2338 * This ordering ensures that a response buffer is already available for the firmware
2339 * to use once it's done processing the request buffer.
2342 * DFX_K_SUCCESS - DMA command succeeded
2343 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2344 * DFX_K_HW_TIMEOUT - DMA command timed out
2347 * Command request buffer has already been filled with desired DMA command.
2353 static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
2355 int status; /* adapter status */
2356 int timeout_cnt; /* used in for loops */
2358 /* Make sure the adapter is in a state that we can issue the DMA command in */
2360 status = dfx_hw_adap_state_rd(bp);
2361 if ((status == PI_STATE_K_RESET) ||
2362 (status == PI_STATE_K_HALTED) ||
2363 (status == PI_STATE_K_DMA_UNAVAIL) ||
2364 (status == PI_STATE_K_UPGRADE))
2365 return(DFX_K_OUTSTATE);
2367 /* Put response buffer on the command response queue */
2369 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2370 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2371 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
2373 /* Bump (and wrap) the producer index and write out to register */
2375 bp->cmd_rsp_reg.index.prod += 1;
2376 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2377 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2379 /* Put request buffer on the command request queue */
2381 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
2382 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
2383 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
2385 /* Bump (and wrap) the producer index and write out to register */
2387 bp->cmd_req_reg.index.prod += 1;
2388 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2389 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2392 * Here we wait for the command request consumer index to be equal
2393 * to the producer, indicating that the adapter has DMAed the request.
2396 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2398 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
2400 udelay(100); /* wait for 100 microseconds */
2402 if (timeout_cnt == 0)
2403 return(DFX_K_HW_TIMEOUT);
2405 /* Bump (and wrap) the completion index and write out to register */
2407 bp->cmd_req_reg.index.comp += 1;
2408 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2409 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2412 * Here we wait for the command response consumer index to be equal
2413 * to the producer, indicating that the adapter has DMAed the response.
2416 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2418 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
2420 udelay(100); /* wait for 100 microseconds */
2422 if (timeout_cnt == 0)
2423 return(DFX_K_HW_TIMEOUT);
2425 /* Bump (and wrap) the completion index and write out to register */
2427 bp->cmd_rsp_reg.index.comp += 1;
2428 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2429 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2430 return(DFX_K_SUCCESS);
2435 * ========================
2436 * = dfx_hw_port_ctrl_req =
2437 * ========================
2440 * Sends PDQ port control command to adapter firmware
2443 * Host data register value in host_data if ptr is not NULL
2446 * bp - pointer to board information
2447 * command - port control command
2448 * data_a - port data A register value
2449 * data_b - port data B register value
2450 * host_data - ptr to host data register value
2452 * Functional Description:
2453 * Send generic port control command to adapter by writing
2454 * to various PDQ port registers, then polling for completion.
2457 * DFX_K_SUCCESS - port control command succeeded
2458 * DFX_K_HW_TIMEOUT - port control command timed out
2467 static int dfx_hw_port_ctrl_req(
2472 PI_UINT32 *host_data
2476 PI_UINT32 port_cmd; /* Port Control command register value */
2477 int timeout_cnt; /* used in for loops */
2479 /* Set Command Error bit in command longword */
2481 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
2483 /* Issue port command to the adapter */
2485 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
2486 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
2487 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
2489 /* Now wait for command to complete */
2491 if (command == PI_PCTRL_M_BLAST_FLASH)
2492 timeout_cnt = 600000; /* set command timeout count to 60 seconds */
2494 timeout_cnt = 20000; /* set command timeout count to 2 seconds */
2496 for (; timeout_cnt > 0; timeout_cnt--)
2498 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
2499 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
2501 udelay(100); /* wait for 100 microseconds */
2503 if (timeout_cnt == 0)
2504 return(DFX_K_HW_TIMEOUT);
2507 * If the address of host_data is non-zero, assume caller has supplied a
2508 * non NULL pointer, and return the contents of the HOST_DATA register in
2512 if (host_data != NULL)
2513 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
2514 return(DFX_K_SUCCESS);
2519 * =====================
2520 * = dfx_hw_adap_reset =
2521 * =====================
2530 * bp - pointer to board information
2531 * type - type of reset to perform
2533 * Functional Description:
2534 * Issue soft reset to adapter by writing to PDQ Port Reset
2535 * register. Use incoming reset type to tell adapter what
2536 * kind of reset operation to perform.
2542 * This routine merely issues a soft reset to the adapter.
2543 * It is expected that after this routine returns, the caller
2544 * will appropriately poll the Port Status register for the
2545 * adapter to enter the proper state.
2548 * Internal adapter registers are cleared.
2551 static void dfx_hw_adap_reset(
2557 /* Set Reset type and assert reset */
2559 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */
2560 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
2562 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2566 /* Deassert reset */
2568 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
2573 * ========================
2574 * = dfx_hw_adap_state_rd =
2575 * ========================
2578 * Returns current adapter state
2581 * Adapter state per PDQ Port Specification
2584 * bp - pointer to board information
2586 * Functional Description:
2587 * Reads PDQ Port Status register and returns adapter state.
2599 static int dfx_hw_adap_state_rd(DFX_board_t *bp)
2601 PI_UINT32 port_status; /* Port Status register value */
2603 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
2604 return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE);
2609 * =====================
2610 * = dfx_hw_dma_uninit =
2611 * =====================
2614 * Brings adapter to DMA_UNAVAILABLE state
2620 * bp - pointer to board information
2621 * type - type of reset to perform
2623 * Functional Description:
2624 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2625 * 1. Set reset type bit in Port Data A Register then reset adapter.
2626 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2629 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2630 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2636 * Internal adapter registers are cleared.
2639 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
2641 int timeout_cnt; /* used in for loops */
2643 /* Set reset type bit and reset adapter */
2645 dfx_hw_adap_reset(bp, type);
2647 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2649 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
2651 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
2653 udelay(100); /* wait for 100 microseconds */
2655 if (timeout_cnt == 0)
2656 return(DFX_K_HW_TIMEOUT);
2657 return(DFX_K_SUCCESS);
2661 * Align an sk_buff to a boundary power of 2
2665 static void my_skb_align(struct sk_buff *skb, int n)
2667 unsigned long x=(unsigned long)skb->data;
2670 v=(x+n-1)&~(n-1); /* Where we want to be */
2672 skb_reserve(skb, v-x);
2682 * Produces buffers to adapter LLC Host receive descriptor block
2688 * bp - pointer to board information
2689 * get_buffers - non-zero if buffers to be allocated
2691 * Functional Description:
2692 * This routine can be called during dfx_adap_init() or during an adapter
2693 * reset. It initializes the descriptor block and produces all allocated
2694 * LLC Host queue receive buffers.
2697 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2698 * dynamic buffer allocation). If the buffer allocation failed, the
2699 * already allocated buffers will not be released and the caller should do
2703 * The PDQ has been reset and the adapter and driver maintained Type 2
2704 * register indices are cleared.
2707 * Receive buffers are posted to the adapter LLC queue and the adapter
2711 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
2713 int i, j; /* used in for loop */
2716 * Since each receive buffer is a single fragment of same length, initialize
2717 * first longword in each receive descriptor for entire LLC Host descriptor
2718 * block. Also initialize second longword in each receive descriptor with
2719 * physical address of receive buffer. We'll always allocate receive
2720 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2721 * block and produce new receive buffers by simply updating the receive
2725 * To support all shipping versions of PDQ, the receive buffer size
2726 * must be mod 128 in length and the physical address must be 128 byte
2727 * aligned. In other words, bits 0-6 of the length and address must
2728 * be zero for the following descriptor field entries to be correct on
2729 * all PDQ-based boards. We guaranteed both requirements during
2730 * driver initialization when we allocated memory for the receive buffers.
2734 #ifdef DYNAMIC_BUFFERS
2735 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
2736 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2738 struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO);
2741 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2742 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2744 * align to 128 bytes for compatibility with
2745 * the old EISA boards.
2748 my_skb_align(newskb, 128);
2749 bp->descr_block_virt->rcv_data[i + j].long_1 =
2750 (u32)pci_map_single(bp->pci_dev, newskb->data,
2752 PCI_DMA_FROMDEVICE);
2754 * p_rcv_buff_va is only used inside the
2755 * kernel so we put the skb pointer here.
2757 bp->p_rcv_buff_va[i+j] = (char *) newskb;
2760 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
2761 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2763 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2764 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2765 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2766 bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
2771 /* Update receive producer and Type 2 register */
2773 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
2774 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
2780 * =========================
2781 * = dfx_rcv_queue_process =
2782 * =========================
2785 * Process received LLC frames.
2791 * bp - pointer to board information
2793 * Functional Description:
2794 * Received LLC frames are processed until there are no more consumed frames.
2795 * Once all frames are processed, the receive buffers are returned to the
2796 * adapter. Note that this algorithm fixes the length of time that can be spent
2797 * in this routine, because there are a fixed number of receive buffers to
2798 * process and buffers are not produced until this routine exits and returns
2811 static void dfx_rcv_queue_process(
2816 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
2817 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */
2818 u32 descr, pkt_len; /* FMC descriptor field and packet length */
2819 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */
2821 /* Service all consumed LLC receive frames */
2823 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
2824 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
2826 /* Process any errors */
2830 entry = bp->rcv_xmt_reg.index.rcv_comp;
2831 #ifdef DYNAMIC_BUFFERS
2832 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
2834 p_buff = (char *) bp->p_rcv_buff_va[entry];
2836 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
2838 if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
2840 if (descr & PI_FMC_DESCR_M_RCC_CRC)
2841 bp->rcv_crc_errors++;
2843 bp->rcv_frame_status_errors++;
2847 int rx_in_place = 0;
2849 /* The frame was received without errors - verify packet length */
2851 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
2852 pkt_len -= 4; /* subtract 4 byte CRC */
2853 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
2854 bp->rcv_length_errors++;
2856 #ifdef DYNAMIC_BUFFERS
2857 if (pkt_len > SKBUFF_RX_COPYBREAK) {
2858 struct sk_buff *newskb;
2860 newskb = dev_alloc_skb(NEW_SKB_SIZE);
2864 my_skb_align(newskb, 128);
2865 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
2866 pci_unmap_single(bp->pci_dev,
2867 bp->descr_block_virt->rcv_data[entry].long_1,
2869 PCI_DMA_FROMDEVICE);
2870 skb_reserve(skb, RCV_BUFF_K_PADDING);
2871 bp->p_rcv_buff_va[entry] = (char *)newskb;
2872 bp->descr_block_virt->rcv_data[entry].long_1 =
2873 (u32)pci_map_single(bp->pci_dev,
2876 PCI_DMA_FROMDEVICE);
2881 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */
2884 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name);
2889 #ifndef DYNAMIC_BUFFERS
2893 /* Receive buffer allocated, pass receive packet up */
2895 memcpy(skb->data, p_buff + RCV_BUFF_K_PADDING, pkt_len+3);
2898 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */
2899 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */
2900 skb->dev = bp->dev; /* pass up device pointer */
2902 skb->protocol = fddi_type_trans(skb, bp->dev);
2903 bp->rcv_total_bytes += skb->len;
2906 /* Update the rcv counters */
2907 bp->dev->last_rx = jiffies;
2908 bp->rcv_total_frames++;
2909 if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
2910 bp->rcv_multicast_frames++;
2916 * Advance the producer (for recycling) and advance the completion
2917 * (for servicing received frames). Note that it is okay to
2918 * advance the producer without checking that it passes the
2919 * completion index because they are both advanced at the same
2923 bp->rcv_xmt_reg.index.rcv_prod += 1;
2924 bp->rcv_xmt_reg.index.rcv_comp += 1;
2930 * =====================
2931 * = dfx_xmt_queue_pkt =
2932 * =====================
2935 * Queues packets for transmission
2941 * skb - pointer to sk_buff to queue for transmission
2942 * dev - pointer to device information
2944 * Functional Description:
2945 * Here we assume that an incoming skb transmit request
2946 * is contained in a single physically contiguous buffer
2947 * in which the virtual address of the start of packet
2948 * (skb->data) can be converted to a physical address
2949 * by using pci_map_single().
2951 * Since the adapter architecture requires a three byte
2952 * packet request header to prepend the start of packet,
2953 * we'll write the three byte field immediately prior to
2954 * the FC byte. This assumption is valid because we've
2955 * ensured that dev->hard_header_len includes three pad
2956 * bytes. By posting a single fragment to the adapter,
2957 * we'll reduce the number of descriptor fetches and
2958 * bus traffic needed to send the request.
2960 * Also, we can't free the skb until after it's been DMA'd
2961 * out by the adapter, so we'll queue it in the driver and
2962 * return it in dfx_xmt_done.
2965 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2966 * 1 - caller should requeue the sk_buff for later transmission
2969 * First and foremost, we assume the incoming skb pointer
2970 * is NOT NULL and is pointing to a valid sk_buff structure.
2972 * The outgoing packet is complete, starting with the
2973 * frame control byte including the last byte of data,
2974 * but NOT including the 4 byte CRC. We'll let the
2975 * adapter hardware generate and append the CRC.
2977 * The entire packet is stored in one physically
2978 * contiguous buffer which is not cached and whose
2979 * 32-bit physical address can be determined.
2981 * It's vital that this routine is NOT reentered for the
2982 * same board and that the OS is not in another section of
2983 * code (eg. dfx_int_common) for the same board on a
2990 static int dfx_xmt_queue_pkt(
2991 struct sk_buff *skb,
2992 struct net_device *dev
2996 DFX_board_t *bp = dev->priv;
2997 u8 prod; /* local transmit producer index */
2998 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */
2999 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3000 unsigned long flags;
3002 netif_stop_queue(dev);
3005 * Verify that incoming transmit request is OK
3007 * Note: The packet size check is consistent with other
3008 * Linux device drivers, although the correct packet
3009 * size should be verified before calling the
3013 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3015 printk("%s: Invalid packet length - %u bytes\n",
3016 dev->name, skb->len);
3017 bp->xmt_length_errors++; /* bump error counter */
3018 netif_wake_queue(dev);
3020 return(0); /* return "success" */
3023 * See if adapter link is available, if not, free buffer
3025 * Note: If the link isn't available, free buffer and return 0
3026 * rather than tell the upper layer to requeue the packet.
3027 * The methodology here is that by the time the link
3028 * becomes available, the packet to be sent will be
3029 * fairly stale. By simply dropping the packet, the
3030 * higher layer protocols will eventually time out
3031 * waiting for response packets which it won't receive.
3034 if (bp->link_available == PI_K_FALSE)
3036 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */
3037 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */
3040 bp->xmt_discards++; /* bump error counter */
3041 dev_kfree_skb(skb); /* free sk_buff now */
3042 netif_wake_queue(dev);
3043 return(0); /* return "success" */
3047 spin_lock_irqsave(&bp->lock, flags);
3049 /* Get the current producer and the next free xmt data descriptor */
3051 prod = bp->rcv_xmt_reg.index.xmt_prod;
3052 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
3055 * Get pointer to auxiliary queue entry to contain information
3058 * Note: The current xmt producer index will become the
3059 * current xmt completion index when we complete this
3060 * packet later on. So, we'll get the pointer to the
3061 * next auxiliary queue entry now before we bump the
3065 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */
3067 /* Write the three PRH bytes immediately before the FC byte */
3070 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */
3071 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */
3072 skb->data[2] = DFX_PRH2_BYTE; /* specification */
3075 * Write the descriptor with buffer info and bump producer
3077 * Note: Since we need to start DMA from the packet request
3078 * header, we'll add 3 bytes to the DMA buffer length,
3079 * and we'll determine the physical address of the
3080 * buffer from the PRH, not skb->data.
3083 * 1. Packet starts with the frame control (FC) byte
3085 * 2. The 4-byte CRC is not appended to the buffer or
3086 * included in the length.
3087 * 3. Packet length (skb->len) is from FC to end of
3089 * 4. The packet length does not exceed the maximum
3090 * FDDI LLC frame length of 4491 bytes.
3091 * 5. The entire packet is contained in a physically
3092 * contiguous, non-cached, locked memory space
3093 * comprised of a single buffer pointed to by
3095 * 6. The physical address of the start of packet
3096 * can be determined from the virtual address
3097 * by using pci_map_single() and is only 32-bits
3101 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3102 p_xmt_descr->long_1 = (u32)pci_map_single(bp->pci_dev, skb->data,
3103 skb->len, PCI_DMA_TODEVICE);
3106 * Verify that descriptor is actually available
3108 * Note: If descriptor isn't available, return 1 which tells
3109 * the upper layer to requeue the packet for later
3112 * We need to ensure that the producer never reaches the
3113 * completion, except to indicate that the queue is empty.
3116 if (prod == bp->rcv_xmt_reg.index.xmt_comp)
3119 spin_unlock_irqrestore(&bp->lock, flags);
3120 return(1); /* requeue packet for later */
3124 * Save info for this packet for xmt done indication routine
3126 * Normally, we'd save the producer index in the p_xmt_drv_descr
3127 * structure so that we'd have it handy when we complete this
3128 * packet later (in dfx_xmt_done). However, since the current
3129 * transmit architecture guarantees a single fragment for the
3130 * entire packet, we can simply bump the completion index by
3131 * one (1) for each completed packet.
3133 * Note: If this assumption changes and we're presented with
3134 * an inconsistent number of transmit fragments for packet
3135 * data, we'll need to modify this code to save the current
3136 * transmit producer index.
3139 p_xmt_drv_descr->p_skb = skb;
3141 /* Update Type 2 register */
3143 bp->rcv_xmt_reg.index.xmt_prod = prod;
3144 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
3145 spin_unlock_irqrestore(&bp->lock, flags);
3146 netif_wake_queue(dev);
3147 return(0); /* packet queued to adapter */
3157 * Processes all frames that have been transmitted.
3163 * bp - pointer to board information
3165 * Functional Description:
3166 * For all consumed transmit descriptors that have not
3167 * yet been completed, we'll free the skb we were holding
3168 * onto using dev_kfree_skb and bump the appropriate
3175 * The Type 2 register is not updated in this routine. It is
3176 * assumed that it will be updated in the ISR when dfx_xmt_done
3183 static int dfx_xmt_done(DFX_board_t *bp)
3185 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3186 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
3187 u8 comp; /* local transmit completion index */
3188 int freed = 0; /* buffers freed */
3190 /* Service all consumed transmit frames */
3192 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3193 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
3195 /* Get pointer to the transmit driver descriptor block information */
3197 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3199 /* Increment transmit counters */
3201 bp->xmt_total_frames++;
3202 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
3204 /* Return skb to operating system */
3205 comp = bp->rcv_xmt_reg.index.xmt_comp;
3206 pci_unmap_single(bp->pci_dev,
3207 bp->descr_block_virt->xmt_data[comp].long_1,
3208 p_xmt_drv_descr->p_skb->len,
3210 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb);
3213 * Move to start of next packet by updating completion index
3215 * Here we assume that a transmit packet request is always
3216 * serviced by posting one fragment. We can therefore
3217 * simplify the completion code by incrementing the
3218 * completion index by one. This code will need to be
3219 * modified if this assumption changes. See comments
3220 * in dfx_xmt_queue_pkt for more details.
3223 bp->rcv_xmt_reg.index.xmt_comp += 1;
3236 * Remove all skb's in the receive ring.
3242 * bp - pointer to board information
3244 * Functional Description:
3245 * Free's all the dynamically allocated skb's that are
3246 * currently attached to the device receive ring. This
3247 * function is typically only used when the device is
3248 * initialized or reinitialized.
3256 #ifdef DYNAMIC_BUFFERS
3257 static void dfx_rcv_flush( DFX_board_t *bp )
3261 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
3262 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
3264 struct sk_buff *skb;
3265 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
3268 bp->p_rcv_buff_va[i+j] = NULL;
3273 static inline void dfx_rcv_flush( DFX_board_t *bp )
3276 #endif /* DYNAMIC_BUFFERS */
3284 * Processes all frames whether they've been transmitted
3291 * bp - pointer to board information
3293 * Functional Description:
3294 * For all produced transmit descriptors that have not
3295 * yet been completed, we'll free the skb we were holding
3296 * onto using dev_kfree_skb and bump the appropriate
3297 * counters. Of course, it's possible that some of
3298 * these transmit requests actually did go out, but we
3299 * won't make that distinction here. Finally, we'll
3300 * update the consumer index to match the producer.
3306 * This routine does NOT update the Type 2 register. It
3307 * is assumed that this routine is being called during a
3308 * transmit flush interrupt, or a shutdown or close routine.
3314 static void dfx_xmt_flush( DFX_board_t *bp )
3316 u32 prod_cons; /* rcv/xmt consumer block longword */
3317 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3318 u8 comp; /* local transmit completion index */
3320 /* Flush all outstanding transmit frames */
3322 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
3324 /* Get pointer to the transmit driver descriptor block information */
3326 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3328 /* Return skb to operating system */
3329 comp = bp->rcv_xmt_reg.index.xmt_comp;
3330 pci_unmap_single(bp->pci_dev,
3331 bp->descr_block_virt->xmt_data[comp].long_1,
3332 p_xmt_drv_descr->p_skb->len,
3334 dev_kfree_skb(p_xmt_drv_descr->p_skb);
3336 /* Increment transmit error counter */
3341 * Move to start of next packet by updating completion index
3343 * Here we assume that a transmit packet request is always
3344 * serviced by posting one fragment. We can therefore
3345 * simplify the completion code by incrementing the
3346 * completion index by one. This code will need to be
3347 * modified if this assumption changes. See comments
3348 * in dfx_xmt_queue_pkt for more details.
3351 bp->rcv_xmt_reg.index.xmt_comp += 1;
3354 /* Update the transmit consumer index in the consumer block */
3356 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
3357 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
3358 bp->cons_block_virt->xmt_rcv_data = prod_cons;
3361 static void __devexit dfx_remove_one_pci_or_eisa(struct pci_dev *pdev, struct net_device *dev)
3363 DFX_board_t *bp = dev->priv;
3364 int alloc_size; /* total buffer size used */
3366 unregister_netdev(dev);
3367 release_region(dev->base_addr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN );
3369 alloc_size = sizeof(PI_DESCR_BLOCK) +
3370 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
3371 #ifndef DYNAMIC_BUFFERS
3372 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
3374 sizeof(PI_CONSUMER_BLOCK) +
3375 (PI_ALIGN_K_DESC_BLK - 1);
3377 pci_free_consistent(pdev, alloc_size, bp->kmalloced,
3382 static void __devexit dfx_remove_one (struct pci_dev *pdev)
3384 struct net_device *dev = pci_get_drvdata(pdev);
3386 dfx_remove_one_pci_or_eisa(pdev, dev);
3387 pci_set_drvdata(pdev, NULL);
3390 static struct pci_device_id dfx_pci_tbl[] = {
3391 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, PCI_ANY_ID, PCI_ANY_ID, },
3394 MODULE_DEVICE_TABLE(pci, dfx_pci_tbl);
3396 static struct pci_driver dfx_driver = {
3398 .probe = dfx_init_one,
3399 .remove = __devexit_p(dfx_remove_one),
3400 .id_table = dfx_pci_tbl,
3403 static int dfx_have_pci;
3404 static int dfx_have_eisa;
3407 static void __exit dfx_eisa_cleanup(void)
3409 struct net_device *dev = root_dfx_eisa_dev;
3413 struct net_device *tmp;
3416 bp = (DFX_board_t*)dev->priv;
3418 dfx_remove_one_pci_or_eisa(NULL, dev);
3423 static int __init dfx_init(void)
3425 int rc_pci, rc_eisa;
3427 /* when a module, this is printed whether or not devices are found in probe */
3432 rc_pci = pci_module_init(&dfx_driver);
3433 if (rc_pci >= 0) dfx_have_pci = 1;
3435 rc_eisa = dfx_eisa_init();
3436 if (rc_eisa >= 0) dfx_have_eisa = 1;
3438 return ((rc_eisa < 0) ? 0 : rc_eisa) + ((rc_pci < 0) ? 0 : rc_pci);
3441 static void __exit dfx_cleanup(void)
3444 pci_unregister_driver(&dfx_driver);
3450 module_init(dfx_init);
3451 module_exit(dfx_cleanup);
3452 MODULE_LICENSE("GPL");
3457 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"