1 /*******************************************************************************
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * e100.c: Intel(R) PRO/100 ethernet driver
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
55 * II. Driver Operation
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
129 * Thanks to JC (jchapman@katalix.com) for helping with
130 * testing/troubleshooting the development driver.
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
137 #include <linux/config.h>
138 #include <linux/module.h>
139 #include <linux/moduleparam.h>
140 #include <linux/kernel.h>
141 #include <linux/types.h>
142 #include <linux/slab.h>
143 #include <linux/delay.h>
144 #include <linux/init.h>
145 #include <linux/pci.h>
146 #include <linux/netdevice.h>
147 #include <linux/etherdevice.h>
148 #include <linux/mii.h>
149 #include <linux/if_vlan.h>
150 #include <linux/skbuff.h>
151 #include <linux/ethtool.h>
152 #include <linux/string.h>
153 #include <asm/unaligned.h>
156 #define DRV_NAME "e100"
157 #define DRV_EXT "-NAPI"
158 #define DRV_VERSION "3.2.3-k2"DRV_EXT
159 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
160 #define DRV_COPYRIGHT "Copyright(c) 1999-2004 Intel Corporation"
161 #define PFX DRV_NAME ": "
163 #define E100_WATCHDOG_PERIOD (2 * HZ)
164 #define E100_NAPI_WEIGHT 16
166 MODULE_DESCRIPTION(DRV_DESCRIPTION);
167 MODULE_AUTHOR(DRV_COPYRIGHT);
168 MODULE_LICENSE("GPL");
170 static int debug = 3;
171 module_param(debug, int, 0);
172 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
173 #define DPRINTK(nlevel, klevel, fmt, args...) \
174 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
175 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
176 __FUNCTION__ , ## args))
178 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
179 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
180 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
181 static struct pci_device_id e100_id_table[] = {
182 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
183 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
184 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
185 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
186 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
190 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
191 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
196 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
197 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
204 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
205 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
206 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
215 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
216 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
219 MODULE_DEVICE_TABLE(pci, e100_id_table);
222 mac_82557_D100_A = 0,
223 mac_82557_D100_B = 1,
224 mac_82557_D100_C = 2,
225 mac_82558_D101_A4 = 4,
226 mac_82558_D101_B0 = 5,
230 mac_82550_D102_C = 13,
238 phy_100a = 0x000003E0,
239 phy_100c = 0x035002A8,
240 phy_82555_tx = 0x015002A8,
241 phy_nsc_tx = 0x5C002000,
242 phy_82562_et = 0x033002A8,
243 phy_82562_em = 0x032002A8,
244 phy_82562_ek = 0x031002A8,
245 phy_82562_eh = 0x017002A8,
246 phy_unknown = 0xFFFFFFFF,
249 /* CSR (Control/Status Registers) */
272 stat_ack_not_ours = 0x00,
273 stat_ack_sw_gen = 0x04,
275 stat_ack_cu_idle = 0x20,
276 stat_ack_frame_rx = 0x40,
277 stat_ack_cu_cmd_done = 0x80,
278 stat_ack_not_present = 0xFF,
279 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
280 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
284 irq_mask_none = 0x00,
292 ruc_load_base = 0x06,
295 cuc_dump_addr = 0x40,
296 cuc_dump_stats = 0x50,
297 cuc_load_base = 0x60,
298 cuc_dump_reset = 0x70,
302 cuc_dump_complete = 0x0000A005,
303 cuc_dump_reset_complete = 0x0000A007,
307 software_reset = 0x0000,
309 selective_reset = 0x0002,
312 enum eeprom_ctrl_lo {
320 mdi_write = 0x04000000,
321 mdi_read = 0x08000000,
322 mdi_ready = 0x10000000,
332 enum eeprom_offsets {
333 eeprom_cnfg_mdix = 0x03,
335 eeprom_config_asf = 0x0D,
336 eeprom_smbus_addr = 0x90,
339 enum eeprom_cnfg_mdix {
340 eeprom_mdix_enabled = 0x0080,
344 eeprom_id_wol = 0x0020,
347 enum eeprom_config_asf {
353 cb_complete = 0x8000,
382 struct rx *next, *prev;
387 #if defined(__BIG_ENDIAN_BITFIELD)
393 /*0*/ u8 X(byte_count:6, pad0:2);
394 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
395 /*2*/ u8 adaptive_ifs;
396 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
397 term_write_cache_line:1), pad3:4);
398 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
399 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
400 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
401 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
402 rx_discard_overruns:1), rx_save_bad_frames:1);
403 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
404 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
406 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
407 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
408 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
409 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
411 /*11*/ u8 X(linear_priority:3, pad11:5);
412 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
413 /*13*/ u8 ip_addr_lo;
414 /*14*/ u8 ip_addr_hi;
415 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
416 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
417 pad15_2:1), crs_or_cdt:1);
418 /*16*/ u8 fc_delay_lo;
419 /*17*/ u8 fc_delay_hi;
420 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
421 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
422 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
423 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
424 full_duplex_force:1), full_duplex_pin:1);
425 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
426 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
427 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
431 #define E100_MAX_MULTICAST_ADDRS 64
434 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
437 /* Important: keep total struct u32-aligned */
438 #define UCODE_SIZE 134
445 u32 ucode[UCODE_SIZE];
446 struct config config;
459 u32 dump_buffer_addr;
461 struct cb *next, *prev;
467 lb_none = 0, lb_mac = 1, lb_phy = 3,
471 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
472 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
473 tx_multiple_collisions, tx_total_collisions;
474 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
475 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
476 rx_short_frame_errors;
477 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
478 u16 xmt_tco_frames, rcv_tco_frames;
498 struct param_range rfds;
499 struct param_range cbs;
503 /* Begin: frequently used values: keep adjacent for cache effect */
504 u32 msg_enable ____cacheline_aligned;
505 struct net_device *netdev;
506 struct pci_dev *pdev;
508 struct rx *rxs ____cacheline_aligned;
509 struct rx *rx_to_use;
510 struct rx *rx_to_clean;
511 struct rfd blank_rfd;
514 spinlock_t cb_lock ____cacheline_aligned;
516 struct csr __iomem *csr;
517 enum scb_cmd_lo cuc_cmd;
518 unsigned int cbs_avail;
520 struct cb *cb_to_use;
521 struct cb *cb_to_send;
522 struct cb *cb_to_clean;
524 /* End: frequently used values: keep adjacent for cache effect */
528 promiscuous = (1 << 1),
529 multicast_all = (1 << 2),
530 wol_magic = (1 << 3),
531 ich_10h_workaround = (1 << 4),
532 } flags ____cacheline_aligned;
536 struct params params;
537 struct net_device_stats net_stats;
538 struct timer_list watchdog;
539 struct timer_list blink_timer;
540 struct mii_if_info mii;
541 enum loopback loopback;
546 dma_addr_t cbs_dma_addr;
552 u32 tx_single_collisions;
553 u32 tx_multiple_collisions;
558 u32 rx_fc_unsupported;
560 u32 rx_over_length_errors;
568 static inline void e100_write_flush(struct nic *nic)
570 /* Flush previous PCI writes through intermediate bridges
571 * by doing a benign read */
572 (void)readb(&nic->csr->scb.status);
575 static inline void e100_enable_irq(struct nic *nic)
579 spin_lock_irqsave(&nic->cmd_lock, flags);
580 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
581 spin_unlock_irqrestore(&nic->cmd_lock, flags);
582 e100_write_flush(nic);
585 static inline void e100_disable_irq(struct nic *nic)
589 spin_lock_irqsave(&nic->cmd_lock, flags);
590 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
591 spin_unlock_irqrestore(&nic->cmd_lock, flags);
592 e100_write_flush(nic);
595 static void e100_hw_reset(struct nic *nic)
597 /* Put CU and RU into idle with a selective reset to get
598 * device off of PCI bus */
599 writel(selective_reset, &nic->csr->port);
600 e100_write_flush(nic); udelay(20);
602 /* Now fully reset device */
603 writel(software_reset, &nic->csr->port);
604 e100_write_flush(nic); udelay(20);
606 /* Mask off our interrupt line - it's unmasked after reset */
607 e100_disable_irq(nic);
610 static int e100_self_test(struct nic *nic)
612 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
614 /* Passing the self-test is a pretty good indication
615 * that the device can DMA to/from host memory */
617 nic->mem->selftest.signature = 0;
618 nic->mem->selftest.result = 0xFFFFFFFF;
620 writel(selftest | dma_addr, &nic->csr->port);
621 e100_write_flush(nic);
622 /* Wait 10 msec for self-test to complete */
623 set_current_state(TASK_UNINTERRUPTIBLE);
624 schedule_timeout(HZ / 100 + 1);
626 /* Interrupts are enabled after self-test */
627 e100_disable_irq(nic);
629 /* Check results of self-test */
630 if(nic->mem->selftest.result != 0) {
631 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
632 nic->mem->selftest.result);
635 if(nic->mem->selftest.signature == 0) {
636 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
643 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
645 u32 cmd_addr_data[3];
649 /* Three cmds: write/erase enable, write data, write/erase disable */
650 cmd_addr_data[0] = op_ewen << (addr_len - 2);
651 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
653 cmd_addr_data[2] = op_ewds << (addr_len - 2);
655 /* Bit-bang cmds to write word to eeprom */
656 for(j = 0; j < 3; j++) {
659 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
660 e100_write_flush(nic); udelay(4);
662 for(i = 31; i >= 0; i--) {
663 ctrl = (cmd_addr_data[j] & (1 << i)) ?
665 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
666 e100_write_flush(nic); udelay(4);
668 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
669 e100_write_flush(nic); udelay(4);
671 /* Wait 10 msec for cmd to complete */
672 set_current_state(TASK_UNINTERRUPTIBLE);
673 schedule_timeout(HZ / 100 + 1);
676 writeb(0, &nic->csr->eeprom_ctrl_lo);
677 e100_write_flush(nic); udelay(4);
681 /* General technique stolen from the eepro100 driver - very clever */
682 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
689 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
692 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
693 e100_write_flush(nic); udelay(4);
695 /* Bit-bang to read word from eeprom */
696 for(i = 31; i >= 0; i--) {
697 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
698 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
699 e100_write_flush(nic); udelay(4);
701 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
702 e100_write_flush(nic); udelay(4);
704 /* Eeprom drives a dummy zero to EEDO after receiving
705 * complete address. Use this to adjust addr_len. */
706 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
707 if(!(ctrl & eedo) && i > 16) {
708 *addr_len -= (i - 16);
712 data = (data << 1) | (ctrl & eedo ? 1 : 0);
716 writeb(0, &nic->csr->eeprom_ctrl_lo);
717 e100_write_flush(nic); udelay(4);
719 return le16_to_cpu(data);
722 /* Load entire EEPROM image into driver cache and validate checksum */
723 static int e100_eeprom_load(struct nic *nic)
725 u16 addr, addr_len = 8, checksum = 0;
727 /* Try reading with an 8-bit addr len to discover actual addr len */
728 e100_eeprom_read(nic, &addr_len, 0);
729 nic->eeprom_wc = 1 << addr_len;
731 for(addr = 0; addr < nic->eeprom_wc; addr++) {
732 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
733 if(addr < nic->eeprom_wc - 1)
734 checksum += cpu_to_le16(nic->eeprom[addr]);
737 /* The checksum, stored in the last word, is calculated such that
738 * the sum of words should be 0xBABA */
739 checksum = le16_to_cpu(0xBABA - checksum);
740 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
741 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
748 /* Save (portion of) driver EEPROM cache to device and update checksum */
749 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
751 u16 addr, addr_len = 8, checksum = 0;
753 /* Try reading with an 8-bit addr len to discover actual addr len */
754 e100_eeprom_read(nic, &addr_len, 0);
755 nic->eeprom_wc = 1 << addr_len;
757 if(start + count >= nic->eeprom_wc)
760 for(addr = start; addr < start + count; addr++)
761 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
763 /* The checksum, stored in the last word, is calculated such that
764 * the sum of words should be 0xBABA */
765 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
766 checksum += cpu_to_le16(nic->eeprom[addr]);
767 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
768 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
769 nic->eeprom[nic->eeprom_wc - 1]);
774 #define E100_WAIT_SCB_TIMEOUT 40
775 static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
781 spin_lock_irqsave(&nic->cmd_lock, flags);
783 /* Previous command is accepted when SCB clears */
784 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
785 if(likely(!readb(&nic->csr->scb.cmd_lo)))
788 if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
791 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
796 if(unlikely(cmd != cuc_resume))
797 writel(dma_addr, &nic->csr->scb.gen_ptr);
798 writeb(cmd, &nic->csr->scb.cmd_lo);
801 spin_unlock_irqrestore(&nic->cmd_lock, flags);
806 static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
807 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
813 spin_lock_irqsave(&nic->cb_lock, flags);
815 if(unlikely(!nic->cbs_avail)) {
821 nic->cb_to_use = cb->next;
825 if(unlikely(!nic->cbs_avail))
828 cb_prepare(nic, cb, skb);
830 /* Order is important otherwise we'll be in a race with h/w:
831 * set S-bit in current first, then clear S-bit in previous. */
832 cb->command |= cpu_to_le16(cb_s);
834 cb->prev->command &= cpu_to_le16(~cb_s);
836 while(nic->cb_to_send != nic->cb_to_use) {
837 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
838 nic->cb_to_send->dma_addr))) {
839 /* Ok, here's where things get sticky. It's
840 * possible that we can't schedule the command
841 * because the controller is too busy, so
842 * let's just queue the command and try again
843 * when another command is scheduled. */
846 nic->cuc_cmd = cuc_resume;
847 nic->cb_to_send = nic->cb_to_send->next;
852 spin_unlock_irqrestore(&nic->cb_lock, flags);
857 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
862 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
864 for(i = 0; i < 100; i++) {
866 if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
871 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
872 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
873 return (u16)data_out;
876 static int mdio_read(struct net_device *netdev, int addr, int reg)
878 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
881 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
883 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
886 static void e100_get_defaults(struct nic *nic)
888 struct param_range rfds = { .min = 64, .max = 256, .count = 64 };
889 struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
891 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
892 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
893 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
894 if(nic->mac == mac_unknown)
895 nic->mac = mac_82557_D100_A;
897 nic->params.rfds = rfds;
898 nic->params.cbs = cbs;
900 /* Quadwords to DMA into FIFO before starting frame transmit */
901 nic->tx_threshold = 0xE0;
903 nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf |
904 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0));
906 /* Template for a freshly allocated RFD */
907 nic->blank_rfd.command = cpu_to_le16(cb_el);
908 nic->blank_rfd.rbd = 0xFFFFFFFF;
909 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
912 nic->mii.phy_id_mask = 0x1F;
913 nic->mii.reg_num_mask = 0x1F;
914 nic->mii.dev = nic->netdev;
915 nic->mii.mdio_read = mdio_read;
916 nic->mii.mdio_write = mdio_write;
919 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
921 struct config *config = &cb->u.config;
922 u8 *c = (u8 *)config;
924 cb->command = cpu_to_le16(cb_config);
926 memset(config, 0, sizeof(struct config));
928 config->byte_count = 0x16; /* bytes in this struct */
929 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
930 config->direct_rx_dma = 0x1; /* reserved */
931 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
932 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
933 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
934 config->tx_underrun_retry = 0x3; /* # of underrun retries */
935 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
937 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
938 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
939 config->ifs = 0x6; /* x16 = inter frame spacing */
940 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
941 config->pad15_1 = 0x1;
942 config->pad15_2 = 0x1;
943 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
944 config->fc_delay_hi = 0x40; /* time delay for fc frame */
945 config->tx_padding = 0x1; /* 1=pad short frames */
946 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
948 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
949 config->pad20_1 = 0x1F;
950 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
951 config->pad21_1 = 0x5;
953 config->adaptive_ifs = nic->adaptive_ifs;
954 config->loopback = nic->loopback;
956 if(nic->mii.force_media && nic->mii.full_duplex)
957 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
959 if(nic->flags & promiscuous || nic->loopback) {
960 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
961 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
962 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
965 if(nic->flags & multicast_all)
966 config->multicast_all = 0x1; /* 1=accept, 0=no */
968 if(!(nic->flags & wol_magic))
969 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
971 if(nic->mac >= mac_82558_D101_A4) {
972 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
973 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
974 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
975 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
976 if(nic->mac >= mac_82559_D101M)
977 config->tno_intr = 0x1; /* TCO stats enable */
979 config->standard_stat_counter = 0x0;
982 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
983 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
984 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
985 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
986 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
987 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
990 static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
993 static const u32 ucode[UCODE_SIZE] = {
994 /* NFS packets are misinterpreted as TCO packets and
995 * incorrectly routed to the BMC over SMBus. This
996 * microcode patch checks the fragmented IP bit in the
997 * NFS/UDP header to distinguish between NFS and TCO. */
998 0x0EF70E36, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF,
999 0x1FFF1FFF, 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000,
1000 0x00906EFD, 0x00900EFD, 0x00E00EF8,
1003 if(nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
1004 for(i = 0; i < UCODE_SIZE; i++)
1005 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1006 cb->command = cpu_to_le16(cb_ucode);
1008 cb->command = cpu_to_le16(cb_nop);
1011 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1012 struct sk_buff *skb)
1014 cb->command = cpu_to_le16(cb_iaaddr);
1015 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1018 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1020 cb->command = cpu_to_le16(cb_dump);
1021 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1022 offsetof(struct mem, dump_buf));
1025 #define NCONFIG_AUTO_SWITCH 0x0080
1026 #define MII_NSC_CONG MII_RESV1
1027 #define NSC_CONG_ENABLE 0x0100
1028 #define NSC_CONG_TXREADY 0x0400
1029 #define ADVERTISE_FC_SUPPORTED 0x0400
1030 static int e100_phy_init(struct nic *nic)
1032 struct net_device *netdev = nic->netdev;
1034 u16 bmcr, stat, id_lo, id_hi, cong;
1036 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1037 for(addr = 0; addr < 32; addr++) {
1038 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1039 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1040 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1041 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1042 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1045 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1049 /* Selected the phy and isolate the rest */
1050 for(addr = 0; addr < 32; addr++) {
1051 if(addr != nic->mii.phy_id) {
1052 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1054 bmcr = mdio_read(netdev, addr, MII_BMCR);
1055 mdio_write(netdev, addr, MII_BMCR,
1056 bmcr & ~BMCR_ISOLATE);
1061 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1062 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1063 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1064 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1066 /* Handle National tx phys */
1067 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1068 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1069 /* Disable congestion control */
1070 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1071 cong |= NSC_CONG_TXREADY;
1072 cong &= ~NSC_CONG_ENABLE;
1073 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1076 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1077 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1078 (nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled)))
1079 /* enable/disable MDI/MDI-X auto-switching */
1080 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1081 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1086 static int e100_hw_init(struct nic *nic)
1092 DPRINTK(HW, ERR, "e100_hw_init\n");
1093 if(!in_interrupt() && (err = e100_self_test(nic)))
1096 if((err = e100_phy_init(nic)))
1098 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1100 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1102 if((err = e100_exec_cb(nic, NULL, e100_load_ucode)))
1104 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1106 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1108 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1109 nic->dma_addr + offsetof(struct mem, stats))))
1111 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1114 e100_disable_irq(nic);
1119 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1121 struct net_device *netdev = nic->netdev;
1122 struct dev_mc_list *list = netdev->mc_list;
1123 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1125 cb->command = cpu_to_le16(cb_multi);
1126 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1127 for(i = 0; list && i < count; i++, list = list->next)
1128 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1132 static void e100_set_multicast_list(struct net_device *netdev)
1134 struct nic *nic = netdev_priv(netdev);
1136 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1137 netdev->mc_count, netdev->flags);
1139 if(netdev->flags & IFF_PROMISC)
1140 nic->flags |= promiscuous;
1142 nic->flags &= ~promiscuous;
1144 if(netdev->flags & IFF_ALLMULTI ||
1145 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1146 nic->flags |= multicast_all;
1148 nic->flags &= ~multicast_all;
1150 e100_exec_cb(nic, NULL, e100_configure);
1151 e100_exec_cb(nic, NULL, e100_multi);
1154 static void e100_update_stats(struct nic *nic)
1156 struct net_device_stats *ns = &nic->net_stats;
1157 struct stats *s = &nic->mem->stats;
1158 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1159 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1162 /* Device's stats reporting may take several microseconds to
1163 * complete, so where always waiting for results of the
1164 * previous command. */
1166 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1168 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1169 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1170 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1171 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1172 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1173 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1174 ns->collisions += nic->tx_collisions;
1175 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1176 le32_to_cpu(s->tx_lost_crs);
1177 ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
1178 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1179 nic->rx_over_length_errors;
1180 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1181 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1182 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1183 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1184 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1185 le32_to_cpu(s->rx_alignment_errors) +
1186 le32_to_cpu(s->rx_short_frame_errors) +
1187 le32_to_cpu(s->rx_cdt_errors);
1188 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1189 nic->tx_single_collisions +=
1190 le32_to_cpu(s->tx_single_collisions);
1191 nic->tx_multiple_collisions +=
1192 le32_to_cpu(s->tx_multiple_collisions);
1193 if(nic->mac >= mac_82558_D101_A4) {
1194 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1195 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1196 nic->rx_fc_unsupported +=
1197 le32_to_cpu(s->fc_rcv_unsupported);
1198 if(nic->mac >= mac_82559_D101M) {
1199 nic->tx_tco_frames +=
1200 le16_to_cpu(s->xmt_tco_frames);
1201 nic->rx_tco_frames +=
1202 le16_to_cpu(s->rcv_tco_frames);
1207 e100_exec_cmd(nic, cuc_dump_reset, 0);
1210 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1212 /* Adjust inter-frame-spacing (IFS) between two transmits if
1213 * we're getting collisions on a half-duplex connection. */
1215 if(duplex == DUPLEX_HALF) {
1216 u32 prev = nic->adaptive_ifs;
1217 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1219 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1220 (nic->tx_frames > min_frames)) {
1221 if(nic->adaptive_ifs < 60)
1222 nic->adaptive_ifs += 5;
1223 } else if (nic->tx_frames < min_frames) {
1224 if(nic->adaptive_ifs >= 5)
1225 nic->adaptive_ifs -= 5;
1227 if(nic->adaptive_ifs != prev)
1228 e100_exec_cb(nic, NULL, e100_configure);
1232 static void e100_watchdog(unsigned long data)
1234 struct nic *nic = (struct nic *)data;
1235 struct ethtool_cmd cmd;
1237 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1239 /* mii library handles link maintenance tasks */
1241 mii_ethtool_gset(&nic->mii, &cmd);
1243 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1244 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1245 cmd.speed == SPEED_100 ? "100" : "10",
1246 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1247 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1248 DPRINTK(LINK, INFO, "link down\n");
1251 mii_check_link(&nic->mii);
1253 /* Software generated interrupt to recover from (rare) Rx
1254 * allocation failure.
1255 * Unfortunately have to use a spinlock to not re-enable interrupts
1256 * accidentally, due to hardware that shares a register between the
1257 * interrupt mask bit and the SW Interrupt generation bit */
1258 spin_lock_irq(&nic->cmd_lock);
1259 writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1260 spin_unlock_irq(&nic->cmd_lock);
1261 e100_write_flush(nic);
1263 e100_update_stats(nic);
1264 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1266 if(nic->mac <= mac_82557_D100_C)
1267 /* Issue a multicast command to workaround a 557 lock up */
1268 e100_set_multicast_list(nic->netdev);
1270 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1271 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1272 nic->flags |= ich_10h_workaround;
1274 nic->flags &= ~ich_10h_workaround;
1276 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1279 static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1280 struct sk_buff *skb)
1282 cb->command = nic->tx_command;
1283 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1284 cb->u.tcb.tcb_byte_count = 0;
1285 cb->u.tcb.threshold = nic->tx_threshold;
1286 cb->u.tcb.tbd_count = 1;
1287 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1288 skb->data, skb->len, PCI_DMA_TODEVICE));
1289 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1292 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1294 struct nic *nic = netdev_priv(netdev);
1297 if(nic->flags & ich_10h_workaround) {
1298 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1299 Issue a NOP command followed by a 1us delay before
1300 issuing the Tx command. */
1301 e100_exec_cmd(nic, cuc_nop, 0);
1305 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1309 /* We queued the skb, but now we're out of space. */
1310 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1311 netif_stop_queue(netdev);
1314 /* This is a hard error - log it. */
1315 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1316 netif_stop_queue(netdev);
1320 netdev->trans_start = jiffies;
1324 static inline int e100_tx_clean(struct nic *nic)
1329 spin_lock(&nic->cb_lock);
1331 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1332 nic->cb_to_clean->status);
1334 /* Clean CBs marked complete */
1335 for(cb = nic->cb_to_clean;
1336 cb->status & cpu_to_le16(cb_complete);
1337 cb = nic->cb_to_clean = cb->next) {
1338 if(likely(cb->skb != NULL)) {
1339 nic->net_stats.tx_packets++;
1340 nic->net_stats.tx_bytes += cb->skb->len;
1342 pci_unmap_single(nic->pdev,
1343 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1344 le16_to_cpu(cb->u.tcb.tbd.size),
1346 dev_kfree_skb_any(cb->skb);
1354 spin_unlock(&nic->cb_lock);
1356 /* Recover from running out of Tx resources in xmit_frame */
1357 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1358 netif_wake_queue(nic->netdev);
1363 static void e100_clean_cbs(struct nic *nic)
1366 while(nic->cbs_avail != nic->params.cbs.count) {
1367 struct cb *cb = nic->cb_to_clean;
1369 pci_unmap_single(nic->pdev,
1370 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1371 le16_to_cpu(cb->u.tcb.tbd.size),
1373 dev_kfree_skb(cb->skb);
1375 nic->cb_to_clean = nic->cb_to_clean->next;
1378 pci_free_consistent(nic->pdev,
1379 sizeof(struct cb) * nic->params.cbs.count,
1380 nic->cbs, nic->cbs_dma_addr);
1384 nic->cuc_cmd = cuc_start;
1385 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1389 static int e100_alloc_cbs(struct nic *nic)
1392 unsigned int i, count = nic->params.cbs.count;
1394 nic->cuc_cmd = cuc_start;
1395 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1398 nic->cbs = pci_alloc_consistent(nic->pdev,
1399 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1403 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1404 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1405 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1407 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1408 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1409 ((i+1) % count) * sizeof(struct cb));
1413 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1414 nic->cbs_avail = count;
1419 static inline void e100_start_receiver(struct nic *nic)
1421 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1422 if(!nic->ru_running && nic->rx_to_clean->skb) {
1423 e100_exec_cmd(nic, ruc_start, nic->rx_to_clean->dma_addr);
1424 nic->ru_running = 1;
1428 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1429 static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1431 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN)))
1434 /* Align, init, and map the RFD. */
1435 rx->skb->dev = nic->netdev;
1436 skb_reserve(rx->skb, NET_IP_ALIGN);
1437 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1438 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1439 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1441 /* Link the RFD to end of RFA by linking previous RFD to
1442 * this one, and clearing EL bit of previous. */
1444 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1445 put_unaligned(cpu_to_le32(rx->dma_addr),
1446 (u32 *)&prev_rfd->link);
1448 prev_rfd->command &= ~cpu_to_le16(cb_el);
1449 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1450 sizeof(struct rfd), PCI_DMA_TODEVICE);
1456 static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1457 unsigned int *work_done, unsigned int work_to_do)
1459 struct sk_buff *skb = rx->skb;
1460 struct rfd *rfd = (struct rfd *)skb->data;
1461 u16 rfd_status, actual_size;
1463 if(unlikely(work_done && *work_done >= work_to_do))
1466 /* Need to sync before taking a peek at cb_complete bit */
1467 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1468 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1469 rfd_status = le16_to_cpu(rfd->status);
1471 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1473 /* If data isn't ready, nothing to indicate */
1474 if(unlikely(!(rfd_status & cb_complete)))
1477 /* Get actual data size */
1478 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1479 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1480 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1483 pci_unmap_single(nic->pdev, rx->dma_addr,
1484 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1486 /* Pull off the RFD and put the actual data (minus eth hdr) */
1487 skb_reserve(skb, sizeof(struct rfd));
1488 skb_put(skb, actual_size);
1489 skb->protocol = eth_type_trans(skb, nic->netdev);
1491 if(unlikely(!(rfd_status & cb_ok))) {
1492 /* Don't indicate if hardware indicates errors */
1493 nic->net_stats.rx_dropped++;
1494 dev_kfree_skb_any(skb);
1495 } else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
1496 /* Don't indicate oversized frames */
1497 nic->rx_over_length_errors++;
1498 nic->net_stats.rx_dropped++;
1499 dev_kfree_skb_any(skb);
1501 nic->net_stats.rx_packets++;
1502 nic->net_stats.rx_bytes += actual_size;
1503 nic->netdev->last_rx = jiffies;
1504 netif_receive_skb(skb);
1514 static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1515 unsigned int work_to_do)
1519 /* Indicate newly arrived packets */
1520 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1521 if(e100_rx_indicate(nic, rx, work_done, work_to_do))
1522 break; /* No more to clean */
1525 /* Alloc new skbs to refill list */
1526 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1527 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1528 break; /* Better luck next time (see watchdog) */
1531 e100_start_receiver(nic);
1534 static void e100_rx_clean_list(struct nic *nic)
1537 unsigned int i, count = nic->params.rfds.count;
1540 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1542 pci_unmap_single(nic->pdev, rx->dma_addr,
1543 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1544 dev_kfree_skb(rx->skb);
1551 nic->rx_to_use = nic->rx_to_clean = NULL;
1552 nic->ru_running = 0;
1555 static int e100_rx_alloc_list(struct nic *nic)
1558 unsigned int i, count = nic->params.rfds.count;
1560 nic->rx_to_use = nic->rx_to_clean = NULL;
1562 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1564 memset(nic->rxs, 0, sizeof(struct rx) * count);
1566 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1567 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1568 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1569 if(e100_rx_alloc_skb(nic, rx)) {
1570 e100_rx_clean_list(nic);
1575 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1580 static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1582 struct net_device *netdev = dev_id;
1583 struct nic *nic = netdev_priv(netdev);
1584 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1586 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1588 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1589 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1592 /* Ack interrupt(s) */
1593 writeb(stat_ack, &nic->csr->scb.stat_ack);
1595 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1596 if(stat_ack & stat_ack_rnr)
1597 nic->ru_running = 0;
1599 e100_disable_irq(nic);
1600 netif_rx_schedule(netdev);
1605 static int e100_poll(struct net_device *netdev, int *budget)
1607 struct nic *nic = netdev_priv(netdev);
1608 unsigned int work_to_do = min(netdev->quota, *budget);
1609 unsigned int work_done = 0;
1612 e100_rx_clean(nic, &work_done, work_to_do);
1613 tx_cleaned = e100_tx_clean(nic);
1615 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1616 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1617 netif_rx_complete(netdev);
1618 e100_enable_irq(nic);
1622 *budget -= work_done;
1623 netdev->quota -= work_done;
1628 #ifdef CONFIG_NET_POLL_CONTROLLER
1629 static void e100_netpoll(struct net_device *netdev)
1631 struct nic *nic = netdev_priv(netdev);
1632 e100_disable_irq(nic);
1633 e100_intr(nic->pdev->irq, netdev, NULL);
1634 e100_enable_irq(nic);
1638 static struct net_device_stats *e100_get_stats(struct net_device *netdev)
1640 struct nic *nic = netdev_priv(netdev);
1641 return &nic->net_stats;
1644 static int e100_set_mac_address(struct net_device *netdev, void *p)
1646 struct nic *nic = netdev_priv(netdev);
1647 struct sockaddr *addr = p;
1649 if (!is_valid_ether_addr(addr->sa_data))
1650 return -EADDRNOTAVAIL;
1652 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1653 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
1658 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1660 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1662 netdev->mtu = new_mtu;
1666 static int e100_asf(struct nic *nic)
1668 /* ASF can be enabled from eeprom */
1669 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
1670 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
1671 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1672 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1675 static int e100_up(struct nic *nic)
1679 if((err = e100_rx_alloc_list(nic)))
1681 if((err = e100_alloc_cbs(nic)))
1682 goto err_rx_clean_list;
1683 if((err = e100_hw_init(nic)))
1685 e100_set_multicast_list(nic->netdev);
1686 e100_start_receiver(nic);
1687 mod_timer(&nic->watchdog, jiffies);
1688 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
1689 nic->netdev->name, nic->netdev)))
1691 e100_enable_irq(nic);
1692 netif_wake_queue(nic->netdev);
1696 del_timer_sync(&nic->watchdog);
1698 e100_clean_cbs(nic);
1700 e100_rx_clean_list(nic);
1704 static void e100_down(struct nic *nic)
1707 free_irq(nic->pdev->irq, nic->netdev);
1708 del_timer_sync(&nic->watchdog);
1709 netif_carrier_off(nic->netdev);
1710 netif_stop_queue(nic->netdev);
1711 e100_clean_cbs(nic);
1712 e100_rx_clean_list(nic);
1715 static void e100_tx_timeout(struct net_device *netdev)
1717 struct nic *nic = netdev_priv(netdev);
1719 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
1720 readb(&nic->csr->scb.status));
1721 e100_down(netdev_priv(netdev));
1722 e100_up(netdev_priv(netdev));
1725 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
1728 struct sk_buff *skb;
1730 /* Use driver resources to perform internal MAC or PHY
1731 * loopback test. A single packet is prepared and transmitted
1732 * in loopback mode, and the test passes if the received
1733 * packet compares byte-for-byte to the transmitted packet. */
1735 if((err = e100_rx_alloc_list(nic)))
1737 if((err = e100_alloc_cbs(nic)))
1740 /* ICH PHY loopback is broken so do MAC loopback instead */
1741 if(nic->flags & ich && loopback_mode == lb_phy)
1742 loopback_mode = lb_mac;
1744 nic->loopback = loopback_mode;
1745 if((err = e100_hw_init(nic)))
1746 goto err_loopback_none;
1748 if(loopback_mode == lb_phy)
1749 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
1752 e100_start_receiver(nic);
1754 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
1756 goto err_loopback_none;
1758 skb_put(skb, ETH_DATA_LEN);
1759 memset(skb->data, 0xFF, ETH_DATA_LEN);
1760 e100_xmit_frame(skb, nic->netdev);
1762 set_current_state(TASK_UNINTERRUPTIBLE);
1763 schedule_timeout(HZ / 100 + 1);
1765 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1766 skb->data, ETH_DATA_LEN))
1770 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
1771 nic->loopback = lb_none;
1773 e100_clean_cbs(nic);
1775 e100_rx_clean_list(nic);
1779 #define MII_LED_CONTROL 0x1B
1780 static void e100_blink_led(unsigned long data)
1782 struct nic *nic = (struct nic *)data;
1790 nic->leds = (nic->leds & led_on) ? led_off :
1791 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
1792 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
1793 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
1796 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1798 struct nic *nic = netdev_priv(netdev);
1799 return mii_ethtool_gset(&nic->mii, cmd);
1802 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1804 struct nic *nic = netdev_priv(netdev);
1807 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
1808 err = mii_ethtool_sset(&nic->mii, cmd);
1809 e100_exec_cb(nic, NULL, e100_configure);
1814 static void e100_get_drvinfo(struct net_device *netdev,
1815 struct ethtool_drvinfo *info)
1817 struct nic *nic = netdev_priv(netdev);
1818 strcpy(info->driver, DRV_NAME);
1819 strcpy(info->version, DRV_VERSION);
1820 strcpy(info->fw_version, "N/A");
1821 strcpy(info->bus_info, pci_name(nic->pdev));
1824 static int e100_get_regs_len(struct net_device *netdev)
1826 struct nic *nic = netdev_priv(netdev);
1827 #define E100_PHY_REGS 0x1C
1828 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
1829 sizeof(nic->mem->dump_buf) / sizeof(u32)
1830 return E100_REGS_LEN * sizeof(u32);
1833 static void e100_get_regs(struct net_device *netdev,
1834 struct ethtool_regs *regs, void *p)
1836 struct nic *nic = netdev_priv(netdev);
1840 regs->version = (1 << 24) | nic->rev_id;
1841 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
1842 readb(&nic->csr->scb.cmd_lo) << 16 |
1843 readw(&nic->csr->scb.status);
1844 for(i = E100_PHY_REGS; i >= 0; i--)
1845 buff[1 + E100_PHY_REGS - i] =
1846 mdio_read(netdev, nic->mii.phy_id, i);
1847 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
1848 e100_exec_cb(nic, NULL, e100_dump);
1849 set_current_state(TASK_UNINTERRUPTIBLE);
1850 schedule_timeout(HZ / 100 + 1);
1851 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
1852 sizeof(nic->mem->dump_buf));
1855 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1857 struct nic *nic = netdev_priv(netdev);
1858 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
1859 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
1862 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1864 struct nic *nic = netdev_priv(netdev);
1866 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
1870 nic->flags |= wol_magic;
1872 nic->flags &= ~wol_magic;
1874 pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
1875 e100_exec_cb(nic, NULL, e100_configure);
1880 static u32 e100_get_msglevel(struct net_device *netdev)
1882 struct nic *nic = netdev_priv(netdev);
1883 return nic->msg_enable;
1886 static void e100_set_msglevel(struct net_device *netdev, u32 value)
1888 struct nic *nic = netdev_priv(netdev);
1889 nic->msg_enable = value;
1892 static int e100_nway_reset(struct net_device *netdev)
1894 struct nic *nic = netdev_priv(netdev);
1895 return mii_nway_restart(&nic->mii);
1898 static u32 e100_get_link(struct net_device *netdev)
1900 struct nic *nic = netdev_priv(netdev);
1901 return mii_link_ok(&nic->mii);
1904 static int e100_get_eeprom_len(struct net_device *netdev)
1906 struct nic *nic = netdev_priv(netdev);
1907 return nic->eeprom_wc << 1;
1910 #define E100_EEPROM_MAGIC 0x1234
1911 static int e100_get_eeprom(struct net_device *netdev,
1912 struct ethtool_eeprom *eeprom, u8 *bytes)
1914 struct nic *nic = netdev_priv(netdev);
1916 eeprom->magic = E100_EEPROM_MAGIC;
1917 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
1922 static int e100_set_eeprom(struct net_device *netdev,
1923 struct ethtool_eeprom *eeprom, u8 *bytes)
1925 struct nic *nic = netdev_priv(netdev);
1927 if(eeprom->magic != E100_EEPROM_MAGIC)
1930 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
1932 return e100_eeprom_save(nic, eeprom->offset >> 1,
1933 (eeprom->len >> 1) + 1);
1936 static void e100_get_ringparam(struct net_device *netdev,
1937 struct ethtool_ringparam *ring)
1939 struct nic *nic = netdev_priv(netdev);
1940 struct param_range *rfds = &nic->params.rfds;
1941 struct param_range *cbs = &nic->params.cbs;
1943 ring->rx_max_pending = rfds->max;
1944 ring->tx_max_pending = cbs->max;
1945 ring->rx_mini_max_pending = 0;
1946 ring->rx_jumbo_max_pending = 0;
1947 ring->rx_pending = rfds->count;
1948 ring->tx_pending = cbs->count;
1949 ring->rx_mini_pending = 0;
1950 ring->rx_jumbo_pending = 0;
1953 static int e100_set_ringparam(struct net_device *netdev,
1954 struct ethtool_ringparam *ring)
1956 struct nic *nic = netdev_priv(netdev);
1957 struct param_range *rfds = &nic->params.rfds;
1958 struct param_range *cbs = &nic->params.cbs;
1960 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1963 if(netif_running(netdev))
1965 rfds->count = max(ring->rx_pending, rfds->min);
1966 rfds->count = min(rfds->count, rfds->max);
1967 cbs->count = max(ring->tx_pending, cbs->min);
1968 cbs->count = min(cbs->count, cbs->max);
1969 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
1970 rfds->count, cbs->count);
1971 if(netif_running(netdev))
1977 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
1978 "Link test (on/offline)",
1979 "Eeprom test (on/offline)",
1980 "Self test (offline)",
1981 "Mac loopback (offline)",
1982 "Phy loopback (offline)",
1984 #define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
1986 static int e100_diag_test_count(struct net_device *netdev)
1988 return E100_TEST_LEN;
1991 static void e100_diag_test(struct net_device *netdev,
1992 struct ethtool_test *test, u64 *data)
1994 struct ethtool_cmd cmd;
1995 struct nic *nic = netdev_priv(netdev);
1998 memset(data, 0, E100_TEST_LEN * sizeof(u64));
1999 data[0] = !mii_link_ok(&nic->mii);
2000 data[1] = e100_eeprom_load(nic);
2001 if(test->flags & ETH_TEST_FL_OFFLINE) {
2003 /* save speed, duplex & autoneg settings */
2004 err = mii_ethtool_gset(&nic->mii, &cmd);
2006 if(netif_running(netdev))
2008 data[2] = e100_self_test(nic);
2009 data[3] = e100_loopback_test(nic, lb_mac);
2010 data[4] = e100_loopback_test(nic, lb_phy);
2012 /* restore speed, duplex & autoneg settings */
2013 err = mii_ethtool_sset(&nic->mii, &cmd);
2015 if(netif_running(netdev))
2018 for(i = 0; i < E100_TEST_LEN; i++)
2019 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2022 static int e100_phys_id(struct net_device *netdev, u32 data)
2024 struct nic *nic = netdev_priv(netdev);
2026 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2027 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2028 mod_timer(&nic->blink_timer, jiffies);
2029 set_current_state(TASK_INTERRUPTIBLE);
2030 schedule_timeout(data * HZ);
2031 del_timer_sync(&nic->blink_timer);
2032 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2037 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2038 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2039 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2040 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2041 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2042 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2043 "tx_heartbeat_errors", "tx_window_errors",
2044 /* device-specific stats */
2045 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2046 "tx_flow_control_pause", "rx_flow_control_pause",
2047 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2049 #define E100_NET_STATS_LEN 21
2050 #define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2052 static int e100_get_stats_count(struct net_device *netdev)
2054 return E100_STATS_LEN;
2057 static void e100_get_ethtool_stats(struct net_device *netdev,
2058 struct ethtool_stats *stats, u64 *data)
2060 struct nic *nic = netdev_priv(netdev);
2063 for(i = 0; i < E100_NET_STATS_LEN; i++)
2064 data[i] = ((unsigned long *)&nic->net_stats)[i];
2066 data[i++] = nic->tx_deferred;
2067 data[i++] = nic->tx_single_collisions;
2068 data[i++] = nic->tx_multiple_collisions;
2069 data[i++] = nic->tx_fc_pause;
2070 data[i++] = nic->rx_fc_pause;
2071 data[i++] = nic->rx_fc_unsupported;
2072 data[i++] = nic->tx_tco_frames;
2073 data[i++] = nic->rx_tco_frames;
2076 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2080 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2083 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2088 static struct ethtool_ops e100_ethtool_ops = {
2089 .get_settings = e100_get_settings,
2090 .set_settings = e100_set_settings,
2091 .get_drvinfo = e100_get_drvinfo,
2092 .get_regs_len = e100_get_regs_len,
2093 .get_regs = e100_get_regs,
2094 .get_wol = e100_get_wol,
2095 .set_wol = e100_set_wol,
2096 .get_msglevel = e100_get_msglevel,
2097 .set_msglevel = e100_set_msglevel,
2098 .nway_reset = e100_nway_reset,
2099 .get_link = e100_get_link,
2100 .get_eeprom_len = e100_get_eeprom_len,
2101 .get_eeprom = e100_get_eeprom,
2102 .set_eeprom = e100_set_eeprom,
2103 .get_ringparam = e100_get_ringparam,
2104 .set_ringparam = e100_set_ringparam,
2105 .self_test_count = e100_diag_test_count,
2106 .self_test = e100_diag_test,
2107 .get_strings = e100_get_strings,
2108 .phys_id = e100_phys_id,
2109 .get_stats_count = e100_get_stats_count,
2110 .get_ethtool_stats = e100_get_ethtool_stats,
2113 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2115 struct nic *nic = netdev_priv(netdev);
2117 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2120 static int e100_alloc(struct nic *nic)
2122 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2124 return nic->mem ? 0 : -ENOMEM;
2127 static void e100_free(struct nic *nic)
2130 pci_free_consistent(nic->pdev, sizeof(struct mem),
2131 nic->mem, nic->dma_addr);
2136 static int e100_open(struct net_device *netdev)
2138 struct nic *nic = netdev_priv(netdev);
2141 netif_carrier_off(netdev);
2142 if((err = e100_up(nic)))
2143 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2147 static int e100_close(struct net_device *netdev)
2149 e100_down(netdev_priv(netdev));
2153 static int __devinit e100_probe(struct pci_dev *pdev,
2154 const struct pci_device_id *ent)
2156 struct net_device *netdev;
2160 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2161 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2162 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2166 netdev->open = e100_open;
2167 netdev->stop = e100_close;
2168 netdev->hard_start_xmit = e100_xmit_frame;
2169 netdev->get_stats = e100_get_stats;
2170 netdev->set_multicast_list = e100_set_multicast_list;
2171 netdev->set_mac_address = e100_set_mac_address;
2172 netdev->change_mtu = e100_change_mtu;
2173 netdev->do_ioctl = e100_do_ioctl;
2174 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2175 netdev->tx_timeout = e100_tx_timeout;
2176 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2177 netdev->poll = e100_poll;
2178 netdev->weight = E100_NAPI_WEIGHT;
2179 #ifdef CONFIG_NET_POLL_CONTROLLER
2180 netdev->poll_controller = e100_netpoll;
2182 strcpy(netdev->name, pci_name(pdev));
2184 nic = netdev_priv(netdev);
2185 nic->netdev = netdev;
2187 nic->msg_enable = (1 << debug) - 1;
2188 pci_set_drvdata(pdev, netdev);
2190 if((err = pci_enable_device(pdev))) {
2191 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2192 goto err_out_free_dev;
2195 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2196 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2197 "base address, aborting.\n");
2199 goto err_out_disable_pdev;
2202 if((err = pci_request_regions(pdev, DRV_NAME))) {
2203 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2204 goto err_out_disable_pdev;
2207 if((err = pci_set_dma_mask(pdev, 0xFFFFFFFFULL))) {
2208 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2209 goto err_out_free_res;
2212 SET_MODULE_OWNER(netdev);
2213 SET_NETDEV_DEV(netdev, &pdev->dev);
2215 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2217 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2219 goto err_out_free_res;
2222 if(ent->driver_data)
2227 e100_get_defaults(nic);
2229 spin_lock_init(&nic->cb_lock);
2230 spin_lock_init(&nic->cmd_lock);
2232 /* Reset the device before pci_set_master() in case device is in some
2233 * funky state and has an interrupt pending - hint: we don't have the
2234 * interrupt handler registered yet. */
2237 pci_set_master(pdev);
2239 init_timer(&nic->watchdog);
2240 nic->watchdog.function = e100_watchdog;
2241 nic->watchdog.data = (unsigned long)nic;
2242 init_timer(&nic->blink_timer);
2243 nic->blink_timer.function = e100_blink_led;
2244 nic->blink_timer.data = (unsigned long)nic;
2246 if((err = e100_alloc(nic))) {
2247 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2248 goto err_out_iounmap;
2253 if((err = e100_eeprom_load(nic)))
2256 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2257 if(!is_valid_ether_addr(netdev->dev_addr)) {
2258 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2259 "EEPROM, aborting.\n");
2264 /* Wol magic packet can be enabled from eeprom */
2265 if((nic->mac >= mac_82558_D101_A4) &&
2266 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2267 nic->flags |= wol_magic;
2269 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2271 strcpy(netdev->name, "eth%d");
2272 if((err = register_netdev(netdev))) {
2273 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2277 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2278 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2279 pci_resource_start(pdev, 0), pdev->irq,
2280 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2281 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2290 pci_release_regions(pdev);
2291 err_out_disable_pdev:
2292 pci_disable_device(pdev);
2294 pci_set_drvdata(pdev, NULL);
2295 free_netdev(netdev);
2299 static void __devexit e100_remove(struct pci_dev *pdev)
2301 struct net_device *netdev = pci_get_drvdata(pdev);
2304 struct nic *nic = netdev_priv(netdev);
2305 unregister_netdev(netdev);
2308 free_netdev(netdev);
2309 pci_release_regions(pdev);
2310 pci_disable_device(pdev);
2311 pci_set_drvdata(pdev, NULL);
2316 static int e100_suspend(struct pci_dev *pdev, u32 state)
2318 struct net_device *netdev = pci_get_drvdata(pdev);
2319 struct nic *nic = netdev_priv(netdev);
2321 if(netif_running(netdev))
2324 netif_device_detach(netdev);
2326 pci_save_state(pdev);
2327 pci_enable_wake(pdev, state, nic->flags & (wol_magic | e100_asf(nic)));
2328 pci_disable_device(pdev);
2329 pci_set_power_state(pdev, state);
2334 static int e100_resume(struct pci_dev *pdev)
2336 struct net_device *netdev = pci_get_drvdata(pdev);
2337 struct nic *nic = netdev_priv(netdev);
2339 pci_set_power_state(pdev, 0);
2340 pci_restore_state(pdev);
2343 netif_device_attach(netdev);
2344 if(netif_running(netdev))
2351 static struct pci_driver e100_driver = {
2353 .id_table = e100_id_table,
2354 .probe = e100_probe,
2355 .remove = __devexit_p(e100_remove),
2357 .suspend = e100_suspend,
2358 .resume = e100_resume,
2362 static int __init e100_init_module(void)
2364 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2365 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2366 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2368 return pci_module_init(&e100_driver);
2371 static void __exit e100_cleanup_module(void)
2373 pci_unregister_driver(&e100_driver);
2376 module_init(e100_init_module);
2377 module_exit(e100_cleanup_module);